diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
| commit | 2823982a3cbd60a1b21db1a73b78440468df158a (patch) | |
| tree | b955647023da451506138be5a325dfaa2bfd8ee5 /tests/long | |
| parent | 9fb93e5cd226ca928ef9cd45bcefcbd94649f4ea (diff) | |
| download | gem5-2823982a3cbd60a1b21db1a73b78440468df158a.tar.xz | |
stats: updates due to changes to ticksToCycles()
Diffstat (limited to 'tests/long')
58 files changed, 27468 insertions, 24244 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index dfd7f9bb3..38f343beb 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -13,15 +15,16 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/dist/m5/system/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console +eventq_index=0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -39,6 +42,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 @@ -48,6 +52,7 @@ slave=system.membus.master[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -79,6 +84,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -143,6 +150,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -158,6 +166,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -180,26 +189,31 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu0.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 +eventq_index=0 [system.cpu0.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu0.fuPool.FUList0.opList [system.cpu0.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -208,16 +222,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 [system.cpu0.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu0.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -226,22 +243,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 [system.cpu0.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu0.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu0.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -250,22 +271,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 [system.cpu0.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu0.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu0.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -274,10 +299,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList4.opList [system.cpu0.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -286,124 +313,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 [system.cpu0.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu0.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu0.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu0.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu0.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu0.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu0.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu0.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu0.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu0.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu0.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu0.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu0.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu0.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu0.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu0.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu0.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu0.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -412,10 +460,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList6.opList [system.cpu0.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -424,16 +474,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 [system.cpu0.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu0.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -442,10 +495,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu0.fuPool.FUList8.opList [system.cpu0.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -456,6 +511,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -478,21 +534,26 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu0.isa] type=AlphaISA +eventq_index=0 [system.cpu0.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=DerivO3CPU @@ -523,6 +584,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -587,6 +650,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -602,6 +666,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -624,26 +689,31 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu1.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 +eventq_index=0 [system.cpu1.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu1.fuPool.FUList0.opList [system.cpu1.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -652,16 +722,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 [system.cpu1.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu1.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -670,22 +743,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 [system.cpu1.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu1.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu1.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -694,22 +771,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 [system.cpu1.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu1.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu1.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -718,10 +799,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList4.opList [system.cpu1.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -730,124 +813,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 [system.cpu1.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu1.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu1.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu1.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu1.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu1.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu1.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu1.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu1.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu1.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu1.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu1.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu1.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu1.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu1.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu1.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu1.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu1.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -856,10 +960,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList6.opList [system.cpu1.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -868,16 +974,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 [system.cpu1.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu1.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -886,10 +995,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu1.fuPool.FUList8.opList [system.cpu1.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -900,6 +1011,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -922,25 +1034,31 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu1.isa] type=AlphaISA +eventq_index=0 [system.cpu1.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.disk0] @@ -948,19 +1066,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk0.image [system.disk0.image] type=CowDiskImage children=child child=system.disk0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -968,28 +1089,33 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk2.image [system.disk2.image] type=CowDiskImage children=child child=system.disk2.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -1003,6 +1129,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -1025,6 +1152,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -1034,6 +1162,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -1056,6 +1185,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -1063,6 +1193,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1074,6 +1205,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1100,6 +1232,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -1111,29 +1244,35 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[1] [system.simple_disk] type=SimpleDisk children=disk disk=system.simple_disk.disk +eventq_index=0 system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1142,6 +1281,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1152,6 +1292,7 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +eventq_index=0 intrctrl=system.intrctrl system=system @@ -1160,6 +1301,7 @@ type=AlphaBackdoor clk_domain=system.clk_domain cpu=system.cpu0 disk=system.simple_disk +eventq_index=0 pio_addr=8804682956800 pio_latency=100000 platform=system.tsunami @@ -1170,6 +1312,7 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8803072344064 pio_latency=100000 system=system @@ -1198,6 +1341,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=2 Command=0 @@ -1207,8 +1351,40 @@ HeaderType=0 InterruptLine=30 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=52 MinimumGrant=176 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=0 Revision=0 Status=656 @@ -1225,6 +1401,7 @@ dma_read_delay=0 dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 +eventq_index=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 pci_bus=0 @@ -1248,6 +1425,7 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8796093677568 pio_latency=100000 @@ -1265,6 +1443,7 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848432 pio_latency=100000 @@ -1282,6 +1461,7 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848304 pio_latency=100000 @@ -1299,6 +1479,7 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848569 pio_latency=100000 @@ -1316,6 +1497,7 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848451 pio_latency=100000 @@ -1333,6 +1515,7 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848515 pio_latency=100000 @@ -1350,6 +1533,7 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848579 pio_latency=100000 @@ -1367,6 +1551,7 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848643 pio_latency=100000 @@ -1384,6 +1569,7 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848707 pio_latency=100000 @@ -1401,6 +1587,7 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848771 pio_latency=100000 @@ -1418,6 +1605,7 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848835 pio_latency=100000 @@ -1435,6 +1623,7 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848899 pio_latency=100000 @@ -1452,6 +1641,7 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615850617 pio_latency=100000 @@ -1469,6 +1659,7 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848891 pio_latency=100000 @@ -1486,6 +1677,7 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848816 pio_latency=100000 @@ -1503,6 +1695,7 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848696 pio_latency=100000 @@ -1520,6 +1713,7 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848936 pio_latency=100000 @@ -1537,6 +1731,7 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848680 pio_latency=100000 @@ -1554,6 +1749,7 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848944 pio_latency=100000 @@ -1572,6 +1768,7 @@ pio=system.iobus.master[6] type=BadDevice clk_domain=system.clk_domain devicename=FrameBuffer +eventq_index=0 pio_addr=8804615848912 pio_latency=100000 system=system @@ -1599,6 +1796,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -1608,8 +1806,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -1621,6 +1851,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=0 @@ -1635,6 +1866,7 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO clk_domain=system.clk_domain +eventq_index=0 frequency=976562500 pio_addr=8804615847936 pio_latency=100000 @@ -1647,6 +1879,7 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8802535473152 pio_latency=100000 system=system @@ -1657,6 +1890,7 @@ pio=system.iobus.master[1] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.tsunami @@ -1667,6 +1901,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain +eventq_index=0 pio_addr=8804615848952 pio_latency=100000 platform=system.tsunami @@ -1676,5 +1911,6 @@ pio=system.iobus.master[23] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index fc255dc72..3ddbcdbc7 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.904665 # Number of seconds simulated -sim_ticks 1904665099500 # Number of ticks simulated -final_tick 1904665099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.903338 # Number of seconds simulated +sim_ticks 1903338216000 # Number of ticks simulated +final_tick 1903338216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 126318 # Simulator instruction rate (inst/s) -host_op_rate 126318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4285588150 # Simulator tick rate (ticks/s) -host_mem_usage 339596 # Number of bytes of host memory used -host_seconds 444.44 # Real time elapsed on the host -sim_insts 56140339 # Number of instructions simulated -sim_ops 56140339 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 734400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24199744 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 243008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1012480 # Number of bytes read from this memory -system.physmem.bytes_read::total 28839936 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 734400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 243008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977408 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7811840 # Number of bytes written to this memory -system.physmem.bytes_written::total 7811840 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11475 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 378121 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41411 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3797 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 15820 # Number of read requests responded to by this memory -system.physmem.num_reads::total 450624 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122060 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122060 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 385580 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12705511 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1391480 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 127586 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 531579 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15141736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 385580 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 127586 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513165 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4101424 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4101424 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4101424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 385580 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12705511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1391480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 127586 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 531579 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19243160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 450624 # Number of read requests accepted -system.physmem.writeReqs 122060 # Number of write requests accepted -system.physmem.readBursts 450624 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122060 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28836416 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3520 # Total number of bytes read from write queue -system.physmem.bytesWritten 7811520 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28839936 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7811840 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 55 # Number of DRAM read bursts serviced by the write queue +host_inst_rate 100362 # Simulator instruction rate (inst/s) +host_op_rate 100362 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3404824916 # Simulator tick rate (ticks/s) +host_mem_usage 359096 # Number of bytes of host memory used +host_seconds 559.01 # Real time elapsed on the host +sim_insts 56103611 # Number of instructions simulated +sim_ops 56103611 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 740992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24346432 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 236544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 996032 # Number of bytes read from this memory +system.physmem.bytes_read::total 28970176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 740992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 236544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7923904 # Number of bytes written to this memory +system.physmem.bytes_written::total 7923904 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11578 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 380413 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41409 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3696 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 15563 # Number of read requests responded to by this memory +system.physmem.num_reads::total 452659 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123811 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123811 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 389312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12791438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1392383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 124278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 523308 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15220719 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 389312 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 124278 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513590 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4163161 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4163161 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4163161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 389312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12791438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1392383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 124278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 523308 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19383880 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 452659 # Number of read requests accepted +system.physmem.writeReqs 123811 # Number of write requests accepted +system.physmem.readBursts 452659 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123811 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28966400 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3776 # Total number of bytes read from write queue +system.physmem.bytesWritten 7923264 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28970176 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7923904 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 59 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3409 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28171 # Per bank write bursts -system.physmem.perBankRdBursts::1 27944 # Per bank write bursts -system.physmem.perBankRdBursts::2 28133 # Per bank write bursts -system.physmem.perBankRdBursts::3 27978 # Per bank write bursts -system.physmem.perBankRdBursts::4 27881 # Per bank write bursts -system.physmem.perBankRdBursts::5 28082 # Per bank write bursts -system.physmem.perBankRdBursts::6 28123 # Per bank write bursts -system.physmem.perBankRdBursts::7 28118 # Per bank write bursts -system.physmem.perBankRdBursts::8 28377 # Per bank write bursts -system.physmem.perBankRdBursts::9 28284 # Per bank write bursts -system.physmem.perBankRdBursts::10 27947 # Per bank write bursts -system.physmem.perBankRdBursts::11 28190 # Per bank write bursts -system.physmem.perBankRdBursts::12 28259 # Per bank write bursts -system.physmem.perBankRdBursts::13 28280 # Per bank write bursts -system.physmem.perBankRdBursts::14 28300 # Per bank write bursts -system.physmem.perBankRdBursts::15 28502 # Per bank write bursts -system.physmem.perBankWrBursts::0 7913 # Per bank write bursts -system.physmem.perBankWrBursts::1 7477 # Per bank write bursts -system.physmem.perBankWrBursts::2 7607 # Per bank write bursts -system.physmem.perBankWrBursts::3 7420 # Per bank write bursts -system.physmem.perBankWrBursts::4 7384 # Per bank write bursts -system.physmem.perBankWrBursts::5 7571 # Per bank write bursts -system.physmem.perBankWrBursts::6 7682 # Per bank write bursts -system.physmem.perBankWrBursts::7 7471 # Per bank write bursts -system.physmem.perBankWrBursts::8 7660 # Per bank write bursts -system.physmem.perBankWrBursts::9 7641 # Per bank write bursts -system.physmem.perBankWrBursts::10 7379 # Per bank write bursts -system.physmem.perBankWrBursts::11 7517 # Per bank write bursts -system.physmem.perBankWrBursts::12 7673 # Per bank write bursts -system.physmem.perBankWrBursts::13 7762 # Per bank write bursts -system.physmem.perBankWrBursts::14 7923 # Per bank write bursts -system.physmem.perBankWrBursts::15 7975 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 3474 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28542 # Per bank write bursts +system.physmem.perBankRdBursts::1 28115 # Per bank write bursts +system.physmem.perBankRdBursts::2 28449 # Per bank write bursts +system.physmem.perBankRdBursts::3 28319 # Per bank write bursts +system.physmem.perBankRdBursts::4 28001 # Per bank write bursts +system.physmem.perBankRdBursts::5 28388 # Per bank write bursts +system.physmem.perBankRdBursts::6 28437 # Per bank write bursts +system.physmem.perBankRdBursts::7 28681 # Per bank write bursts +system.physmem.perBankRdBursts::8 28670 # Per bank write bursts +system.physmem.perBankRdBursts::9 28576 # Per bank write bursts +system.physmem.perBankRdBursts::10 28034 # Per bank write bursts +system.physmem.perBankRdBursts::11 27899 # Per bank write bursts +system.physmem.perBankRdBursts::12 27884 # Per bank write bursts +system.physmem.perBankRdBursts::13 28245 # Per bank write bursts +system.physmem.perBankRdBursts::14 28268 # Per bank write bursts +system.physmem.perBankRdBursts::15 28092 # Per bank write bursts +system.physmem.perBankWrBursts::0 8222 # Per bank write bursts +system.physmem.perBankWrBursts::1 7571 # Per bank write bursts +system.physmem.perBankWrBursts::2 7821 # Per bank write bursts +system.physmem.perBankWrBursts::3 7782 # Per bank write bursts +system.physmem.perBankWrBursts::4 7428 # Per bank write bursts +system.physmem.perBankWrBursts::5 7859 # Per bank write bursts +system.physmem.perBankWrBursts::6 7924 # Per bank write bursts +system.physmem.perBankWrBursts::7 7992 # Per bank write bursts +system.physmem.perBankWrBursts::8 7912 # Per bank write bursts +system.physmem.perBankWrBursts::9 7920 # Per bank write bursts +system.physmem.perBankWrBursts::10 7418 # Per bank write bursts +system.physmem.perBankWrBursts::11 7297 # Per bank write bursts +system.physmem.perBankWrBursts::12 7319 # Per bank write bursts +system.physmem.perBankWrBursts::13 7829 # Per bank write bursts +system.physmem.perBankWrBursts::14 7922 # Per bank write bursts +system.physmem.perBankWrBursts::15 7585 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 12 # Number of times write queue was full causing retry -system.physmem.totGap 1904663535000 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 1903333578000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 450624 # Read request sizes (log2) +system.physmem.readPktSize::6 452659 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 122060 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 322714 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66953 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 33909 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2356 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 970 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see +system.physmem.writePktSize::6 123811 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 323009 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 67548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 34699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6478 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1342 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 975 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 959 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 951 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 952 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 951 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 955 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -141,458 +141,451 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 46334 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 790.933310 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 228.010271 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1879.334417 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 16305 35.19% 35.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6714 14.49% 49.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 4888 10.55% 60.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2813 6.07% 66.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1747 3.77% 70.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1443 3.11% 73.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1071 2.31% 75.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 878 1.89% 77.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 653 1.41% 78.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 584 1.26% 80.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 640 1.38% 81.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 489 1.06% 82.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 295 0.64% 83.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 293 0.63% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 217 0.47% 84.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 380 0.82% 85.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 150 0.32% 85.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 199 0.43% 85.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 125 0.27% 86.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 135 0.29% 86.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 141 0.30% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 397 0.86% 87.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 230 0.50% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 690 1.49% 89.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 125 0.27% 89.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 87 0.19% 89.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 68 0.15% 90.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 129 0.28% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 56 0.12% 90.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 91 0.20% 90.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 45 0.10% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 78 0.17% 90.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 66 0.14% 91.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 92 0.20% 91.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 29 0.06% 91.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 29 0.06% 91.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 53 0.11% 91.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 51 0.11% 91.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 26 0.06% 91.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 27 0.06% 91.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 25 0.05% 91.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 53 0.11% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 52 0.11% 92.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 16 0.03% 92.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 30 0.06% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 83 0.18% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 42 0.09% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 33 0.07% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 42 0.09% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 86 0.19% 92.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 27 0.06% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 14 0.03% 92.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 51 0.11% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 53 0.11% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 26 0.06% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 25 0.05% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 24 0.05% 93.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 50 0.11% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 51 0.11% 93.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 12 0.03% 93.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 28 0.06% 93.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 84 0.18% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 42 0.09% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 31 0.07% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 39 0.08% 93.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 87 0.19% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 25 0.05% 94.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 14 0.03% 94.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 55 0.12% 94.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 50 0.11% 94.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 24 0.05% 94.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 21 0.05% 94.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 23 0.05% 94.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 49 0.11% 94.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 50 0.11% 94.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 11 0.02% 94.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 26 0.06% 94.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 86 0.19% 95.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 41 0.09% 95.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 30 0.06% 95.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 38 0.08% 95.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 84 0.18% 95.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 26 0.06% 95.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 9 0.02% 95.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 54 0.12% 95.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 52 0.11% 95.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 23 0.05% 95.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 22 0.05% 95.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 22 0.05% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 49 0.11% 96.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 50 0.11% 96.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 9 0.02% 96.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 25 0.05% 96.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 85 0.18% 96.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 39 0.08% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 31 0.07% 96.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 44 0.09% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 84 0.18% 96.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 24 0.05% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 9 0.02% 96.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 51 0.11% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 50 0.11% 97.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 23 0.05% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 20 0.04% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 23 0.05% 97.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 51 0.11% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 49 0.11% 97.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 7 0.02% 97.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 28 0.06% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 86 0.19% 97.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 45 0.10% 97.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 319 0.69% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.00% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 8 0.02% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 15 0.03% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 1 0.00% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 7 0.02% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 1 0.00% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 2 0.00% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 319 0.69% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 2 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 3 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 2 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 3 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11971 4 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 2 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12803 3 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12867 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12931 3 0.01% 99.47% # Bytes accessed per row activation +system.physmem.wrQLenPdf::31 24 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 47120 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 782.856367 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 226.112166 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1866.075506 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 16751 35.55% 35.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6847 14.53% 50.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 4876 10.35% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2833 6.01% 66.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1808 3.84% 70.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1449 3.08% 73.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1103 2.34% 75.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 806 1.71% 77.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 633 1.34% 78.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 628 1.33% 80.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 650 1.38% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 508 1.08% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 311 0.66% 83.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 305 0.65% 83.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 262 0.56% 84.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 366 0.78% 85.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 155 0.33% 85.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 210 0.45% 85.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 130 0.28% 86.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 135 0.29% 86.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 148 0.31% 86.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 388 0.82% 87.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 228 0.48% 88.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 713 1.51% 89.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 124 0.26% 89.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 79 0.17% 90.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 68 0.14% 90.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 140 0.30% 90.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 59 0.13% 90.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 90 0.19% 90.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 49 0.10% 90.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 89 0.19% 91.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 69 0.15% 91.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 88 0.19% 91.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 28 0.06% 91.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 26 0.06% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 54 0.11% 91.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 52 0.11% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 27 0.06% 91.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 28 0.06% 91.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 27 0.06% 91.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 54 0.11% 92.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 53 0.11% 92.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 17 0.04% 92.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 31 0.07% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 83 0.18% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 40 0.08% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 35 0.07% 92.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 42 0.09% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 86 0.18% 92.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 24 0.05% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 15 0.03% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 51 0.11% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 50 0.11% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 24 0.05% 93.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 22 0.05% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 24 0.05% 93.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 52 0.11% 93.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 51 0.11% 93.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 12 0.03% 93.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 29 0.06% 93.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 84 0.18% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 41 0.09% 93.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 31 0.07% 94.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 38 0.08% 94.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 87 0.18% 94.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 24 0.05% 94.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 17 0.04% 94.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 52 0.11% 94.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 51 0.11% 94.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 24 0.05% 94.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 22 0.05% 94.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 23 0.05% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 50 0.11% 94.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 51 0.11% 94.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 12 0.03% 94.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 27 0.06% 95.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 86 0.18% 95.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 41 0.09% 95.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 30 0.06% 95.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 39 0.08% 95.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 84 0.18% 95.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 24 0.05% 95.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 9 0.02% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 53 0.11% 95.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 50 0.11% 95.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 23 0.05% 95.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 22 0.05% 95.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 22 0.05% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 49 0.10% 96.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 50 0.11% 96.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 9 0.02% 96.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 25 0.05% 96.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 85 0.18% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 41 0.09% 96.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 30 0.06% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 42 0.09% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 84 0.18% 96.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 24 0.05% 96.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 10 0.02% 96.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 52 0.11% 97.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 52 0.11% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 24 0.05% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 22 0.05% 97.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 25 0.05% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 49 0.10% 97.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 49 0.10% 97.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 8 0.02% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 27 0.06% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 87 0.18% 97.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 41 0.09% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 317 0.67% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 2 0.00% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 1 0.00% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 6 0.01% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7491 1 0.00% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 14 0.03% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 2 0.00% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 8 0.02% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 1 0.00% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 3 0.01% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 322 0.68% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 2 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 2 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 3 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9731 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 3 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10307 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11331 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11587 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11907 2 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 4 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12483 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 5 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 2 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 3 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 3 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 3 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 38 0.08% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 173 0.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 46334 # Bytes accessed per row activation -system.physmem.totQLat 8608105750 # Total ticks spent queuing -system.physmem.totMemAccLat 16109367000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2252845000 # Total ticks spent in databus transfers -system.physmem.totBankLat 5248416250 # Total ticks spent accessing banks -system.physmem.avgQLat 19104.97 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 11648.42 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 39 0.08% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 175 0.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 47120 # Bytes accessed per row activation +system.physmem.totQLat 8783315250 # Total ticks spent queuing +system.physmem.totMemAccLat 16310447750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2263000000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5264132500 # Total ticks spent accessing banks +system.physmem.avgQLat 19406.35 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11630.87 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35753.39 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.14 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.14 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 36037.22 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.16 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.22 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.16 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.81 # Average write queue length when enqueuing -system.physmem.readRowHits 429097 # Number of row buffer hits during reads -system.physmem.writeRowHits 97193 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.23 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.63 # Row buffer hit rate for writes -system.physmem.avgGap 3325854.28 # Average gap between requests -system.physmem.pageHitRate 91.91 # Row buffer hit rate, read and write combined +system.physmem.avgWrQLen 9.32 # Average write queue length when enqueuing +system.physmem.readRowHits 430734 # Number of row buffer hits during reads +system.physmem.writeRowHits 98547 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.17 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.59 # Row buffer hit rate for writes +system.physmem.avgGap 3301704.47 # Average gap between requests +system.physmem.pageHitRate 91.82 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 19299112 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296504 # Transaction distribution -system.membus.trans_dist::ReadResp 296255 # Transaction distribution -system.membus.trans_dist::WriteReq 12358 # Transaction distribution -system.membus.trans_dist::WriteResp 12358 # Transaction distribution -system.membus.trans_dist::Writeback 122060 # Transaction distribution -system.membus.trans_dist::UpgradeReq 5288 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1522 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3409 # Transaction distribution -system.membus.trans_dist::ReadExReq 162296 # Transaction distribution -system.membus.trans_dist::ReadExResp 162161 # Transaction distribution +system.membus.throughput 19439855 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296479 # Transaction distribution +system.membus.trans_dist::ReadResp 296230 # Transaction distribution +system.membus.trans_dist::WriteReq 12351 # Transaction distribution +system.membus.trans_dist::WriteResp 12351 # Transaction distribution +system.membus.trans_dist::Writeback 123811 # Transaction distribution +system.membus.trans_dist::UpgradeReq 5304 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1475 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3474 # Transaction distribution +system.membus.trans_dist::ReadExReq 164353 # Transaction distribution +system.membus.trans_dist::ReadExResp 164224 # Transaction distribution system.membus.trans_dist::BadAddressError 249 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39102 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 909601 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39094 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 915454 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 498 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 949201 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124660 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124660 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1073861 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68234 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31344192 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31412426 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307584 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5307584 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36720010 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36720010 # Total data (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 955046 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124656 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124656 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1079702 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68202 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31586624 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31654826 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307456 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5307456 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36962282 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36962282 # Total data (bytes) system.membus.snoop_data_through_bus 38336 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 36331000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 36252500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1605524497 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1624596499 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 312000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 317500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3818350840 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3836772510 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376337493 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376321991 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 343738 # number of replacements -system.l2c.tags.tagsinuse 65291.635140 # Cycle average of tags in use -system.l2c.tags.total_refs 2609074 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 408707 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.383727 # Average number of references to valid blocks. +system.l2c.tags.replacements 345713 # number of replacements +system.l2c.tags.tagsinuse 65292.619294 # Cycle average of tags in use +system.l2c.tags.total_refs 2607692 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 410924 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.345923 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 7069563750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53622.087129 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4120.650208 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5604.001242 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1368.077401 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 576.819161 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.818208 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.062876 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.085510 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.020875 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008802 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996271 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 744945 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 568804 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 325372 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 253262 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1892383 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 840158 # number of Writeback hits -system.l2c.Writeback_hits::total 840158 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 141 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 87 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 228 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 35 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 143496 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 47101 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 190597 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 744945 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 712300 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 325372 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 300363 # number of demand (read+write) hits -system.l2c.demand_hits::total 2082980 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 744945 # number of overall hits -system.l2c.overall_hits::cpu0.data 712300 # number of overall hits -system.l2c.overall_hits::cpu1.inst 325372 # number of overall hits -system.l2c.overall_hits::cpu1.data 300363 # number of overall hits -system.l2c.overall_hits::total 2082980 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11483 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 272043 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3807 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1819 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289152 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2542 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 549 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3091 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 55 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 155 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 106452 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 14320 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 120772 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 11483 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 378495 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3807 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16139 # number of demand (read+write) misses -system.l2c.demand_misses::total 409924 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11483 # number of overall misses -system.l2c.overall_misses::cpu0.data 378495 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3807 # number of overall misses -system.l2c.overall_misses::cpu1.data 16139 # number of overall misses -system.l2c.overall_misses::total 409924 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 923162249 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17695673499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 318789981 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 142364996 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 19079990725 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 555479 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1281945 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1837424 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 201494 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 69497 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 270991 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8670131391 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1451250197 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10121381588 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 923162249 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 26365804890 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 318789981 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1593615193 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 29201372313 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 923162249 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 26365804890 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 318789981 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1593615193 # number of overall miss cycles -system.l2c.overall_miss_latency::total 29201372313 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 756428 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 840847 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 329179 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 255081 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2181535 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 840158 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 840158 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2683 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 636 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3319 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 90 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 131 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 221 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 249948 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 61421 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 311369 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 756428 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1090795 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 329179 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 316502 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2492904 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 756428 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1090795 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 329179 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 316502 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2492904 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015181 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.323534 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.011565 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.007131 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.132545 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947447 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.863208 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.931305 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.611111 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.763359 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.701357 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.425897 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.233145 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.387874 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015181 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.346990 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.011565 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.050992 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.164436 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015181 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.346990 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.011565 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.050992 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.164436 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80393.821214 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 65047.339939 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83737.846336 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 78265.528312 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 65986.023700 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 218.520456 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2335.054645 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 594.443222 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3663.527273 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 694.970000 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1748.329032 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81446.392656 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 101344.287500 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 83805.696585 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 80393.821214 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 69659.585701 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 83737.846336 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 98743.118719 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 71236.064034 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 80393.821214 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 69659.585701 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 83737.846336 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 98743.118719 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 71236.064034 # average overall miss latency +system.l2c.tags.occ_blocks::writebacks 53648.503329 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4120.078366 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5598.798644 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1365.340117 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 559.898838 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.818611 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.062867 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.085431 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.020833 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008543 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996286 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 754547 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 572386 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 313557 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 249669 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1890159 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 840492 # number of Writeback hits +system.l2c.Writeback_hits::total 840492 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 130 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 74 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 204 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 33 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 70 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 144073 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 44330 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 188403 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 754547 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 716459 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 313557 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 293999 # number of demand (read+write) hits +system.l2c.demand_hits::total 2078562 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 754547 # number of overall hits +system.l2c.overall_hits::cpu0.data 716459 # number of overall hits +system.l2c.overall_hits::cpu1.inst 313557 # number of overall hits +system.l2c.overall_hits::cpu1.data 293999 # number of overall hits +system.l2c.overall_hits::total 2078562 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 11586 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 272059 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 3706 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1775 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289126 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2565 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 587 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3152 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 58 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 107 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 165 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 108741 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 14088 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 122829 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 11586 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 380800 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 3706 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 15863 # number of demand (read+write) misses +system.l2c.demand_misses::total 411955 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11586 # number of overall misses +system.l2c.overall_misses::cpu0.data 380800 # number of overall misses +system.l2c.overall_misses::cpu1.inst 3706 # number of overall misses +system.l2c.overall_misses::cpu1.data 15863 # number of overall misses +system.l2c.overall_misses::total 411955 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 929054999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 17693461250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 314236981 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 144928247 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 19081681477 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 842965 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 1256946 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 2099911 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 221993 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 116495 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 338488 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 8947158383 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1452475204 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10399633587 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 929054999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 26640619633 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 314236981 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1597403451 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 29481315064 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 929054999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 26640619633 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 314236981 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1597403451 # number of overall miss cycles +system.l2c.overall_miss_latency::total 29481315064 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 766133 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 844445 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 317263 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 251444 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2179285 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 840492 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 840492 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2695 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 661 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3356 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 95 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 140 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 235 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 252814 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 58418 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 311232 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 766133 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1097259 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 317263 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 309862 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2490517 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 766133 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1097259 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 317263 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 309862 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2490517 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015123 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.322175 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.011681 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.007059 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.132670 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951763 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.888048 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.939213 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.610526 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.764286 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.702128 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.430123 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.241159 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.394654 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015123 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.347047 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.011681 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.051194 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.165409 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015123 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.347047 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.011681 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.051194 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.165409 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80187.726480 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 65035.382950 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84791.414193 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 81649.716620 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 65997.805376 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 328.641326 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2141.304940 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 666.215419 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3827.465517 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1088.738318 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 2051.442424 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82279.530104 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 103100.170642 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 84667.575141 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 80187.726480 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 69959.610381 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 84791.414193 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 100699.959087 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 71564.406462 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 80187.726480 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 69959.610381 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 84791.414193 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 100699.959087 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 71564.406462 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -601,8 +594,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 80540 # number of writebacks -system.l2c.writebacks::total 80540 # number of writebacks +system.l2c.writebacks::writebacks 82291 # number of writebacks +system.l2c.writebacks::total 82291 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 10 # number of ReadReq MSHR hits @@ -615,111 +608,111 @@ system.l2c.overall_mshr_hits::cpu0.inst 7 # nu system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 11476 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 272042 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 3797 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1819 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 289134 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2542 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 549 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3091 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 55 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 100 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 155 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 106452 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 14320 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 120772 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 11476 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 378494 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 3797 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 16139 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 409906 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 11476 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 378494 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 3797 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 16139 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 409906 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 777853501 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14301350001 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 270265519 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 144194502 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 15493663523 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25563003 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5558045 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 31121048 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 600552 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1003598 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 1604150 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7364952609 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1275013301 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8639965910 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 777853501 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 21666302610 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 270265519 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1419207803 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 24133629433 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 777853501 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 21666302610 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 270265519 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1419207803 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 24133629433 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 929130500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 460152500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1389283000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1572515500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 890654999 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2463170499 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2501646000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1350807499 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 3852453499 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015171 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.323533 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011535 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.007131 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.132537 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.947447 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.863208 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.931305 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.611111 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.763359 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.701357 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.425897 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.233145 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.387874 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015171 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.346989 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011535 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.050992 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.164429 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015171 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.346989 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011535 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.050992 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.164429 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67780.890641 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52570.375166 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71178.698710 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 79271.304013 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 53586.446156 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10056.256098 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10123.943534 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10068.278227 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10919.127273 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10035.980000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10349.354839 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69185.666864 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89037.241690 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 71539.478604 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67780.890641 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57243.450649 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71178.698710 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 87936.539005 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58876.009214 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67780.890641 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57243.450649 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71178.698710 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 87936.539005 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58876.009214 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 11579 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 272058 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 3696 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1775 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 289108 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2565 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 587 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3152 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 58 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 107 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 165 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 108741 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 14088 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 122829 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 11579 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 380799 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 3696 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 15863 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 411937 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 11579 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 380799 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 3696 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 15863 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 411937 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 782519751 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14298950750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 266998019 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 147305751 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 15495774271 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25723531 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5884082 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 31607613 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 641556 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1072106 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 1713662 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7614105115 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1279019296 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8893124411 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 782519751 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 21913055865 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 266998019 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1426325047 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 24388898682 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 782519751 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 21913055865 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 266998019 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1426325047 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 24388898682 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 931434500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 458421000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1389855500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1577498000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 884169000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2461667000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2508932500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1342590000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3851522500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015114 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.322174 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011650 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.007059 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.132662 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.951763 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.888048 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.939213 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.610526 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.764286 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.702128 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.430123 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.241159 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.394654 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015114 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.347046 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011650 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.051194 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.165402 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015114 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.347046 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011650 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.051194 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.165402 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67580.944037 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52558.464555 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72239.723755 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82989.155493 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 53598.566179 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10028.667057 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10023.989779 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10027.796003 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 11061.310345 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10019.682243 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10385.830303 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70020.554483 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 90787.854628 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72402.481588 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67580.944037 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57544.940677 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72239.723755 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 89915.214461 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59205.409279 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67580.944037 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57544.940677 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72239.723755 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 89915.214461 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59205.409279 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -730,39 +723,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41697 # number of replacements -system.iocache.tags.tagsinuse 0.224170 # Cycle average of tags in use +system.iocache.tags.replacements 41695 # number of replacements +system.iocache.tags.tagsinuse 0.213166 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41713 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1712302770000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.224170 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.014011 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.014011 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses -system.iocache.ReadReq_misses::total 177 # number of ReadReq misses +system.iocache.tags.warmup_cycle 1712301131000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.213166 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.013323 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.013323 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses -system.iocache.demand_misses::total 41729 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses -system.iocache.overall_misses::total 41729 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21589383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21589383 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12994516805 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12994516805 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 13016106188 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 13016106188 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 13016106188 # number of overall miss cycles -system.iocache.overall_miss_latency::total 13016106188 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses +system.iocache.demand_misses::total 41727 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses +system.iocache.overall_misses::total 41727 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21368383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21368383 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 13021515788 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 13021515788 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13042884171 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13042884171 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13042884171 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13042884171 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -771,40 +764,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121973.915254 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 121973.915254 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312729.033621 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 312729.033621 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 311919.916317 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 311919.916317 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 311919.916317 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 311919.916317 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 404619 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122105.045714 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122105.045714 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 313378.797362 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 313378.797362 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 312576.609174 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 312576.609174 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 312576.609174 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 312576.609174 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 407057 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 29217 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 29358 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.848752 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.865284 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12384383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12384383 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10832260819 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10832260819 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10844645202 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10844645202 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10844645202 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10844645202 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12267383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12267383 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10859254806 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10859254806 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10871522189 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10871522189 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10871522189 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10871522189 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -813,14 +806,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69968.265537 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 69968.265537 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260691.683168 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 260691.683168 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259882.700328 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 259882.700328 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259882.700328 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 259882.700328 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70099.331429 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70099.331429 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 261341.326675 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 261341.326675 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 260539.271671 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 260539.271671 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 260539.271671 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 260539.271671 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -834,35 +827,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 10889682 # Number of BP lookups -system.cpu0.branchPred.condPredicted 9229516 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 284462 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 7161619 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4680131 # Number of BTB hits +system.cpu0.branchPred.lookups 11006012 # Number of BP lookups +system.cpu0.branchPred.condPredicted 9319545 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 291548 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 7161716 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4729334 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.350181 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 674122 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 25966 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 66.036324 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 682987 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 26515 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7794998 # DTB read hits -system.cpu0.dtb.read_misses 29740 # DTB read misses -system.cpu0.dtb.read_acv 552 # DTB read access violations -system.cpu0.dtb.read_accesses 624038 # DTB read accesses -system.cpu0.dtb.write_hits 5176736 # DTB write hits -system.cpu0.dtb.write_misses 7776 # DTB write misses -system.cpu0.dtb.write_acv 327 # DTB write access violations -system.cpu0.dtb.write_accesses 207382 # DTB write accesses -system.cpu0.dtb.data_hits 12971734 # DTB hits -system.cpu0.dtb.data_misses 37516 # DTB misses -system.cpu0.dtb.data_acv 879 # DTB access violations -system.cpu0.dtb.data_accesses 831420 # DTB accesses -system.cpu0.itb.fetch_hits 929400 # ITB hits -system.cpu0.itb.fetch_misses 28175 # ITB misses -system.cpu0.itb.fetch_acv 908 # ITB acv -system.cpu0.itb.fetch_accesses 957575 # ITB accesses +system.cpu0.dtb.read_hits 7888949 # DTB read hits +system.cpu0.dtb.read_misses 30101 # DTB read misses +system.cpu0.dtb.read_acv 574 # DTB read access violations +system.cpu0.dtb.read_accesses 665608 # DTB read accesses +system.cpu0.dtb.write_hits 5247941 # DTB write hits +system.cpu0.dtb.write_misses 8093 # DTB write misses +system.cpu0.dtb.write_acv 365 # DTB write access violations +system.cpu0.dtb.write_accesses 232480 # DTB write accesses +system.cpu0.dtb.data_hits 13136890 # DTB hits +system.cpu0.dtb.data_misses 38194 # DTB misses +system.cpu0.dtb.data_acv 939 # DTB access violations +system.cpu0.dtb.data_accesses 898088 # DTB accesses +system.cpu0.itb.fetch_hits 973403 # ITB hits +system.cpu0.itb.fetch_misses 31216 # ITB misses +system.cpu0.itb.fetch_acv 1004 # ITB acv +system.cpu0.itb.fetch_accesses 1004619 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -875,269 +868,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 103787820 # number of cpu cycles simulated +system.cpu0.numCycles 104578589 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 21704485 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 55964987 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 10889682 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5354253 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10541115 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1495269 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 32108430 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 29198 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 196165 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 243475 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 129 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6808420 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 194219 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 65778101 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.850815 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.187217 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 21960114 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 56555379 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 11006012 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5412321 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10656012 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1518801 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 32354382 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 30030 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 204805 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 243991 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 103 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6896028 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 198863 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 66418859 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.851496 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.187669 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 55236986 83.97% 83.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 687368 1.04% 85.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1350712 2.05% 87.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 596944 0.91% 87.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2343219 3.56% 91.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 450390 0.68% 92.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 484863 0.74% 92.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 769593 1.17% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3858026 5.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 55762847 83.96% 83.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 696881 1.05% 85.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1363707 2.05% 87.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 607827 0.92% 87.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2362378 3.56% 91.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 460793 0.69% 92.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 493104 0.74% 92.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 775074 1.17% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3896248 5.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 65778101 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.104923 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.539225 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 22868260 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 31583202 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9551685 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 850413 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 924540 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 430365 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 30891 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 54921627 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 95919 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 924540 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 23764379 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12229388 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 16273784 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8983229 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3602779 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 51919548 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6908 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 427524 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1365609 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 34775855 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 63273064 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 63154051 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 110251 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30610760 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4165087 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1306243 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 192817 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 9794386 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 8157712 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5414054 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 996311 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 651476 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 46072688 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1607529 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 45052642 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 77910 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5101692 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2707567 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1088536 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 65778101 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.684919 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.328831 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 66418859 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.105242 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.540793 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 23145338 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 31820288 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9657130 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 858074 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 938028 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 439220 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 31710 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 55497748 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 98418 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 938028 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 24047696 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12280609 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 16434779 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9089203 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3628542 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 52477613 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6876 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 427894 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1374075 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 35152162 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 63950241 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 63830636 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 110747 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30925813 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4226341 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1321793 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 195129 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 9844333 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8256385 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5476723 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1002198 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 667476 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 46574896 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1622063 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 45553168 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 69417 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5159281 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2712846 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1098313 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 66418859 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.685847 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.329893 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 45611929 69.34% 69.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9242272 14.05% 83.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4206709 6.40% 89.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2691383 4.09% 93.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2059923 3.13% 97.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1077701 1.64% 98.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 567124 0.86% 99.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 276618 0.42% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 44442 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 46042875 69.32% 69.32% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9328009 14.04% 83.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4252197 6.40% 89.77% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2720710 4.10% 93.86% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2085310 3.14% 97.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1089347 1.64% 98.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 576580 0.87% 99.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 279468 0.42% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 44363 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 65778101 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 66418859 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 64943 10.84% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 279384 46.63% 57.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 254855 42.53% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 65077 10.66% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 284948 46.66% 57.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 260601 42.68% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3777 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 30907747 68.60% 68.61% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47065 0.10% 68.72% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.72% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 14613 0.03% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.75% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 8107891 18.00% 86.75% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5235503 11.62% 98.37% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 734167 1.63% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 31229788 68.56% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47289 0.10% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 14649 0.03% 68.70% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.70% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.70% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.70% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.71% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8205422 18.01% 86.72% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5307142 11.65% 98.37% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 743210 1.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 45052642 # Type of FU issued -system.cpu0.iq.rate 0.434084 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 599182 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013300 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 156086675 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 52562386 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 44135345 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 473801 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 230205 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 223474 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 45400371 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 247676 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 493959 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 45553168 # Type of FU issued +system.cpu0.iq.rate 0.435588 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 610626 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013405 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 157729759 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 53136035 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 44625486 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 475478 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 231159 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 224228 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 45911492 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 248517 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 497947 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 994643 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3486 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 10933 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 382957 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1006840 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3517 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 11189 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 378910 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 13548 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 145981 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 13584 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 146356 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 924540 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8545801 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 700799 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50460891 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 559365 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 8157712 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5414054 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1419298 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 572111 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4914 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 10933 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 138244 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 310094 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 448338 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 44721018 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 7845228 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 331623 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 938028 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8572601 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 702117 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50999649 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 565079 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8256385 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5476723 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1432117 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 572819 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5269 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 11189 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 141170 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 315582 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 456752 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 45215846 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 7939970 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 337321 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 2780674 # number of nop insts executed -system.cpu0.iew.exec_refs 13041346 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7066025 # Number of branches executed -system.cpu0.iew.exec_stores 5196118 # Number of stores executed -system.cpu0.iew.exec_rate 0.430889 # Inst execution rate -system.cpu0.iew.wb_sent 44442278 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44358819 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 22095606 # num instructions producing a value -system.cpu0.iew.wb_consumers 29563187 # num instructions consuming a value +system.cpu0.iew.exec_nop 2802690 # number of nop insts executed +system.cpu0.iew.exec_refs 13207799 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7146234 # Number of branches executed +system.cpu0.iew.exec_stores 5267829 # Number of stores executed +system.cpu0.iew.exec_rate 0.432362 # Inst execution rate +system.cpu0.iew.wb_sent 44934571 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44849714 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 22315831 # num instructions producing a value +system.cpu0.iew.wb_consumers 29845824 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.427399 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.747403 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.428861 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.747704 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 5494607 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 518993 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 418437 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 64853561 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.691924 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.608025 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 5562563 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 523750 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 426483 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 65480831 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.692465 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.608721 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 47955107 73.94% 73.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7091089 10.93% 84.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3807248 5.87% 90.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2121571 3.27% 94.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1151711 1.78% 95.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 474089 0.73% 96.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 405970 0.63% 97.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 383893 0.59% 97.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1462883 2.26% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 48404249 73.92% 73.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7174588 10.96% 84.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3839849 5.86% 90.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2141053 3.27% 94.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1161993 1.77% 95.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 481151 0.73% 96.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 411214 0.63% 97.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 389126 0.59% 97.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1477608 2.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 64853561 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 44873722 # Number of instructions committed -system.cpu0.commit.committedOps 44873722 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 65480831 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 45343202 # Number of instructions committed +system.cpu0.commit.committedOps 45343202 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 12194166 # Number of memory references committed -system.cpu0.commit.loads 7163069 # Number of loads committed -system.cpu0.commit.membars 173899 # Number of memory barriers committed -system.cpu0.commit.branches 6736138 # Number of branches committed -system.cpu0.commit.fp_insts 221634 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 41596674 # Number of committed integer instructions. -system.cpu0.commit.function_calls 557213 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1462883 # number cycles where commit BW limit reached +system.cpu0.commit.refs 12347358 # Number of memory references committed +system.cpu0.commit.loads 7249545 # Number of loads committed +system.cpu0.commit.membars 175312 # Number of memory barriers committed +system.cpu0.commit.branches 6808554 # Number of branches committed +system.cpu0.commit.fp_insts 222342 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 42040123 # Number of committed integer instructions. +system.cpu0.commit.function_calls 564734 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1477608 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 113567039 # The number of ROB reads -system.cpu0.rob.rob_writes 101661188 # The number of ROB writes -system.cpu0.timesIdled 942687 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 38009719 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3705537551 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 42330060 # Number of Instructions Simulated -system.cpu0.committedOps 42330060 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 42330060 # Number of Instructions Simulated -system.cpu0.cpi 2.451870 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.451870 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.407852 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.407852 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 58864464 # number of integer regfile reads -system.cpu0.int_regfile_writes 32110567 # number of integer regfile writes -system.cpu0.fp_regfile_reads 109878 # number of floating regfile reads -system.cpu0.fp_regfile_writes 110737 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1513799 # number of misc regfile reads -system.cpu0.misc_regfile_writes 739168 # number of misc regfile writes +system.cpu0.rob.rob_reads 114710793 # The number of ROB reads +system.cpu0.rob.rob_writes 102749676 # The number of ROB writes +system.cpu0.timesIdled 949561 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 38159730 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3702093008 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 42781436 # Number of Instructions Simulated +system.cpu0.committedOps 42781436 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 42781436 # Number of Instructions Simulated +system.cpu0.cpi 2.444485 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.444485 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.409084 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.409084 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 59516377 # number of integer regfile reads +system.cpu0.int_regfile_writes 32453910 # number of integer regfile writes +system.cpu0.fp_regfile_reads 110308 # number of floating regfile reads +system.cpu0.fp_regfile_writes 111090 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1526243 # number of misc regfile reads +system.cpu0.misc_regfile_writes 747832 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1169,49 +1162,49 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 112875870 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2213010 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2212746 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12358 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12358 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 840158 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 5353 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1588 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 6941 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 354001 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 312453 # Transaction distribution +system.toL2Bus.throughput 112873708 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2210500 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2210236 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12351 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12351 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 840492 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 5351 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1545 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 6896 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 353777 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 312228 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 249 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1512954 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2808902 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 658389 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 920655 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5900900 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 48411392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 107554025 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 21067456 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 36346017 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 213378890 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 213368266 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 1622464 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5059270351 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1532372 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2827999 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 634560 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 901176 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5896107 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 49032512 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 108336621 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20304832 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 35573309 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 213247274 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 213236842 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 1600000 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5059383343 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 747000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 733500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3408360184 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3452114362 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5017953643 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5048329138 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1482953497 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1429282335 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1519289016 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1486623569 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1433257 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7370 # Transaction distribution -system.iobus.trans_dist::ReadResp 7370 # Transaction distribution -system.iobus.trans_dist::WriteReq 53910 # Transaction distribution -system.iobus.trans_dist::WriteResp 53910 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10510 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 468 # Packet count per connected master and slave (bytes) +system.iobus.throughput 1434231 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7371 # Transaction distribution +system.iobus.trans_dist::ReadResp 7371 # Transaction distribution +system.iobus.trans_dist::WriteReq 53903 # Transaction distribution +system.iobus.trans_dist::WriteResp 53903 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10490 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1222,12 +1215,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83458 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83458 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122560 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42040 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39094 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 122548 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41960 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1238,14 +1231,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 68234 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661640 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661640 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2729874 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2729874 # Total data (bytes) -system.iobus.reqLayer0.occupancy 9865000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 68202 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2729826 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2729826 # Total data (bytes) +system.iobus.reqLayer0.occupancy 9845000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 350000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1265,253 +1258,253 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 377768695 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 377802180 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26744000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26743000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42672507 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42660009 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 755849 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.693536 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6013634 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 756358 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.950777 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 765570 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.693534 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6090993 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 766079 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.950868 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 26716185250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.693536 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.693534 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995495 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.995495 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6013634 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6013634 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6013634 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6013634 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6013634 # number of overall hits -system.cpu0.icache.overall_hits::total 6013634 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 794785 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 794785 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 794785 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 794785 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 794785 # number of overall misses -system.cpu0.icache.overall_misses::total 794785 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11289773018 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11289773018 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11289773018 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11289773018 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11289773018 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11289773018 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6808419 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6808419 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6808419 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6808419 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6808419 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6808419 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116736 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.116736 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116736 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.116736 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116736 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.116736 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14204.813903 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14204.813903 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14204.813903 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14204.813903 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14204.813903 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14204.813903 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5327 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 6090993 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6090993 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6090993 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6090993 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6090993 # number of overall hits +system.cpu0.icache.overall_hits::total 6090993 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 805033 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 805033 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 805033 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 805033 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 805033 # number of overall misses +system.cpu0.icache.overall_misses::total 805033 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11432598915 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11432598915 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11432598915 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11432598915 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11432598915 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11432598915 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6896026 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6896026 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6896026 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6896026 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6896026 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6896026 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116739 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.116739 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116739 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.116739 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116739 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.116739 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14201.404060 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14201.404060 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14201.404060 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14201.404060 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14201.404060 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14201.404060 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4227 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 127 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 138 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 41.944882 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.630435 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 38259 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 38259 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 38259 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 38259 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 38259 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 38259 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 756526 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 756526 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 756526 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 756526 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 756526 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 756526 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9285394312 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9285394312 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9285394312 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9285394312 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9285394312 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9285394312 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111116 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.111116 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.111116 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12273.727951 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12273.727951 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12273.727951 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 38794 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 38794 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 38794 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 38794 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 38794 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 38794 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 766239 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 766239 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 766239 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 766239 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 766239 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 766239 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9400829636 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9400829636 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9400829636 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9400829636 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9400829636 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9400829636 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111113 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111113 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111113 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.111113 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111113 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.111113 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12268.795553 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12268.795553 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12268.795553 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12268.795553 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12268.795553 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12268.795553 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1092682 # number of replacements -system.cpu0.dcache.tags.tagsinuse 465.850340 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9201265 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1093194 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.416864 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1099493 # number of replacements +system.cpu0.dcache.tags.tagsinuse 471.490981 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9327298 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1100005 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.479323 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 25754000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 465.850340 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.909864 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.909864 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5673895 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5673895 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3199282 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3199282 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148885 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 148885 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 172652 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 172652 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8873177 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8873177 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8873177 # number of overall hits -system.cpu0.dcache.overall_hits::total 8873177 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1348613 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1348613 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1646140 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1646140 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16729 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16729 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 773 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 773 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2994753 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2994753 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2994753 # number of overall misses -system.cpu0.dcache.overall_misses::total 2994753 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36556454998 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 36556454998 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 72896722210 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 72896722210 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 251362748 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 251362748 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4670052 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4670052 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 109453177208 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 109453177208 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 109453177208 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 109453177208 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7022508 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7022508 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4845422 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4845422 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 165614 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 165614 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 173425 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 173425 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11867930 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11867930 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11867930 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11867930 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.192042 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.192042 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.339731 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.339731 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101012 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101012 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004457 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004457 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.252340 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.252340 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.252340 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.252340 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27106.705184 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27106.705184 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44283.428026 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44283.428026 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15025.569251 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15025.569251 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6041.464424 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6041.464424 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36548.315406 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36548.315406 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36548.315406 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36548.315406 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2779952 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1302 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 46345 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 59.983860 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 162.750000 # average number of cycles each access was blocked +system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.490981 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.920881 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.920881 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5751167 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5751167 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3244504 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3244504 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151160 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 151160 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 174499 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 174499 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8995671 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8995671 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8995671 # number of overall hits +system.cpu0.dcache.overall_hits::total 8995671 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1359261 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1359261 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1665675 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1665675 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 17016 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 17016 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 764 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 764 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3024936 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3024936 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3024936 # number of overall misses +system.cpu0.dcache.overall_misses::total 3024936 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36687958870 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 36687958870 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 74828467074 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 74828467074 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 254575245 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 254575245 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4747557 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4747557 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 111516425944 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 111516425944 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 111516425944 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 111516425944 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7110428 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7110428 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4910179 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4910179 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 168176 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 168176 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 175263 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 175263 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12020607 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12020607 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12020607 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12020607 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.191164 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.191164 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.339229 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.339229 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101180 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101180 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004359 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004359 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.251646 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.251646 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.251646 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.251646 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26991.106837 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 26991.106837 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44923.809911 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44923.809911 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14960.933533 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14960.933533 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6214.079843 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6214.079843 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36865.714165 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36865.714165 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36865.714165 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36865.714165 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2890749 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 819 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 46898 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 61.639068 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 117 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 588957 # number of writebacks -system.cpu0.dcache.writebacks::total 588957 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 514989 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 514989 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1392541 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1392541 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3960 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3960 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1907530 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1907530 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1907530 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1907530 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 833624 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 833624 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 253599 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 253599 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12769 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12769 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 773 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 773 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1087223 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1087223 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1087223 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1087223 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24857542918 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24857542918 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10684541815 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10684541815 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 151212250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 151212250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3123948 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3123948 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35542084733 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 35542084733 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35542084733 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 35542084733 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 990981000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 990981000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1668402499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1668402499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2659383499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2659383499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118707 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118707 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052338 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052338 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.077101 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.077101 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004457 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004457 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091610 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.091610 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091610 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.091610 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29818.650756 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29818.650756 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42131.640168 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42131.640168 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11842.137207 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11842.137207 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4041.329884 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4041.329884 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32690.703501 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32690.703501 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32690.703501 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32690.703501 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 594718 # number of writebacks +system.cpu0.dcache.writebacks::total 594718 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 521771 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 521771 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1409219 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1409219 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4206 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4206 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1930990 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1930990 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1930990 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1930990 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 837490 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 837490 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256456 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 256456 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12810 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12810 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 764 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 764 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1093946 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1093946 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1093946 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1093946 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24898598196 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24898598196 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10973118276 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10973118276 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 152117754 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 152117754 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3219443 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3219443 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35871716472 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 35871716472 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35871716472 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 35871716472 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 993486001 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 993486001 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1673832998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1673832998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2667318999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2667318999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117783 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117783 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052229 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052229 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.076170 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.076170 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004359 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004359 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091006 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.091006 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091006 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.091006 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29730.024473 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29730.024473 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42787.527981 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42787.527981 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11874.922248 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11874.922248 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4213.930628 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4213.930628 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32791.121748 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32791.121748 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32791.121748 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32791.121748 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1519,35 +1512,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 4005476 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3286567 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 126561 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2463252 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1409799 # Number of BTB hits +system.cpu1.branchPred.lookups 3875512 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3181518 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 119538 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2413999 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1363069 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 57.233243 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 290076 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 11654 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 56.465185 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 281270 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 11131 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2861061 # DTB read hits -system.cpu1.dtb.read_misses 13171 # DTB read misses -system.cpu1.dtb.read_acv 26 # DTB read access violations -system.cpu1.dtb.read_accesses 327320 # DTB read accesses -system.cpu1.dtb.write_hits 1771736 # DTB write hits -system.cpu1.dtb.write_misses 2413 # DTB write misses -system.cpu1.dtb.write_acv 61 # DTB write access violations -system.cpu1.dtb.write_accesses 133954 # DTB write accesses -system.cpu1.dtb.data_hits 4632797 # DTB hits -system.cpu1.dtb.data_misses 15584 # DTB misses -system.cpu1.dtb.data_acv 87 # DTB access violations -system.cpu1.dtb.data_accesses 461274 # DTB accesses -system.cpu1.itb.fetch_hits 484886 # ITB hits -system.cpu1.itb.fetch_misses 6783 # ITB misses -system.cpu1.itb.fetch_acv 213 # ITB acv -system.cpu1.itb.fetch_accesses 491669 # ITB accesses +system.cpu1.dtb.read_hits 2756439 # DTB read hits +system.cpu1.dtb.read_misses 11971 # DTB read misses +system.cpu1.dtb.read_acv 6 # DTB read access violations +system.cpu1.dtb.read_accesses 281635 # DTB read accesses +system.cpu1.dtb.write_hits 1697476 # DTB write hits +system.cpu1.dtb.write_misses 2261 # DTB write misses +system.cpu1.dtb.write_acv 35 # DTB write access violations +system.cpu1.dtb.write_accesses 106637 # DTB write accesses +system.cpu1.dtb.data_hits 4453915 # DTB hits +system.cpu1.dtb.data_misses 14232 # DTB misses +system.cpu1.dtb.data_acv 41 # DTB access violations +system.cpu1.dtb.data_accesses 388272 # DTB accesses +system.cpu1.itb.fetch_hits 435796 # ITB hits +system.cpu1.itb.fetch_misses 5916 # ITB misses +system.cpu1.itb.fetch_acv 132 # ITB acv +system.cpu1.itb.fetch_accesses 441712 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1560,508 +1553,508 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 26365345 # number of cpu cycles simulated +system.cpu1.numCycles 25703316 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 8788859 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 19229785 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4005476 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1699875 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 3495206 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 620790 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 10702778 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 24531 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65519 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 161249 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 2272198 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 84032 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 23644267 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.813296 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.175765 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 8513027 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 18550498 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3875512 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1644339 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 3370867 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 594419 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 10509044 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24053 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 56236 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 158916 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 118 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 2181303 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 77306 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 23021613 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.805786 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.167146 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 20149061 85.22% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 201364 0.85% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 434975 1.84% 87.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 271433 1.15% 89.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 534220 2.26% 91.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 181805 0.77% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 209247 0.88% 92.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 254511 1.08% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1407651 5.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 19650746 85.36% 85.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 192109 0.83% 86.19% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 424155 1.84% 88.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 258878 1.12% 89.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 512227 2.22% 91.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 176251 0.77% 92.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 202668 0.88% 93.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 249358 1.08% 94.11% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1355221 5.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 23644267 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.151922 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.729358 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 8879389 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 10928600 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 3243065 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 199967 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 393245 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 183870 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 12999 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 18844715 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 38529 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 393245 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 9206755 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 3122476 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6754638 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 3034107 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1133044 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 17630254 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 270 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 267231 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 248854 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 11666322 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 21081705 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 21016911 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 58919 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 9884504 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1781818 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 561630 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 56869 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 3357033 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 3030330 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1870850 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 319037 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 184061 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 15497472 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 666578 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 15021403 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 38685 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2244261 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1133404 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 478003 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 23644267 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.635308 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.316901 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 23021613 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.150779 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.721716 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 8599650 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 10723354 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 3129491 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 191921 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 377196 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 176309 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 12258 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 18185515 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 36387 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 377196 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 8917984 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 3106321 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6595327 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2921217 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1103566 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 17011608 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 230 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 267059 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 236234 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 11254383 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 20310939 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 20246817 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 58360 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 9542826 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1711557 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 544600 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 54677 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 3272980 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2918733 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1792509 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 312208 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 170960 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 14943030 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 650638 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 14484391 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 37394 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2166782 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1088105 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 467114 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 23021613 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.629165 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.310842 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 17155384 72.56% 72.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2869349 12.14% 84.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1269974 5.37% 90.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 909350 3.85% 93.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 787037 3.33% 97.24% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 325991 1.38% 98.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 202457 0.86% 99.47% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 106589 0.45% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 18136 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 16750827 72.76% 72.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2784830 12.10% 84.86% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1224236 5.32% 90.18% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 874900 3.80% 93.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 759442 3.30% 97.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 313710 1.36% 98.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 192948 0.84% 99.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 103377 0.45% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 17343 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 23644267 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 23021613 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 18902 7.17% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 136410 51.75% 58.92% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 108303 41.08% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 19111 7.55% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 130840 51.68% 59.23% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 103199 40.77% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 9862540 65.66% 65.68% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 23545 0.16% 65.84% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 11158 0.07% 65.91% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.91% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.91% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.91% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2986833 19.88% 85.81% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1799237 11.98% 97.78% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 332801 2.22% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 9521262 65.73% 65.76% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 23052 0.16% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 11116 0.08% 65.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2876494 19.86% 85.87% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1724250 11.90% 97.77% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 322940 2.23% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 15021403 # Type of FU issued -system.cpu1.iq.rate 0.569740 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 263615 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.017549 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 53759316 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 18299643 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 14636122 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 230057 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 112007 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 108764 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 15161393 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 120099 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 139894 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 14484391 # Type of FU issued +system.cpu1.iq.rate 0.563522 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 253150 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.017477 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 52052620 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 17652734 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 14115090 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 228319 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 110924 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 107745 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 14614655 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 119368 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 134347 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 437460 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1072 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 3446 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 176357 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 418294 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 981 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 3304 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 169372 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 5243 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 21515 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 5236 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 20861 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 393245 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2412385 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 142199 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 17062579 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 198140 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 3030330 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1870850 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 597759 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 52684 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2595 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 3446 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 61011 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 139338 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 200349 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 14878419 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2882425 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 142984 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 377196 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2407064 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 140680 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 16469424 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 189598 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2918733 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1792509 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 583051 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 52184 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2431 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 3304 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 57543 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 133828 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 191371 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 14348807 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2776029 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 135584 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 898529 # number of nop insts executed -system.cpu1.iew.exec_refs 4662637 # number of memory reference insts executed -system.cpu1.iew.exec_branches 2338044 # Number of branches executed -system.cpu1.iew.exec_stores 1780212 # Number of stores executed -system.cpu1.iew.exec_rate 0.564317 # Inst execution rate -system.cpu1.iew.wb_sent 14784457 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 14744886 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 7139948 # num instructions producing a value -system.cpu1.iew.wb_consumers 10043269 # num instructions consuming a value +system.cpu1.iew.exec_nop 875756 # number of nop insts executed +system.cpu1.iew.exec_refs 4481633 # number of memory reference insts executed +system.cpu1.iew.exec_branches 2254475 # Number of branches executed +system.cpu1.iew.exec_stores 1705604 # Number of stores executed +system.cpu1.iew.exec_rate 0.558247 # Inst execution rate +system.cpu1.iew.wb_sent 14259530 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 14222835 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 6903248 # num instructions producing a value +system.cpu1.iew.wb_consumers 9726426 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.559253 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.710919 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.553346 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.709741 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 2396118 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 188575 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 186792 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 23251022 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.628108 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.559407 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 2312839 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 183524 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 178531 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 22644417 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.622505 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.551942 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 17812881 76.61% 76.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2343231 10.08% 86.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1160626 4.99% 91.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 598215 2.57% 94.25% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 379804 1.63% 95.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 180518 0.78% 96.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 173796 0.75% 97.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 135154 0.58% 97.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 466797 2.01% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 17386197 76.78% 76.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2263939 10.00% 86.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1130304 4.99% 91.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 578693 2.56% 94.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 365284 1.61% 95.94% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 174241 0.77% 96.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 166825 0.74% 97.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 129123 0.57% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 449811 1.99% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 23251022 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 14604164 # Number of instructions committed -system.cpu1.commit.committedOps 14604164 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 22644417 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 14096266 # Number of instructions committed +system.cpu1.commit.committedOps 14096266 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 4287363 # Number of memory references committed -system.cpu1.commit.loads 2592870 # Number of loads committed -system.cpu1.commit.membars 62980 # Number of memory barriers committed -system.cpu1.commit.branches 2183593 # Number of branches committed -system.cpu1.commit.fp_insts 107360 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 13494360 # Number of committed integer instructions. -system.cpu1.commit.function_calls 233831 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 466797 # number cycles where commit BW limit reached +system.cpu1.commit.refs 4123576 # Number of memory references committed +system.cpu1.commit.loads 2500439 # Number of loads committed +system.cpu1.commit.membars 61456 # Number of memory barriers committed +system.cpu1.commit.branches 2105755 # Number of branches committed +system.cpu1.commit.fp_insts 106451 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 13014804 # Number of committed integer instructions. +system.cpu1.commit.function_calls 225813 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 449811 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 39695803 # The number of ROB reads -system.cpu1.rob.rob_writes 34392702 # The number of ROB writes -system.cpu1.timesIdled 272923 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2721078 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3782349185 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 13810279 # Number of Instructions Simulated -system.cpu1.committedOps 13810279 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 13810279 # Number of Instructions Simulated -system.cpu1.cpi 1.909110 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.909110 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.523804 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.523804 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 19249115 # number of integer regfile reads -system.cpu1.int_regfile_writes 10558811 # number of integer regfile writes -system.cpu1.fp_regfile_reads 58616 # number of floating regfile reads -system.cpu1.fp_regfile_writes 58623 # number of floating regfile writes -system.cpu1.misc_regfile_reads 636847 # number of misc regfile reads -system.cpu1.misc_regfile_writes 274262 # number of misc regfile writes -system.cpu1.icache.tags.replacements 328629 # number of replacements -system.cpu1.icache.tags.tagsinuse 504.249918 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1927863 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 329141 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 5.857256 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 49124844500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.249918 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.984863 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.984863 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1927863 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1927863 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1927863 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1927863 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1927863 # number of overall hits -system.cpu1.icache.overall_hits::total 1927863 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 344335 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 344335 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 344335 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 344335 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 344335 # number of overall misses -system.cpu1.icache.overall_misses::total 344335 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4815194513 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4815194513 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4815194513 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4815194513 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4815194513 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4815194513 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 2272198 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 2272198 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 2272198 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 2272198 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 2272198 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 2272198 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.151543 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.151543 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.151543 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.151543 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.151543 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.151543 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13984.040289 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13984.040289 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13984.040289 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13984.040289 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13984.040289 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13984.040289 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1435 # number of cycles access was blocked +system.cpu1.rob.rob_reads 38521772 # The number of ROB reads +system.cpu1.rob.rob_writes 33194220 # The number of ROB writes +system.cpu1.timesIdled 266846 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2681703 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3780938744 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 13322175 # Number of Instructions Simulated +system.cpu1.committedOps 13322175 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 13322175 # Number of Instructions Simulated +system.cpu1.cpi 1.929363 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.929363 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.518306 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.518306 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 18552962 # number of integer regfile reads +system.cpu1.int_regfile_writes 10191479 # number of integer regfile writes +system.cpu1.fp_regfile_reads 58039 # number of floating regfile reads +system.cpu1.fp_regfile_writes 58174 # number of floating regfile writes +system.cpu1.misc_regfile_reads 621722 # number of misc regfile reads +system.cpu1.misc_regfile_writes 265027 # number of misc regfile writes +system.cpu1.icache.tags.replacements 316719 # number of replacements +system.cpu1.icache.tags.tagsinuse 504.225697 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1849767 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 317231 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.830978 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 49140510500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.225697 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.984816 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.984816 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1849767 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1849767 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1849767 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1849767 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1849767 # number of overall hits +system.cpu1.icache.overall_hits::total 1849767 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 331536 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 331536 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 331536 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 331536 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 331536 # number of overall misses +system.cpu1.icache.overall_misses::total 331536 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4647513106 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4647513106 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4647513106 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4647513106 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4647513106 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4647513106 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 2181303 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 2181303 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 2181303 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 2181303 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 2181303 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 2181303 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.151990 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.151990 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.151990 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.151990 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.151990 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.151990 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14018.125048 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14018.125048 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14018.125048 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14018.125048 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14018.125048 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14018.125048 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1365 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 51 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 71 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 28.137255 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 19.225352 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 15125 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 15125 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 15125 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 15125 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 15125 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 15125 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329210 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 329210 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 329210 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 329210 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 329210 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 329210 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3979739752 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3979739752 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3979739752 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3979739752 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3979739752 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3979739752 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.144886 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.144886 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.144886 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12088.757182 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12088.757182 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12088.757182 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 14239 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 14239 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 14239 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 14239 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 14239 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 14239 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 317297 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 317297 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 317297 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 317297 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 317297 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 317297 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3842042413 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3842042413 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3842042413 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3842042413 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3842042413 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3842042413 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.145462 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.145462 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.145462 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.145462 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.145462 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.145462 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12108.662903 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12108.662903 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12108.662903 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 330658 # number of replacements -system.cpu1.dcache.tags.tagsinuse 495.877996 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3531981 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 331060 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 10.668704 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 42038170500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 495.877996 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968512 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.968512 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 2174883 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2174883 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1270139 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1270139 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 43234 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 43234 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 46255 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 46255 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3445022 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3445022 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3445022 # number of overall hits -system.cpu1.dcache.overall_hits::total 3445022 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 478937 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 478937 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 369959 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 369959 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7995 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 7995 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 815 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 815 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 848896 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 848896 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 848896 # number of overall misses -system.cpu1.dcache.overall_misses::total 848896 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7393539723 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 7393539723 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13842081157 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 13842081157 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 114418247 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 114418247 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5712098 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5712098 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 21235620880 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 21235620880 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 21235620880 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 21235620880 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2653820 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2653820 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1640098 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1640098 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 51229 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 51229 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 47070 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 47070 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4293918 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4293918 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4293918 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4293918 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.180471 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.180471 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.225571 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.225571 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156064 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156064 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.017315 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.017315 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.197697 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.197697 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.197697 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.197697 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15437.395154 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15437.395154 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37415.176160 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 37415.176160 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14311.225391 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14311.225391 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7008.709202 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7008.709202 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25015.574205 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 25015.574205 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25015.574205 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 25015.574205 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 432228 # number of cycles access was blocked +system.cpu1.dcache.tags.replacements 323504 # number of replacements +system.cpu1.dcache.tags.tagsinuse 495.920224 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3389718 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 323845 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 10.467100 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 42037852500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 495.920224 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968594 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.968594 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2089496 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2089496 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1222054 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1222054 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 41428 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 41428 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 44398 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 44398 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3311550 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3311550 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3311550 # number of overall hits +system.cpu1.dcache.overall_hits::total 3311550 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 467553 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 467553 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 348721 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 348721 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7730 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 7730 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 782 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 782 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 816274 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 816274 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 816274 # number of overall misses +system.cpu1.dcache.overall_misses::total 816274 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7286969700 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 7286969700 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13547153677 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 13547153677 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 112298247 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 112298247 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5736606 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5736606 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 20834123377 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 20834123377 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 20834123377 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 20834123377 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2557049 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2557049 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1570775 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1570775 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 49158 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 49158 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 45180 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 45180 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4127824 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4127824 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4127824 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4127824 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.182849 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.182849 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.222006 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.222006 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.157248 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.157248 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.017309 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.017309 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.197749 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.197749 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.197749 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.197749 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15585.334069 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15585.334069 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38848.115476 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 38848.115476 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14527.586934 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14527.586934 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7335.813299 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7335.813299 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25523.443570 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 25523.443570 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25523.443570 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 25523.443570 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 423453 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 7570 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 7447 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 57.097490 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 56.862226 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 251201 # number of writebacks -system.cpu1.dcache.writebacks::total 251201 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 211025 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 211025 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306586 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 306586 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1580 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1580 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 517611 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 517611 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 517611 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 517611 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 267912 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 267912 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 63373 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 63373 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6415 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6415 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 815 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 815 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 331285 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 331285 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 331285 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 331285 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3418270202 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3418270202 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2068179649 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2068179649 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 71253503 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 71253503 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4081902 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4081902 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5486449851 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5486449851 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5486449851 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5486449851 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 491833500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 491833500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 943255503 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 943255503 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1435089003 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1435089003 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.100953 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.100953 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038640 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038640 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.125222 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.125222 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.017315 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.017315 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.077152 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.077152 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.077152 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.077152 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12758.929059 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12758.929059 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32635.028309 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32635.028309 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11107.327046 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11107.327046 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5008.468712 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5008.468712 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16561.117621 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16561.117621 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16561.117621 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16561.117621 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 245774 # number of writebacks +system.cpu1.dcache.writebacks::total 245774 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 203756 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 203756 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 288423 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 288423 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1420 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1420 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 492179 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 492179 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 492179 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 492179 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 263797 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 263797 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 60298 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 60298 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6310 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6310 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 781 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 781 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 324095 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 324095 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 324095 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 324095 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3377520942 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3377520942 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2032860866 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2032860866 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70443003 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70443003 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4174394 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4174394 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5410381808 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5410381808 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5410381808 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5410381808 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 489946000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 489946000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 936242002 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 936242002 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1426188002 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1426188002 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.103165 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.103165 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038387 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038387 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.128362 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.128362 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.017286 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.017286 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.078515 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.078515 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.078515 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.078515 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12803.485036 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12803.485036 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33713.570367 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33713.570367 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11163.708875 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11163.708875 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5344.934699 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5344.934699 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16693.814493 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16693.814493 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16693.814493 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16693.814493 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2070,170 +2063,161 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4829 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 164539 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56531 39.74% 39.74% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 39.83% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1925 1.35% 41.18% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 16 0.01% 41.20% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 83653 58.80% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 142256 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 55584 49.09% 49.09% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.12% 49.21% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1925 1.70% 50.91% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 16 0.01% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55568 49.08% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 113224 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1866804619500 98.01% 98.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 62415000 0.00% 98.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 563852000 0.03% 98.05% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 8731500 0.00% 98.05% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 37224635500 1.95% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1904664253500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983248 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4836 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 166329 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 57049 39.81% 39.81% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 39.90% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1924 1.34% 41.24% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 41.25% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 84196 58.75% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 143316 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56102 49.10% 49.10% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.22% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1924 1.68% 50.90% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.01% 50.91% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 56086 49.09% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114259 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1865433154000 98.01% 98.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 62620000 0.00% 98.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 558222500 0.03% 98.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 8649500 0.00% 98.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 37274722500 1.96% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1903337368500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983400 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.664268 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.795917 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed -system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed -system.cpu0.kern.syscall::6 29 14.36% 27.72% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.50% 28.22% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.46% 32.67% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.47% 36.14% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.98% 38.12% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.50% 38.61% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.49% 40.10% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.47% 43.56% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.99% 44.55% # number of syscalls executed -system.cpu0.kern.syscall::45 34 16.83% 61.39% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.49% 62.87% # number of syscalls executed -system.cpu0.kern.syscall::48 8 3.96% 66.83% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.46% 71.29% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.50% 71.78% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.48% 74.26% # number of syscalls executed -system.cpu0.kern.syscall::71 25 12.38% 86.63% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.49% 88.12% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.97% 91.09% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.50% 91.58% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.99% 92.57% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.47% 96.04% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.99% 97.03% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.99% 98.02% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.50% 98.51% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.50% 99.01% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 202 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.666136 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.797252 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.67% 28.44% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.44% 28.89% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.00% 32.89% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.44% 37.33% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.67% 40.00% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.44% 40.44% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.33% 41.78% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.11% 44.89% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.89% 45.78% # number of syscalls executed +system.cpu0.kern.syscall::45 36 16.00% 61.78% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.33% 63.11% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.44% 67.56% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.44% 72.00% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.44% 72.44% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.67% 75.11% # number of syscalls executed +system.cpu0.kern.syscall::71 25 11.11% 86.22% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.33% 87.56% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.67% 90.22% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.44% 90.67% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.33% 92.00% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.00% 96.00% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.89% 96.89% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.89% 97.78% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.44% 98.22% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.89% 99.11% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 225 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 108 0.07% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wripir 104 0.07% 0.07% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2969 1.98% 2.05% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.09% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed -system.cpu0.kern.callpal::swpipl 135909 90.65% 92.74% # number of callpals executed -system.cpu0.kern.callpal::rdps 6127 4.09% 96.83% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.83% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.83% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.01% 96.83% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.84% # number of callpals executed -system.cpu0.kern.callpal::rti 4274 2.85% 99.69% # number of callpals executed -system.cpu0.kern.callpal::callsys 333 0.22% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149930 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6311 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1258 # number of protection mode switches +system.cpu0.kern.callpal::swpctx 3010 1.99% 2.06% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.09% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.10% # number of callpals executed +system.cpu0.kern.callpal::swpipl 136886 90.50% 92.60% # number of callpals executed +system.cpu0.kern.callpal::rdps 6293 4.16% 96.76% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.77% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.77% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.77% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed +system.cpu0.kern.callpal::rti 4358 2.88% 99.66% # number of callpals executed +system.cpu0.kern.callpal::callsys 382 0.25% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 151247 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6436 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1343 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1257 -system.cpu0.kern.mode_good::user 1258 +system.cpu0.kern.mode_good::kernel 1342 +system.cpu0.kern.mode_good::user 1343 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.199176 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.208515 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.332276 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1902741106000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1923139500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.345160 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1901289587500 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2047773000 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2970 # number of times the context was actually changed +system.cpu0.kern.swap_context 3011 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3864 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 73072 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 25114 39.08% 39.08% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1924 2.99% 42.08% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 108 0.17% 42.25% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 37111 57.75% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 64257 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 24684 48.12% 48.12% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1924 3.75% 51.88% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 108 0.21% 52.09% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 24576 47.91% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 51292 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870089135500 98.20% 98.20% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533638000 0.03% 98.23% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 50840000 0.00% 98.23% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 33685568500 1.77% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1904359182000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.982878 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3850 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 71149 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 24567 38.92% 38.92% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1923 3.05% 41.97% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 104 0.16% 42.13% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 36529 57.87% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 63123 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 24137 48.08% 48.08% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1923 3.83% 51.92% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 104 0.21% 52.12% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 24033 47.88% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 50197 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1869107624500 98.20% 98.20% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 533184500 0.03% 98.23% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 48972500 0.00% 98.23% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 33633158500 1.77% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1903322940000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.982497 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.662230 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.798232 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed -system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed -system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.81% 23.39% # number of syscalls executed -system.cpu1.kern.syscall::17 6 4.84% 28.23% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.42% 30.65% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.61% 32.26% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.42% 34.68% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.42% 37.10% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.23% 40.32% # number of syscalls executed -system.cpu1.kern.syscall::45 20 16.13% 56.45% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.42% 58.87% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.61% 60.48% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.81% 61.29% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.61% 62.90% # number of syscalls executed -system.cpu1.kern.syscall::71 29 23.39% 86.29% # number of syscalls executed -system.cpu1.kern.syscall::74 10 8.06% 94.35% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.81% 95.16% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.61% 96.77% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.42% 99.19% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 124 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.657916 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.795225 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed +system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.94% 26.73% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.97% 29.70% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.97% 32.67% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.96% 36.63% # number of syscalls executed +system.cpu1.kern.syscall::45 18 17.82% 54.46% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.97% 57.43% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.99% 58.42% # number of syscalls executed +system.cpu1.kern.syscall::71 29 28.71% 87.13% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.90% 97.03% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 101 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal::wripir 16 0.02% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1277 1.92% 1.95% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 1.96% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 1.97% # number of callpals executed -system.cpu1.kern.callpal::swpipl 59282 89.28% 91.25% # number of callpals executed -system.cpu1.kern.callpal::rdps 2633 3.97% 95.21% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 95.21% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 95.22% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 95.22% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 95.23% # number of callpals executed -system.cpu1.kern.callpal::rti 2942 4.43% 99.66% # number of callpals executed -system.cpu1.kern.callpal::callsys 184 0.28% 99.93% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1228 1.89% 1.92% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 1.92% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 1.93% # number of callpals executed +system.cpu1.kern.callpal::swpipl 58251 89.62% 91.55% # number of callpals executed +system.cpu1.kern.callpal::rdps 2464 3.79% 95.34% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 95.34% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 95.35% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 95.35% # number of callpals executed +system.cpu1.kern.callpal::rti 2844 4.38% 99.73% # number of callpals executed +system.cpu1.kern.callpal::callsys 133 0.20% 99.93% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 66403 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1747 # number of protection mode switches -system.cpu1.kern.mode_switch::user 488 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2062 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 557 -system.cpu1.kern.mode_good::user 488 -system.cpu1.kern.mode_good::idle 69 -system.cpu1.kern.mode_switch_good::kernel 0.318832 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 65000 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1608 # number of protection mode switches +system.cpu1.kern.mode_switch::user 397 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 463 +system.cpu1.kern.mode_good::user 397 +system.cpu1.kern.mode_good::idle 66 +system.cpu1.kern.mode_switch_good::kernel 0.287935 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.033463 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.259251 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 38709369000 2.03% 2.03% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 835914500 0.04% 2.08% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1864803541000 97.92% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1278 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.032132 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.228135 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 38501499500 2.02% 2.02% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 724848000 0.04% 2.06% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1863406690000 97.94% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1229 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 4bc22a482..275c9f168 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -13,15 +15,16 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/dist/m5/system/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console +eventq_index=0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -39,6 +42,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 @@ -48,6 +52,7 @@ slave=system.membus.master[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -79,6 +84,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -143,6 +150,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -158,6 +166,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -180,26 +189,31 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -208,16 +222,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -226,22 +243,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -250,22 +271,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -274,10 +299,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -286,124 +313,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -412,10 +460,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -424,16 +474,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -442,10 +495,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -456,6 +511,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -478,17 +534,21 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -497,6 +557,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -519,12 +580,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -534,10 +597,12 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.disk0] @@ -545,19 +610,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk0.image [system.disk0.image] type=CowDiskImage children=child child=system.disk0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -565,28 +633,33 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk2.image [system.disk2.image] type=CowDiskImage children=child child=system.disk2.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -600,6 +673,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -622,6 +696,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -629,6 +704,7 @@ size=1024 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -640,6 +716,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -666,6 +743,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -677,29 +755,35 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[1] [system.simple_disk] type=SimpleDisk children=disk disk=system.simple_disk.disk +eventq_index=0 system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -708,6 +792,7 @@ port=3456 [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +eventq_index=0 intrctrl=system.intrctrl system=system @@ -716,6 +801,7 @@ type=AlphaBackdoor clk_domain=system.clk_domain cpu=system.cpu disk=system.simple_disk +eventq_index=0 pio_addr=8804682956800 pio_latency=100000 platform=system.tsunami @@ -726,6 +812,7 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8803072344064 pio_latency=100000 system=system @@ -754,6 +841,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=2 Command=0 @@ -763,8 +851,40 @@ HeaderType=0 InterruptLine=30 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=52 MinimumGrant=176 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=0 Revision=0 Status=656 @@ -781,6 +901,7 @@ dma_read_delay=0 dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 +eventq_index=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 pci_bus=0 @@ -804,6 +925,7 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8796093677568 pio_latency=100000 @@ -821,6 +943,7 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848432 pio_latency=100000 @@ -838,6 +961,7 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848304 pio_latency=100000 @@ -855,6 +979,7 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848569 pio_latency=100000 @@ -872,6 +997,7 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848451 pio_latency=100000 @@ -889,6 +1015,7 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848515 pio_latency=100000 @@ -906,6 +1033,7 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848579 pio_latency=100000 @@ -923,6 +1051,7 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848643 pio_latency=100000 @@ -940,6 +1069,7 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848707 pio_latency=100000 @@ -957,6 +1087,7 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848771 pio_latency=100000 @@ -974,6 +1105,7 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848835 pio_latency=100000 @@ -991,6 +1123,7 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848899 pio_latency=100000 @@ -1008,6 +1141,7 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615850617 pio_latency=100000 @@ -1025,6 +1159,7 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848891 pio_latency=100000 @@ -1042,6 +1177,7 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848816 pio_latency=100000 @@ -1059,6 +1195,7 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848696 pio_latency=100000 @@ -1076,6 +1213,7 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848936 pio_latency=100000 @@ -1093,6 +1231,7 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848680 pio_latency=100000 @@ -1110,6 +1249,7 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848944 pio_latency=100000 @@ -1128,6 +1268,7 @@ pio=system.iobus.master[6] type=BadDevice clk_domain=system.clk_domain devicename=FrameBuffer +eventq_index=0 pio_addr=8804615848912 pio_latency=100000 system=system @@ -1155,6 +1296,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -1164,8 +1306,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -1177,6 +1351,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=0 @@ -1191,6 +1366,7 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO clk_domain=system.clk_domain +eventq_index=0 frequency=976562500 pio_addr=8804615847936 pio_latency=100000 @@ -1203,6 +1379,7 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8802535473152 pio_latency=100000 system=system @@ -1213,6 +1390,7 @@ pio=system.iobus.master[1] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.tsunami @@ -1223,6 +1401,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain +eventq_index=0 pio_addr=8804615848952 pio_latency=100000 platform=system.tsunami @@ -1232,5 +1411,6 @@ pio=system.iobus.master[23] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index cb131fc03..c08f75535 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,126 +1,126 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.860198 # Number of seconds simulated -sim_ticks 1860197608000 # Number of ticks simulated -final_tick 1860197608000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1860197780500 # Number of ticks simulated +final_tick 1860197780500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128608 # Simulator instruction rate (inst/s) -host_op_rate 128608 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4515644283 # Simulator tick rate (ticks/s) -host_mem_usage 336512 # Number of bytes of host memory used -host_seconds 411.95 # Real time elapsed on the host -sim_insts 52979573 # Number of instructions simulated -sim_ops 52979573 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 964544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24879808 # Number of bytes read from this memory +host_inst_rate 103834 # Simulator instruction rate (inst/s) +host_op_rate 103834 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3645751305 # Simulator tick rate (ticks/s) +host_mem_usage 355004 # Number of bytes of host memory used +host_seconds 510.24 # Real time elapsed on the host +sim_insts 52979882 # Number of instructions simulated +sim_ops 52979882 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24878976 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28496640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 964544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 964544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7516672 # Number of bytes written to this memory -system.physmem.bytes_written::total 7516672 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15071 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388747 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28495232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 963968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 963968 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7515456 # Number of bytes written to this memory +system.physmem.bytes_written::total 7515456 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15062 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388734 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445260 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117448 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117448 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 518517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13374820 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 445238 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117429 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117429 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 518207 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13374371 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 1425810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15319147 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 518517 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 518517 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4040792 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4040792 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4040792 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 518517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13374820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 15318388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 518207 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518207 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4040138 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4040138 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4040138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 518207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13374371 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1425810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19359939 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445260 # Number of read requests accepted -system.physmem.writeReqs 117448 # Number of write requests accepted -system.physmem.readBursts 445260 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117448 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28493888 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2752 # Total number of bytes read from write queue -system.physmem.bytesWritten 7515904 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28496640 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7516672 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 43 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 19358526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445238 # Number of read requests accepted +system.physmem.writeReqs 117429 # Number of write requests accepted +system.physmem.readBursts 445238 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117429 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28492032 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3200 # Total number of bytes read from write queue +system.physmem.bytesWritten 7514752 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28495232 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7515456 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 177 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 179 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 28229 # Per bank write bursts system.physmem.perBankRdBursts::1 27970 # Per bank write bursts -system.physmem.perBankRdBursts::2 28438 # Per bank write bursts -system.physmem.perBankRdBursts::3 28034 # Per bank write bursts -system.physmem.perBankRdBursts::4 27800 # Per bank write bursts -system.physmem.perBankRdBursts::5 27233 # Per bank write bursts +system.physmem.perBankRdBursts::2 28433 # Per bank write bursts +system.physmem.perBankRdBursts::3 28029 # Per bank write bursts +system.physmem.perBankRdBursts::4 27802 # Per bank write bursts +system.physmem.perBankRdBursts::5 27222 # Per bank write bursts system.physmem.perBankRdBursts::6 27248 # Per bank write bursts -system.physmem.perBankRdBursts::7 27300 # Per bank write bursts -system.physmem.perBankRdBursts::8 27656 # Per bank write bursts -system.physmem.perBankRdBursts::9 27404 # Per bank write bursts -system.physmem.perBankRdBursts::10 27929 # Per bank write bursts -system.physmem.perBankRdBursts::11 27540 # Per bank write bursts -system.physmem.perBankRdBursts::12 27555 # Per bank write bursts -system.physmem.perBankRdBursts::13 28228 # Per bank write bursts -system.physmem.perBankRdBursts::14 28334 # Per bank write bursts -system.physmem.perBankRdBursts::15 28319 # Per bank write bursts -system.physmem.perBankWrBursts::0 7929 # Per bank write bursts -system.physmem.perBankWrBursts::1 7498 # Per bank write bursts -system.physmem.perBankWrBursts::2 7947 # Per bank write bursts +system.physmem.perBankRdBursts::7 27296 # Per bank write bursts +system.physmem.perBankRdBursts::8 27665 # Per bank write bursts +system.physmem.perBankRdBursts::9 27395 # Per bank write bursts +system.physmem.perBankRdBursts::10 27922 # Per bank write bursts +system.physmem.perBankRdBursts::11 27539 # Per bank write bursts +system.physmem.perBankRdBursts::12 27561 # Per bank write bursts +system.physmem.perBankRdBursts::13 28227 # Per bank write bursts +system.physmem.perBankRdBursts::14 28327 # Per bank write bursts +system.physmem.perBankRdBursts::15 28323 # Per bank write bursts +system.physmem.perBankWrBursts::0 7932 # Per bank write bursts +system.physmem.perBankWrBursts::1 7497 # Per bank write bursts +system.physmem.perBankWrBursts::2 7944 # Per bank write bursts system.physmem.perBankWrBursts::3 7517 # Per bank write bursts -system.physmem.perBankWrBursts::4 7338 # Per bank write bursts -system.physmem.perBankWrBursts::5 6689 # Per bank write bursts -system.physmem.perBankWrBursts::6 6763 # Per bank write bursts -system.physmem.perBankWrBursts::7 6689 # Per bank write bursts -system.physmem.perBankWrBursts::8 7098 # Per bank write bursts -system.physmem.perBankWrBursts::9 6803 # Per bank write bursts -system.physmem.perBankWrBursts::10 7320 # Per bank write bursts -system.physmem.perBankWrBursts::11 6984 # Per bank write bursts -system.physmem.perBankWrBursts::12 7119 # Per bank write bursts -system.physmem.perBankWrBursts::13 7873 # Per bank write bursts -system.physmem.perBankWrBursts::14 8054 # Per bank write bursts -system.physmem.perBankWrBursts::15 7815 # Per bank write bursts +system.physmem.perBankWrBursts::4 7343 # Per bank write bursts +system.physmem.perBankWrBursts::5 6680 # Per bank write bursts +system.physmem.perBankWrBursts::6 6761 # Per bank write bursts +system.physmem.perBankWrBursts::7 6683 # Per bank write bursts +system.physmem.perBankWrBursts::8 7104 # Per bank write bursts +system.physmem.perBankWrBursts::9 6801 # Per bank write bursts +system.physmem.perBankWrBursts::10 7313 # Per bank write bursts +system.physmem.perBankWrBursts::11 6981 # Per bank write bursts +system.physmem.perBankWrBursts::12 7123 # Per bank write bursts +system.physmem.perBankWrBursts::13 7875 # Per bank write bursts +system.physmem.perBankWrBursts::14 8050 # Per bank write bursts +system.physmem.perBankWrBursts::15 7814 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 1860192151000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry +system.physmem.totGap 1860192344000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 445260 # Read request sizes (log2) +system.physmem.readPktSize::6 445238 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117448 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 332300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20080 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117429 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 332275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66533 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19911 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 5799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1330 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1436 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1086 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 956 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2385 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2335 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1259 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1090 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 958 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 955 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -131,226 +131,229 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 24 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 43193 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 833.653601 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 238.014185 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1939.409877 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 14703 34.04% 34.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6277 14.53% 48.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 4438 10.27% 58.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2692 6.23% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1642 3.80% 68.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1371 3.17% 72.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 939 2.17% 74.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 792 1.83% 76.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 658 1.52% 77.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 515 1.19% 78.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 623 1.44% 80.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 600 1.39% 81.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 275 0.64% 82.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 275 0.64% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 263 0.61% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 360 0.83% 84.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 192 0.44% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 168 0.39% 85.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 100 0.23% 85.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 208 0.48% 85.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 111 0.26% 86.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 353 0.82% 86.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 185 0.43% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 668 1.55% 88.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 85 0.20% 89.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 28 0.06% 89.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 47 0.11% 89.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 186 0.43% 89.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 41 0.09% 89.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 74 0.17% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 86 0.20% 90.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 80 0.19% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 97 0.22% 90.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 73 0.17% 90.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 19 0.04% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 108 0.25% 91.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 28 0.06% 91.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 15 0.03% 91.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 1 0.00% 91.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 16 0.04% 91.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 2 0.00% 91.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 13 0.03% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 24 0.06% 91.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 101 0.23% 91.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 13 0.03% 91.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 66 0.15% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 82 0.19% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 39 0.09% 91.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 82 0.19% 92.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 66 0.15% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 13 0.03% 92.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 95 0.22% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 22 0.05% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 10 0.02% 92.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 4 0.01% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 12 0.03% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 3 0.01% 92.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 11 0.03% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 24 0.06% 92.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 91 0.21% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 11 0.03% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 66 0.15% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 81 0.19% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 39 0.09% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 79 0.18% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 68 0.16% 93.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 12 0.03% 93.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 94 0.22% 94.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 22 0.05% 94.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 12 0.03% 94.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 4 0.01% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 11 0.03% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 4 0.01% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 12 0.03% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 21 0.05% 94.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 92 0.21% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 13 0.03% 94.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 67 0.16% 94.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 81 0.19% 94.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 35 0.08% 94.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 79 0.18% 95.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 68 0.16% 95.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 12 0.03% 95.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 99 0.23% 95.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 22 0.05% 95.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 11 0.03% 95.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 1 0.00% 95.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 12 0.03% 95.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 11 0.03% 95.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 21 0.05% 95.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 92 0.21% 95.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 14 0.03% 95.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 64 0.15% 96.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 83 0.19% 96.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 39 0.09% 96.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 81 0.19% 96.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 67 0.16% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 13 0.03% 96.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 94 0.22% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 21 0.05% 96.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 8 0.02% 97.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.00% 97.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 12 0.03% 97.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 3 0.01% 97.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 10 0.02% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 24 0.06% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 89 0.21% 97.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 13 0.03% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 66 0.15% 97.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 81 0.19% 97.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 309 0.72% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 2 0.00% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 1 0.00% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 16 0.04% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 4 0.01% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 1 0.00% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 3 0.01% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 18 0.04% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 3 0.01% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 331 0.77% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 2 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 5 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 2 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.32% # Bytes accessed per row activation +system.physmem.wrQLenPdf::0 4574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 43301 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 831.507817 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 237.255649 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1940.687281 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 14819 34.22% 34.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6274 14.49% 48.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 4433 10.24% 58.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2614 6.04% 64.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1636 3.78% 68.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1435 3.31% 72.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 928 2.14% 74.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 854 1.97% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 632 1.46% 77.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 524 1.21% 78.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 594 1.37% 80.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 623 1.44% 81.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 284 0.66% 82.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 262 0.61% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 268 0.62% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 398 0.92% 84.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 204 0.47% 84.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 163 0.38% 85.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 93 0.21% 85.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 193 0.45% 85.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 100 0.23% 86.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 353 0.82% 87.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 186 0.43% 87.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 655 1.51% 88.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 89 0.21% 89.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 28 0.06% 89.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 40 0.09% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 175 0.40% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 41 0.09% 89.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 79 0.18% 90.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 86 0.20% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 82 0.19% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 104 0.24% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 73 0.17% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 16 0.04% 90.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 102 0.24% 91.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 26 0.06% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 14 0.03% 91.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 2 0.00% 91.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 17 0.04% 91.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 4 0.01% 91.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 13 0.03% 91.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 25 0.06% 91.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 100 0.23% 91.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 15 0.03% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 67 0.15% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 82 0.19% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 42 0.10% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 83 0.19% 92.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 68 0.16% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 12 0.03% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 94 0.22% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 22 0.05% 92.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 9 0.02% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 5 0.01% 92.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 12 0.03% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 4 0.01% 92.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 11 0.03% 92.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 22 0.05% 92.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 92 0.21% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 13 0.03% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 66 0.15% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 81 0.19% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 40 0.09% 93.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 80 0.18% 93.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 68 0.16% 93.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 12 0.03% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 95 0.22% 94.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 21 0.05% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 10 0.02% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 1 0.00% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 11 0.03% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 4 0.01% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 13 0.03% 94.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 21 0.05% 94.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 92 0.21% 94.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 14 0.03% 94.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 68 0.16% 94.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 81 0.19% 94.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 35 0.08% 94.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 79 0.18% 95.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 65 0.15% 95.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 12 0.03% 95.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 98 0.23% 95.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 22 0.05% 95.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 10 0.02% 95.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 1 0.00% 95.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 12 0.03% 95.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 11 0.03% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 21 0.05% 95.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 92 0.21% 95.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 13 0.03% 95.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 64 0.15% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 81 0.19% 96.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 41 0.09% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 82 0.19% 96.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 69 0.16% 96.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 14 0.03% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 94 0.22% 96.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 21 0.05% 97.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 8 0.02% 97.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 12 0.03% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 2 0.00% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 10 0.02% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 22 0.05% 97.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 89 0.21% 97.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 14 0.03% 97.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 66 0.15% 97.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 80 0.18% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 307 0.71% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 1 0.00% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 1 0.00% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 17 0.04% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7491 2 0.00% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 5 0.01% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 1 0.00% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 16 0.04% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 1 0.00% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 2 0.00% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 330 0.76% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 2 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.32% # Bytes accessed per row activation system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9411 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9411 2 0.00% 99.34% # Bytes accessed per row activation system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 2 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10307 2 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 3 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11011 3 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11715 2 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11840-11843 3 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11907 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 4 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12931 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13123 2 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 3 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 37 0.09% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11456-11459 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11651 2 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 4 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12483 2 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 4 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 7 0.02% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 4 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 3 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 40 0.09% 99.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 2 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 176 0.41% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 43193 # Bytes accessed per row activation -system.physmem.totQLat 8380902250 # Total ticks spent queuing -system.physmem.totMemAccLat 15783312250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2226085000 # Total ticks spent in databus transfers -system.physmem.totBankLat 5176325000 # Total ticks spent accessing banks -system.physmem.avgQLat 18824.31 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 11626.52 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 174 0.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 43301 # Bytes accessed per row activation +system.physmem.totQLat 8362787000 # Total ticks spent queuing +system.physmem.totMemAccLat 15768695750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2225940000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5179968750 # Total ticks spent accessing banks +system.physmem.avgQLat 18784.84 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11635.46 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35450.83 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 35420.31 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.32 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s @@ -360,59 +363,60 @@ system.physmem.busUtil 0.15 # Da system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.37 # Average write queue length when enqueuing -system.physmem.readRowHits 424661 # Number of row buffer hits during reads -system.physmem.writeRowHits 94799 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.72 # Row buffer hit rate for writes -system.physmem.avgGap 3305785.86 # Average gap between requests -system.physmem.pageHitRate 92.32 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.40 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 19402801 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 295960 # Transaction distribution -system.membus.trans_dist::ReadResp 295877 # Transaction distribution +system.physmem.avgWrQLen 11.24 # Average write queue length when enqueuing +system.physmem.readRowHits 424550 # Number of row buffer hits during reads +system.physmem.writeRowHits 94755 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.69 # Row buffer hit rate for writes +system.physmem.avgGap 3306027.09 # Average gap between requests +system.physmem.pageHitRate 92.30 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.39 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 19401389 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 295980 # Transaction distribution +system.membus.trans_dist::ReadResp 295901 # Transaction distribution system.membus.trans_dist::WriteReq 9598 # Transaction distribution system.membus.trans_dist::WriteResp 9598 # Transaction distribution -system.membus.trans_dist::Writeback 117448 # Transaction distribution -system.membus.trans_dist::UpgradeReq 180 # Transaction distribution -system.membus.trans_dist::UpgradeResp 180 # Transaction distribution -system.membus.trans_dist::ReadExReq 156869 # Transaction distribution -system.membus.trans_dist::ReadExResp 156869 # Transaction distribution -system.membus.trans_dist::BadAddressError 83 # Transaction distribution +system.membus.trans_dist::Writeback 117429 # Transaction distribution +system.membus.trans_dist::UpgradeReq 181 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 182 # Transaction distribution +system.membus.trans_dist::ReadExReq 156823 # Transaction distribution +system.membus.trans_dist::ReadExResp 156823 # Transaction distribution +system.membus.trans_dist::BadAddressError 79 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884202 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 166 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884143 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 158 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917357 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1042103 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1042036 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30748404 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30701632 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30745780 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36057460 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36057460 # Total data (bytes) +system.membus.tot_pkt_size::total 36054836 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36054836 # Total data (bytes) system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29954500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 29837500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1551414500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1551324500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 106000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 96500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3763341794 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3763216294 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376305243 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376313495 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.261102 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.261116 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710341438000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.261102 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078819 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078819 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1710341603000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.261116 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078820 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078820 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -423,12 +427,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21133883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21133883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12983817806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12983817806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 13004951689 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 13004951689 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 13004951689 # number of overall miss cycles -system.iocache.overall_miss_latency::total 13004951689 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12974928560 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12974928560 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 12996062443 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 12996062443 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 12996062443 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12996062443 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -447,17 +451,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122161.173410 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 122161.173410 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312471.549047 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 312471.549047 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 311682.485057 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 311682.485057 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 311682.485057 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 311682.485057 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 402476 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312257.618406 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 312257.618406 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 311469.441414 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 311469.441414 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 311469.441414 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 311469.441414 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 401483 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 29170 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 29284 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.797600 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.709978 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -473,12 +477,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12136883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10821554320 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10821554320 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10833691203 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10833691203 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10833691203 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10833691203 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10812648570 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10812648570 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10824785453 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10824785453 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10824785453 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10824785453 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -489,12 +493,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70155.393064 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 70155.393064 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260434.018098 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 260434.018098 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259645.085752 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 259645.085752 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259645.085752 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 259645.085752 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260219.690268 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 260219.690268 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259431.646567 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 259431.646567 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259431.646567 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 259431.646567 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -508,35 +512,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13864479 # Number of BP lookups -system.cpu.branchPred.condPredicted 11634507 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 398117 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9551974 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5822395 # Number of BTB hits +system.cpu.branchPred.lookups 13863448 # Number of BP lookups +system.cpu.branchPred.condPredicted 11631259 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 399718 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9400932 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5821857 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 60.954887 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 906213 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 38605 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.928509 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 906521 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 39211 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9930859 # DTB read hits -system.cpu.dtb.read_misses 42001 # DTB read misses -system.cpu.dtb.read_acv 541 # DTB read access violations -system.cpu.dtb.read_accesses 942214 # DTB read accesses -system.cpu.dtb.write_hits 6592411 # DTB write hits -system.cpu.dtb.write_misses 10345 # DTB write misses +system.cpu.dtb.read_hits 9926517 # DTB read hits +system.cpu.dtb.read_misses 41406 # DTB read misses +system.cpu.dtb.read_acv 531 # DTB read access violations +system.cpu.dtb.read_accesses 940700 # DTB read accesses +system.cpu.dtb.write_hits 6593963 # DTB write hits +system.cpu.dtb.write_misses 10630 # DTB write misses system.cpu.dtb.write_acv 410 # DTB write access violations -system.cpu.dtb.write_accesses 337923 # DTB write accesses -system.cpu.dtb.data_hits 16523270 # DTB hits -system.cpu.dtb.data_misses 52346 # DTB misses -system.cpu.dtb.data_acv 951 # DTB access violations -system.cpu.dtb.data_accesses 1280137 # DTB accesses -system.cpu.itb.fetch_hits 1308071 # ITB hits -system.cpu.itb.fetch_misses 36703 # ITB misses -system.cpu.itb.fetch_acv 1058 # ITB acv -system.cpu.itb.fetch_accesses 1344774 # ITB accesses +system.cpu.dtb.write_accesses 338096 # DTB write accesses +system.cpu.dtb.data_hits 16520480 # DTB hits +system.cpu.dtb.data_misses 52036 # DTB misses +system.cpu.dtb.data_acv 941 # DTB access violations +system.cpu.dtb.data_accesses 1278796 # DTB accesses +system.cpu.itb.fetch_hits 1306353 # ITB hits +system.cpu.itb.fetch_misses 36823 # ITB misses +system.cpu.itb.fetch_acv 1069 # ITB acv +system.cpu.itb.fetch_accesses 1343176 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -549,269 +553,269 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 121927488 # number of cpu cycles simulated +system.cpu.numCycles 121966998 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28039089 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70847333 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13864479 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6728608 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13268188 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1998523 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 38187764 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33374 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 253703 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 358378 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 313 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8556240 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 264321 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 81433386 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.870004 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.213508 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28067964 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70813073 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13863448 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6728378 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13263425 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1999195 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 38181411 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33091 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 255000 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 364206 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 297 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8556045 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 264477 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 81457086 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.869330 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.212823 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68165198 83.71% 83.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 850053 1.04% 84.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1699284 2.09% 86.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 821371 1.01% 87.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2763942 3.39% 91.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 562061 0.69% 91.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 645266 0.79% 92.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1012758 1.24% 93.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4913453 6.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68193661 83.72% 83.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 852857 1.05% 84.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1696439 2.08% 86.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 825181 1.01% 87.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2758325 3.39% 91.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 561473 0.69% 91.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 645881 0.79% 92.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1010308 1.24% 93.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4912961 6.03% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81433386 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.113711 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.581061 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29221081 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37872240 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12130703 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 959021 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1250340 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 583021 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42672 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69509272 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129850 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1250340 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30372674 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14147971 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20014852 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11335195 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4312352 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65701425 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7084 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 503729 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1544223 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43873094 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79768312 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79589398 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 166462 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38180112 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5692974 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682864 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 240315 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12255388 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10448429 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6906827 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1318660 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 851527 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58223534 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2050984 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56812947 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 113805 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6931173 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3605221 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1390018 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 81433386 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.697662 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.359692 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 81457086 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.113666 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.580592 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29256938 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37863691 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12127839 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 959156 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1249461 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 584263 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42640 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69481989 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129319 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1249461 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30407522 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14148846 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20005990 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11332374 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4312891 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65679549 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7211 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 504797 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1541440 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43855166 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79746051 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79567055 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 166544 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38180329 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5674829 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1682909 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 240455 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12257327 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10441163 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6908790 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1318239 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 851396 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58211664 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2050007 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56814932 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 114609 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6922962 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3587498 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1389025 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 81457086 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.697483 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.359485 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56726750 69.66% 69.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10882649 13.36% 83.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5163201 6.34% 89.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3388782 4.16% 93.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2628492 3.23% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1462722 1.80% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 751690 0.92% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 332968 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 96132 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56746030 69.66% 69.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10887232 13.37% 83.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5162469 6.34% 89.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3392471 4.16% 93.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2625915 3.22% 96.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1461124 1.79% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 753330 0.92% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 332031 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 96484 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 81433386 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 81457086 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 91250 11.56% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 372174 47.14% 58.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 326051 41.30% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91940 11.62% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 373423 47.20% 58.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 325849 41.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38733166 68.18% 68.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61715 0.11% 68.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38737583 68.18% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61738 0.11% 68.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10362094 18.24% 86.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6670366 11.74% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10357242 18.23% 86.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6672763 11.74% 98.33% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 949077 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56812947 # Type of FU issued -system.cpu.iq.rate 0.465957 # Inst issue rate -system.cpu.iq.fu_busy_cnt 789475 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013896 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 195270080 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66882864 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55570085 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692479 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336490 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327821 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57233809 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361327 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 596971 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56814932 # Type of FU issued +system.cpu.iq.rate 0.465822 # Inst issue rate +system.cpu.iq.fu_busy_cnt 791212 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013926 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 195300199 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66861892 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55573336 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692571 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336551 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327871 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57237458 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361400 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 598272 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1356016 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3236 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14012 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 528856 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1348718 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3201 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14139 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 530806 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17919 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 183461 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17937 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 182742 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1250340 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10233655 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 702274 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63801966 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 688802 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10448429 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6906827 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1805093 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512952 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17454 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14012 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 201109 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 411560 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 612669 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56346471 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10001011 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 466475 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1249461 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10237116 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 702035 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63785040 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 690324 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10441163 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6908790 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1805677 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512237 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17569 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14139 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 202047 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411314 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 613361 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56348369 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 9996094 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 466562 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3527448 # number of nop insts executed -system.cpu.iew.exec_refs 16619020 # number of memory reference insts executed -system.cpu.iew.exec_branches 8923746 # Number of branches executed -system.cpu.iew.exec_stores 6618009 # Number of stores executed -system.cpu.iew.exec_rate 0.462131 # Inst execution rate -system.cpu.iew.wb_sent 56013491 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55897906 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27708487 # num instructions producing a value -system.cpu.iew.wb_consumers 37528450 # num instructions consuming a value +system.cpu.iew.exec_nop 3523369 # number of nop insts executed +system.cpu.iew.exec_refs 16615920 # number of memory reference insts executed +system.cpu.iew.exec_branches 8927027 # Number of branches executed +system.cpu.iew.exec_stores 6619826 # Number of stores executed +system.cpu.iew.exec_rate 0.461997 # Inst execution rate +system.cpu.iew.wb_sent 56016387 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55901207 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27709617 # num instructions producing a value +system.cpu.iew.wb_consumers 37531222 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.458452 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738333 # average fanout of values written-back +system.cpu.iew.wb_rate 0.458331 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738308 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7515002 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660966 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 566897 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80183046 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.700527 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.629598 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7496348 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660982 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 568504 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80207625 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.700316 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.629380 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59370328 74.04% 74.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8654728 10.79% 84.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4617014 5.76% 90.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2519187 3.14% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1509953 1.88% 95.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 613300 0.76% 96.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 523538 0.65% 97.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 523484 0.65% 97.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1851514 2.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59390670 74.05% 74.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8659340 10.80% 84.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4620197 5.76% 90.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2517886 3.14% 93.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1507376 1.88% 95.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 612052 0.76% 96.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 525608 0.66% 97.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 522089 0.65% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1852407 2.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80183046 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56170357 # Number of instructions committed -system.cpu.commit.committedOps 56170357 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 80207625 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56170683 # Number of instructions committed +system.cpu.commit.committedOps 56170683 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15470384 # Number of memory references committed -system.cpu.commit.loads 9092413 # Number of loads committed -system.cpu.commit.membars 226354 # Number of memory barriers committed -system.cpu.commit.branches 8439829 # Number of branches committed +system.cpu.commit.refs 15470429 # Number of memory references committed +system.cpu.commit.loads 9092445 # Number of loads committed +system.cpu.commit.membars 226358 # Number of memory barriers committed +system.cpu.commit.branches 8439899 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52019973 # Number of committed integer instructions. -system.cpu.commit.function_calls 740579 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1851514 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52020266 # Number of committed integer instructions. +system.cpu.commit.function_calls 740581 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1852407 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141767299 # The number of ROB reads -system.cpu.rob.rob_writes 128622610 # The number of ROB writes -system.cpu.timesIdled 1192878 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 40494102 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3598461292 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52979573 # Number of Instructions Simulated -system.cpu.committedOps 52979573 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52979573 # Number of Instructions Simulated -system.cpu.cpi 2.301406 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.301406 # CPI: Total CPI of All Threads -system.cpu.ipc 0.434517 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.434517 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73879526 # number of integer regfile reads -system.cpu.int_regfile_writes 40317649 # number of integer regfile writes -system.cpu.fp_regfile_reads 165968 # number of floating regfile reads -system.cpu.fp_regfile_writes 167427 # number of floating regfile writes -system.cpu.misc_regfile_reads 1984782 # number of misc regfile reads -system.cpu.misc_regfile_writes 938976 # number of misc regfile writes +system.cpu.rob.rob_reads 141772543 # The number of ROB reads +system.cpu.rob.rob_writes 128585215 # The number of ROB writes +system.cpu.timesIdled 1193212 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 40509912 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3598422122 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52979882 # Number of Instructions Simulated +system.cpu.committedOps 52979882 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52979882 # Number of Instructions Simulated +system.cpu.cpi 2.302138 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.302138 # CPI: Total CPI of All Threads +system.cpu.ipc 0.434379 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.434379 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73881277 # number of integer regfile reads +system.cpu.int_regfile_writes 40316653 # number of integer regfile writes +system.cpu.fp_regfile_reads 166009 # number of floating regfile reads +system.cpu.fp_regfile_writes 167434 # number of floating regfile writes +system.cpu.misc_regfile_reads 1986207 # number of misc regfile reads +system.cpu.misc_regfile_writes 938984 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -903,225 +907,233 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 377740446 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 377738948 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42670757 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42679505 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.throughput 111891693 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2116597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2116497 # Transaction distribution +system.cpu.toL2Bus.throughput 111941811 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2118263 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2118167 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 840887 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 63 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 840743 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 65 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 342605 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301054 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 83 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2016984 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3678218 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5695202 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64539584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143593268 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 208132852 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 208122804 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 17856 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2479701498 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::UpgradeResp 66 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 342536 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 300985 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 79 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2020543 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677710 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5698253 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64653440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143572596 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 208226036 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 208215988 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 17920 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2480284498 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1516139861 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1518802860 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2192873665 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2192631666 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 1007825 # number of replacements -system.cpu.icache.tags.tagsinuse 509.660233 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7491263 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1008333 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.429354 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1009602 # number of replacements +system.cpu.icache.tags.tagsinuse 509.660060 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7489391 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1010110 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.414431 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 26489829250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.660233 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 509.660060 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.995430 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.995430 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7491264 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7491264 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7491264 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7491264 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7491264 # number of overall hits -system.cpu.icache.overall_hits::total 7491264 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1064974 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1064974 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1064974 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1064974 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1064974 # number of overall misses -system.cpu.icache.overall_misses::total 1064974 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14872208186 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14872208186 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14872208186 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14872208186 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14872208186 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14872208186 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8556238 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8556238 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8556238 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8556238 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8556238 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8556238 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124468 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124468 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124468 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124468 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124468 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124468 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13964.855655 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13964.855655 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13964.855655 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13964.855655 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13964.855655 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13964.855655 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5226 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 7489392 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7489392 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7489392 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7489392 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7489392 # number of overall hits +system.cpu.icache.overall_hits::total 7489392 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1066652 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1066652 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1066652 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1066652 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1066652 # number of overall misses +system.cpu.icache.overall_misses::total 1066652 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14896343949 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14896343949 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14896343949 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14896343949 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14896343949 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14896343949 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8556044 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8556044 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8556044 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8556044 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8556044 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8556044 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124666 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.124666 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.124666 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.124666 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.124666 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.124666 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13965.514478 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13965.514478 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13965.514478 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13965.514478 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13965.514478 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13965.514478 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4660 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 214 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 199 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 24.420561 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 23.417085 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56421 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 56421 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 56421 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 56421 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 56421 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 56421 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1008553 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1008553 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1008553 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1008553 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1008553 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1008553 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12184986133 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12184986133 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12184986133 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12184986133 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12184986133 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12184986133 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117873 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117873 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117873 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.117873 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117873 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.117873 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12081.651765 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12081.651765 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12081.651765 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12081.651765 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12081.651765 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12081.651765 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56319 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 56319 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 56319 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 56319 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 56319 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 56319 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010333 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1010333 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1010333 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1010333 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1010333 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1010333 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12206065633 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12206065633 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12206065633 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12206065633 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12206065633 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12206065633 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118084 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118084 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118084 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.118084 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118084 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.118084 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12081.230281 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12081.230281 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12081.230281 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12081.230281 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12081.230281 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12081.230281 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 338320 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65339.826573 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2544675 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 403486 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.306724 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 338298 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65338.001327 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2546240 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 403465 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.310932 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 5511908750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 53856.157750 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5301.221918 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6182.446905 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.821780 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.080890 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.094337 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997007 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 993358 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 827156 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1820514 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 840887 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 840887 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 24 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 24 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 185595 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 185595 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 993358 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1012751 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2006109 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 993358 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1012751 # number of overall hits -system.cpu.l2cache.overall_hits::total 2006109 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 15073 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 273785 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 288858 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 39 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 39 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 115458 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 115458 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15073 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389243 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404316 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15073 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389243 # number of overall misses -system.cpu.l2cache.overall_misses::total 404316 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1217060992 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17822778727 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19039839719 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 308496 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 308496 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9541842859 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9541842859 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1217060992 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 27364621586 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28581682578 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1217060992 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 27364621586 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28581682578 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1008431 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1100941 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2109372 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 840887 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 840887 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 63 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 63 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.tags.occ_blocks::writebacks 53847.908430 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5309.513440 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6180.579458 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.821654 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081017 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.094308 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996979 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 995146 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 827013 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1822159 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 840743 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 840743 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 185570 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 185570 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 995146 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1012583 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2007729 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 995146 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1012583 # number of overall hits +system.cpu.l2cache.overall_hits::total 2007729 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 15064 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 273814 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 288878 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 38 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 38 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 115414 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 115414 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 15064 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 389228 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404292 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 15064 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 389228 # number of overall misses +system.cpu.l2cache.overall_misses::total 404292 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1218545993 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17819527728 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19038073721 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 262498 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 262498 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 22999 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 22999 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9547009857 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9547009857 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1218545993 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 27366537585 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28585083578 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1218545993 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 27366537585 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28585083578 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1010210 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1100827 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2111037 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 840743 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 840743 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 64 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 64 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 301053 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 301053 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1008431 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1401994 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2410425 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1008431 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1401994 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2410425 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014947 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248683 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.136940 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.619048 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.619048 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383514 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383514 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014947 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.277635 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.167736 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014947 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.277635 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.167736 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80744.443177 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65097.718016 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 65914.185236 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7910.153846 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7910.153846 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82643.410236 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82643.410236 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80744.443177 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70302.154659 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70691.445745 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80744.443177 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70302.154659 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70691.445745 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 300984 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 300984 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1010210 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1401811 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2412021 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1010210 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1401811 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2412021 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014912 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248735 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.136842 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.593750 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.593750 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383456 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383456 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014912 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.277661 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.167615 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014912 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.277661 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.167615 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80891.263476 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65078.950412 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 65903.508474 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6907.842105 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6907.842105 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 22999 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 22999 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82719.686147 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82719.686147 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80891.263476 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70309.786513 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70704.054441 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80891.263476 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70309.786513 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70704.054441 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1130,72 +1142,80 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75936 # number of writebacks -system.cpu.l2cache.writebacks::total 75936 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 75917 # number of writebacks +system.cpu.l2cache.writebacks::total 75917 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15072 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273785 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 288857 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 39 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 39 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115458 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115458 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15072 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389243 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404315 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15072 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389243 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404315 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1026861258 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14410483773 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15437345031 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 542534 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 542534 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8118910641 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8118910641 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1026861258 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22529394414 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23556255672 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1026861258 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22529394414 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23556255672 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334047500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334047500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882613000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882613000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216660500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216660500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014946 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248683 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136940 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.619048 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.619048 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383514 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383514 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014946 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277635 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.167736 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014946 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277635 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.167736 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68130.391322 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52634.307113 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53442.862839 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13911.128205 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13911.128205 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70319.169230 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70319.169230 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68130.391322 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57880.024596 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58262.136384 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68130.391322 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57880.024596 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58262.136384 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15063 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273814 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288877 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 38 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115414 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115414 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15063 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389228 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404291 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15063 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389228 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404291 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1028470757 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14406345772 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15434816529 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 532033 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 532033 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8124534143 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8124534143 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1028470757 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22530879915 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23559350672 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1028470757 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22530879915 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23559350672 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333940000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333940000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882589500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882589500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216529500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216529500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014911 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136841 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.593750 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.593750 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383456 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383456 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014911 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277661 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.167615 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014911 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277661 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.167615 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68277.949744 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52613.620092 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53430.409929 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14000.868421 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14000.868421 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70394.702055 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70394.702055 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68277.949744 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57886.071698 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58273.250386 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68277.949744 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57886.071698 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58273.250386 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1203,161 +1223,161 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1401398 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994568 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11815525 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1401910 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.428162 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1401219 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994567 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11810743 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1401731 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.425827 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 25477000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994568 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994567 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7210216 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7210216 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4203313 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4203313 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186240 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186240 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215515 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215515 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11413529 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11413529 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11413529 # number of overall hits -system.cpu.dcache.overall_hits::total 11413529 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1806580 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1806580 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1944438 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1944438 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22731 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22731 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 7205308 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7205308 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4203634 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4203634 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186044 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186044 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215517 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215517 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11408942 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11408942 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11408942 # number of overall hits +system.cpu.dcache.overall_hits::total 11408942 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1806790 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1806790 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1944128 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1944128 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22738 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22738 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3751018 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3751018 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3751018 # number of overall misses -system.cpu.dcache.overall_misses::total 3751018 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 40329752439 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 40329752439 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 77181819403 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 77181819403 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 321716499 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 321716499 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 117511571842 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 117511571842 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 117511571842 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 117511571842 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9016796 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9016796 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208971 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 208971 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215517 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215517 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15164547 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15164547 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15164547 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15164547 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200357 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.200357 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316284 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316284 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108776 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 3750918 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3750918 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3750918 # number of overall misses +system.cpu.dcache.overall_misses::total 3750918 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40335866684 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40335866684 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 77256495609 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 77256495609 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 322518001 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 322518001 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 39001 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 39001 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 117592362293 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 117592362293 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 117592362293 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 117592362293 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9012098 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9012098 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147762 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147762 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208782 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 208782 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215519 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215519 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15159860 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15159860 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15159860 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15159860 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200485 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.200485 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316233 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316233 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108908 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108908 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247354 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247354 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247354 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247354 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22323.812086 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22323.812086 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39693.638678 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39693.638678 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14153.204830 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14153.204830 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31327.914673 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31327.914673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31327.914673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31327.914673 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3032993 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.247424 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247424 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247424 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247424 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22324.601467 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22324.601467 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39738.379165 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39738.379165 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14184.097150 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14184.097150 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19500.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31350.288727 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31350.288727 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31350.288727 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31350.288727 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3041849 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 733 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 98350 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 98391 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.838770 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.915927 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 104.714286 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840887 # number of writebacks -system.cpu.dcache.writebacks::total 840887 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722519 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 722519 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643978 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1643978 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5197 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5197 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2366497 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2366497 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2366497 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2366497 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084061 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1084061 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300460 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300460 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17534 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17534 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 840743 # number of writebacks +system.cpu.dcache.writebacks::total 840743 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722826 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 722826 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643736 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1643736 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5220 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5220 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2366562 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2366562 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2366562 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2366562 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083964 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083964 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300392 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300392 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17518 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17518 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384521 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384521 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384521 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384521 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27189046254 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27189046254 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11757002855 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11757002855 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200761751 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200761751 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38946049109 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 38946049109 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38946049109 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 38946049109 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424137500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424137500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997802998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997802998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421940498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421940498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120227 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120227 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048873 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048873 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1384356 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384356 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384356 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384356 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27183263254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27183263254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11761438359 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11761438359 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200916999 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200916999 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 34999 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 34999 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38944701613 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 38944701613 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38944701613 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 38944701613 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424030000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424030000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997779498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997779498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421809498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421809498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120279 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120279 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048862 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048862 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083906 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083906 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091300 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091300 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091300 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091300 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25080.734621 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25080.734621 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39130.010168 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39130.010168 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11449.854625 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11449.854625 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28129.619637 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28129.619637 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28129.619637 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28129.619637 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091317 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091317 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091317 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091317 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25077.643957 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25077.643957 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39153.633782 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39153.633782 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11469.174506 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11469.174506 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17499.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17499.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28131.999004 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28131.999004 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28131.999004 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28131.999004 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1366,7 +1386,7 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6437 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed system.cpu.kern.inst.hwrei 211017 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl @@ -1378,11 +1398,11 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.41% # nu system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 148607 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818037303500 97.73% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64303500 0.00% 97.74% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 561270000 0.03% 97.77% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41533903500 2.23% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1860196780500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1818029044000 97.73% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64103000 0.00% 97.74% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 561251500 0.03% 97.77% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 41542545500 2.23% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1860196944000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -1446,9 +1466,9 @@ system.cpu.kern.mode_switch_good::kernel 0.326384 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.394343 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29638597000 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2732860000 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827825315500 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 29636227500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2736556500 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827824152000 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini index 8b5822c19..8069712e0 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -13,15 +15,16 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/dist/m5/system/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console +eventq_index=0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -39,6 +42,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 @@ -48,6 +52,7 @@ slave=system.membus.master[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -60,6 +65,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -93,6 +99,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -115,11 +122,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu0.icache] @@ -128,6 +137,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -150,21 +160,26 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu0.isa] type=AlphaISA +eventq_index=0 [system.cpu0.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=TimingSimpleCPU @@ -176,6 +191,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=Null @@ -196,17 +212,21 @@ workload= [system.cpu1.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu1.isa] type=AlphaISA +eventq_index=0 [system.cpu1.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu2] type=DerivO3CPU @@ -237,6 +257,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu2.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -299,6 +321,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -310,21 +333,25 @@ predType=tournament [system.cpu2.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu2.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 +eventq_index=0 [system.cpu2.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu2.fuPool.FUList0.opList [system.cpu2.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -333,16 +360,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 [system.cpu2.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu2.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -351,22 +381,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 [system.cpu2.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu2.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu2.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -375,22 +409,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 [system.cpu2.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu2.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu2.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -399,10 +437,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList4.opList [system.cpu2.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -411,124 +451,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 [system.cpu2.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu2.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu2.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu2.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu2.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu2.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu2.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu2.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu2.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu2.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu2.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu2.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu2.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu2.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu2.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu2.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu2.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu2.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -537,10 +598,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList6.opList [system.cpu2.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -549,16 +612,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 [system.cpu2.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu2.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -567,27 +633,33 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu2.fuPool.FUList8.opList [system.cpu2.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 [system.cpu2.isa] type=AlphaISA +eventq_index=0 [system.cpu2.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu2.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.disk0] @@ -595,19 +667,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk0.image [system.disk0.image] type=CowDiskImage children=child child=system.disk0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -615,28 +690,33 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk2.image [system.disk2.image] type=CowDiskImage children=child child=system.disk2.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -650,6 +730,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -672,6 +753,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -681,6 +763,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -703,6 +786,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -710,6 +794,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -721,6 +806,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -747,6 +833,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -758,29 +845,35 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[1] [system.simple_disk] type=SimpleDisk children=disk disk=system.simple_disk.disk +eventq_index=0 system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -789,6 +882,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -799,6 +893,7 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +eventq_index=0 intrctrl=system.intrctrl system=system @@ -807,6 +902,7 @@ type=AlphaBackdoor clk_domain=system.clk_domain cpu=system.cpu0 disk=system.simple_disk +eventq_index=0 pio_addr=8804682956800 pio_latency=100000 platform=system.tsunami @@ -817,6 +913,7 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8803072344064 pio_latency=100000 system=system @@ -845,6 +942,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=2 Command=0 @@ -854,8 +952,40 @@ HeaderType=0 InterruptLine=30 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=52 MinimumGrant=176 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=0 Revision=0 Status=656 @@ -872,6 +1002,7 @@ dma_read_delay=0 dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 +eventq_index=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 pci_bus=0 @@ -895,6 +1026,7 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8796093677568 pio_latency=100000 @@ -912,6 +1044,7 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848432 pio_latency=100000 @@ -929,6 +1062,7 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848304 pio_latency=100000 @@ -946,6 +1080,7 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848569 pio_latency=100000 @@ -963,6 +1098,7 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848451 pio_latency=100000 @@ -980,6 +1116,7 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848515 pio_latency=100000 @@ -997,6 +1134,7 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848579 pio_latency=100000 @@ -1014,6 +1152,7 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848643 pio_latency=100000 @@ -1031,6 +1170,7 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848707 pio_latency=100000 @@ -1048,6 +1188,7 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848771 pio_latency=100000 @@ -1065,6 +1206,7 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848835 pio_latency=100000 @@ -1082,6 +1224,7 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848899 pio_latency=100000 @@ -1099,6 +1242,7 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615850617 pio_latency=100000 @@ -1116,6 +1260,7 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848891 pio_latency=100000 @@ -1133,6 +1278,7 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848816 pio_latency=100000 @@ -1150,6 +1296,7 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848696 pio_latency=100000 @@ -1167,6 +1314,7 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848936 pio_latency=100000 @@ -1184,6 +1332,7 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848680 pio_latency=100000 @@ -1201,6 +1350,7 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848944 pio_latency=100000 @@ -1219,6 +1369,7 @@ pio=system.iobus.master[6] type=BadDevice clk_domain=system.clk_domain devicename=FrameBuffer +eventq_index=0 pio_addr=8804615848912 pio_latency=100000 system=system @@ -1246,6 +1397,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -1255,8 +1407,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -1268,6 +1452,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=0 @@ -1282,6 +1467,7 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO clk_domain=system.clk_domain +eventq_index=0 frequency=976562500 pio_addr=8804615847936 pio_latency=100000 @@ -1294,6 +1480,7 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8802535473152 pio_latency=100000 system=system @@ -1304,6 +1491,7 @@ pio=system.iobus.master[1] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.tsunami @@ -1314,6 +1502,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain +eventq_index=0 pio_addr=8804615848952 pio_latency=100000 platform=system.tsunami @@ -1323,5 +1512,6 @@ pio=system.iobus.master[23] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 739cb26e4..caa1e9081 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,145 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.842698 # Number of seconds simulated -sim_ticks 1842698476000 # Number of ticks simulated -final_tick 1842698476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.842697 # Number of seconds simulated +sim_ticks 1842697218000 # Number of ticks simulated +final_tick 1842697218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 222585 # Simulator instruction rate (inst/s) -host_op_rate 222585 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5605413242 # Simulator tick rate (ticks/s) -host_mem_usage 334468 # Number of bytes of host memory used -host_seconds 328.74 # Real time elapsed on the host -sim_insts 73171582 # Number of instructions simulated -sim_ops 73171582 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 489344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20103680 # Number of bytes read from this memory +host_inst_rate 189301 # Simulator instruction rate (inst/s) +host_op_rate 189301 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4767309141 # Simulator tick rate (ticks/s) +host_mem_usage 353980 # Number of bytes of host memory used +host_seconds 386.53 # Real time elapsed on the host +sim_insts 73170192 # Number of instructions simulated +sim_ops 73170192 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 489152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20102912 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 144384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2235712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 284736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2526400 # Number of bytes read from this memory -system.physmem.bytes_read::total 28436608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 489344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 144384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 284736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 918464 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7460736 # Number of bytes written to this memory -system.physmem.bytes_written::total 7460736 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7646 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 314120 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 144448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2236224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 284928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2526528 # Number of bytes read from this memory +system.physmem.bytes_read::total 28436544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 489152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 144448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 284928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 918528 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7459712 # Number of bytes written to this memory +system.physmem.bytes_written::total 7459712 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7643 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 314108 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2256 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 34933 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4449 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39475 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444322 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116574 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116574 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 265558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10909913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1439385 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 78355 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1213282 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 154521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1371033 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15432046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 265558 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 78355 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 154521 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498434 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4048810 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4048810 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4048810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 265558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10909913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1439385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 78355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1213282 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 154521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1371033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19480856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 98004 # Number of read requests accepted -system.physmem.writeReqs 44399 # Number of write requests accepted -system.physmem.readBursts 98004 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 44399 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6271808 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 2840768 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6272256 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2841536 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu1.inst 2257 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 34941 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4452 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39477 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444321 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116558 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116558 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 265454 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10909504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1439386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 78389 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1213560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 154626 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1371103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15432022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 265454 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 78389 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 154626 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498469 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4048257 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4048257 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4048257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 265454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10909504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1439386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 78389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1213560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 154626 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1371103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19480279 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 98018 # Number of read requests accepted +system.physmem.writeReqs 44365 # Number of write requests accepted +system.physmem.readBursts 98018 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 44365 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6272576 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue +system.physmem.bytesWritten 2838464 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6273152 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2839360 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6232 # Per bank write bursts -system.physmem.perBankRdBursts::1 6028 # Per bank write bursts -system.physmem.perBankRdBursts::2 6221 # Per bank write bursts -system.physmem.perBankRdBursts::3 6513 # Per bank write bursts -system.physmem.perBankRdBursts::4 5794 # Per bank write bursts -system.physmem.perBankRdBursts::5 6242 # Per bank write bursts -system.physmem.perBankRdBursts::6 5925 # Per bank write bursts -system.physmem.perBankRdBursts::7 6039 # Per bank write bursts -system.physmem.perBankRdBursts::8 6348 # Per bank write bursts -system.physmem.perBankRdBursts::9 6026 # Per bank write bursts -system.physmem.perBankRdBursts::10 6373 # Per bank write bursts -system.physmem.perBankRdBursts::11 5867 # Per bank write bursts -system.physmem.perBankRdBursts::12 5876 # Per bank write bursts -system.physmem.perBankRdBursts::13 6234 # Per bank write bursts -system.physmem.perBankRdBursts::14 6235 # Per bank write bursts -system.physmem.perBankRdBursts::15 6044 # Per bank write bursts -system.physmem.perBankWrBursts::0 2859 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 42 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6238 # Per bank write bursts +system.physmem.perBankRdBursts::1 6029 # Per bank write bursts +system.physmem.perBankRdBursts::2 6222 # Per bank write bursts +system.physmem.perBankRdBursts::3 6415 # Per bank write bursts +system.physmem.perBankRdBursts::4 5671 # Per bank write bursts +system.physmem.perBankRdBursts::5 6259 # Per bank write bursts +system.physmem.perBankRdBursts::6 6020 # Per bank write bursts +system.physmem.perBankRdBursts::7 6028 # Per bank write bursts +system.physmem.perBankRdBursts::8 6370 # Per bank write bursts +system.physmem.perBankRdBursts::9 6122 # Per bank write bursts +system.physmem.perBankRdBursts::10 6366 # Per bank write bursts +system.physmem.perBankRdBursts::11 5871 # Per bank write bursts +system.physmem.perBankRdBursts::12 5882 # Per bank write bursts +system.physmem.perBankRdBursts::13 6242 # Per bank write bursts +system.physmem.perBankRdBursts::14 6237 # Per bank write bursts +system.physmem.perBankRdBursts::15 6037 # Per bank write bursts +system.physmem.perBankWrBursts::0 2849 # Per bank write bursts system.physmem.perBankWrBursts::1 2656 # Per bank write bursts -system.physmem.perBankWrBursts::2 2839 # Per bank write bursts -system.physmem.perBankWrBursts::3 3122 # Per bank write bursts -system.physmem.perBankWrBursts::4 2688 # Per bank write bursts -system.physmem.perBankWrBursts::5 2969 # Per bank write bursts -system.physmem.perBankWrBursts::6 2850 # Per bank write bursts -system.physmem.perBankWrBursts::7 2699 # Per bank write bursts -system.physmem.perBankWrBursts::8 3075 # Per bank write bursts -system.physmem.perBankWrBursts::9 2558 # Per bank write bursts -system.physmem.perBankWrBursts::10 2888 # Per bank write bursts -system.physmem.perBankWrBursts::11 2432 # Per bank write bursts -system.physmem.perBankWrBursts::12 2458 # Per bank write bursts -system.physmem.perBankWrBursts::13 2707 # Per bank write bursts -system.physmem.perBankWrBursts::14 2844 # Per bank write bursts -system.physmem.perBankWrBursts::15 2743 # Per bank write bursts +system.physmem.perBankWrBursts::2 2849 # Per bank write bursts +system.physmem.perBankWrBursts::3 3015 # Per bank write bursts +system.physmem.perBankWrBursts::4 2565 # Per bank write bursts +system.physmem.perBankWrBursts::5 2994 # Per bank write bursts +system.physmem.perBankWrBursts::6 2937 # Per bank write bursts +system.physmem.perBankWrBursts::7 2695 # Per bank write bursts +system.physmem.perBankWrBursts::8 3093 # Per bank write bursts +system.physmem.perBankWrBursts::9 2622 # Per bank write bursts +system.physmem.perBankWrBursts::10 2879 # Per bank write bursts +system.physmem.perBankWrBursts::11 2436 # Per bank write bursts +system.physmem.perBankWrBursts::12 2462 # Per bank write bursts +system.physmem.perBankWrBursts::13 2714 # Per bank write bursts +system.physmem.perBankWrBursts::14 2848 # Per bank write bursts +system.physmem.perBankWrBursts::15 2737 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 6 # Number of times write queue was full causing retry -system.physmem.totGap 1841686150500 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times write queue was full causing retry +system.physmem.totGap 1841684892500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 98004 # Read request sizes (log2) +system.physmem.readPktSize::6 98018 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 44399 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 66399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 14093 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 978 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 963 # What read queue length does an incoming req see +system.physmem.writePktSize::6 44365 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 66438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 14086 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2022 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 959 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 394 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 394 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 393 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 553 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 609 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -151,181 +151,177 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 2173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 2221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 2213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 17930 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 508.141439 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 169.008973 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1572.275953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 7528 41.99% 41.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 2973 16.58% 58.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 1838 10.25% 68.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 1006 5.61% 74.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 670 3.74% 78.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 572 3.19% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 359 2.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 327 1.82% 85.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 240 1.34% 86.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 222 1.24% 87.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 225 1.25% 89.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 213 1.19% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 93 0.52% 90.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 79 0.44% 91.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 78 0.44% 91.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 102 0.57% 92.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 45 0.25% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 56 0.31% 92.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 39 0.22% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 53 0.30% 93.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 30 0.17% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 119 0.66% 94.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 70 0.39% 94.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 89 0.50% 94.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 16 0.09% 95.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 17 0.09% 95.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 5 0.03% 95.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 36 0.20% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 6 0.03% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 15 0.08% 95.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 5 0.03% 95.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 15 0.08% 95.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 11 0.06% 95.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 11 0.06% 95.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 2 0.01% 95.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 23 0.13% 95.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 1 0.01% 95.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 12 0.07% 95.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 2 0.01% 95.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 9 0.05% 96.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 2 0.01% 96.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 15 0.08% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 1 0.01% 96.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 22 0.12% 96.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 1 0.01% 96.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 14 0.08% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 4 0.02% 96.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 10 0.06% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 3 0.02% 96.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 12 0.07% 96.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.01% 96.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 20 0.11% 96.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 13 0.07% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 2 0.01% 96.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 7 0.04% 96.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 1 0.01% 96.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 13 0.07% 96.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 21 0.12% 96.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 13 0.07% 96.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 2 0.01% 96.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 8 0.04% 97.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 2 0.01% 97.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 14 0.08% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 23 0.13% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 1 0.01% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 14 0.08% 97.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 2 0.01% 97.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 76 0.42% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 3 0.02% 97.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 19 0.11% 97.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.01% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 4 0.02% 97.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 1 0.01% 97.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 9 0.05% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 5 0.03% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.01% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 21 0.12% 98.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 8 0.04% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 8 0.04% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 3 0.02% 98.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 4 0.02% 98.25% # Bytes accessed per row activation +system.physmem.wrQLenPdf::0 1794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 2181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 2225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 2215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 17929 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 508.069831 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 168.315652 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1577.422962 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 7580 42.28% 42.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 2972 16.58% 58.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 1827 10.19% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 983 5.48% 74.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 676 3.77% 78.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 569 3.17% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 353 1.97% 83.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 316 1.76% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 239 1.33% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 212 1.18% 87.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 225 1.25% 88.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 207 1.15% 90.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 92 0.51% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 80 0.45% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 62 0.35% 91.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 115 0.64% 92.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 35 0.20% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 50 0.28% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 54 0.30% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 63 0.35% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 30 0.17% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 123 0.69% 94.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 74 0.41% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 80 0.45% 94.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 19 0.11% 95.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 17 0.09% 95.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 7 0.04% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 37 0.21% 95.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 7 0.04% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 18 0.10% 95.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 6 0.03% 95.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 15 0.08% 95.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 9 0.05% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 16 0.09% 95.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 1 0.01% 95.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 23 0.13% 95.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 12 0.07% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 4 0.02% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 9 0.05% 96.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 2 0.01% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 15 0.08% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 22 0.12% 96.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 1 0.01% 96.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 14 0.08% 96.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 3 0.02% 96.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 12 0.07% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 2 0.01% 96.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 12 0.07% 96.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.01% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 20 0.11% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 11 0.06% 96.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 2 0.01% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 9 0.05% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 1 0.01% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 13 0.07% 96.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 21 0.12% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 1 0.01% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 13 0.07% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 2 0.01% 97.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 8 0.04% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 3 0.02% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 14 0.08% 97.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 22 0.12% 97.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 13 0.07% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 1 0.01% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 77 0.43% 97.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 3 0.02% 97.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 19 0.11% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 5 0.03% 97.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 2 0.01% 97.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 8 0.04% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 4 0.02% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 21 0.12% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 6 0.03% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 9 0.05% 98.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 2 0.01% 98.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 3 0.02% 98.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::5888-5891 21 0.12% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 3 0.02% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 5 0.03% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 3 0.02% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 6 0.03% 98.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::6272-6275 5 0.03% 98.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::6400-6403 19 0.11% 98.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::6528-6531 6 0.03% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.01% 98.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::6656-6659 6 0.03% 98.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::6784-6787 25 0.14% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 1 0.01% 98.76% # Bytes accessed per row activation system.physmem.bytesPerActivate::6912-6915 15 0.08% 98.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::6976-6979 1 0.01% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 20 0.11% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7491 2 0.01% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 2 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.01% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 2 0.01% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 52 0.29% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 1 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 1 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 2 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 1 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9411 1 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 1 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10051 1 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10243 1 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10691 1 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 4 0.02% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11267 1 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11840-11843 1 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 2 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12739 1 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 1 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13123 1 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 2 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 2 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 1 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14403 1 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 1 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 1 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 1 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 1 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 14 0.08% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 1 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 1 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 76 0.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 17930 # Bytes accessed per row activation -system.physmem.totQLat 2684942500 # Total ticks spent queuing -system.physmem.totMemAccLat 4336678750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 489985000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1161751250 # Total ticks spent accessing banks -system.physmem.avgQLat 27398.21 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 11854.97 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::7040-7043 1 0.01% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 21 0.12% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 4 0.02% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 1 0.01% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 52 0.29% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 1 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 1 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 1 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9411 1 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 1 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 2 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11011 1 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11331 1 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 1 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 1 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 1 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12099 1 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 1 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12803 2 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 1 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 2 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 2 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 1 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 1 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 2 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14467 1 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 1 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 1 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 1 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 1 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 16 0.09% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 1 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 1 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 75 0.42% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 17929 # Bytes accessed per row activation +system.physmem.totQLat 2679388500 # Total ticks spent queuing +system.physmem.totMemAccLat 4331514750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 490045000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1162081250 # Total ticks spent accessing banks +system.physmem.avgQLat 27338.19 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11856.88 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44253.18 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 44195.07 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.40 # Average system read bandwidth in MiByte/s @@ -335,229 +331,233 @@ system.physmem.busUtil 0.04 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.18 # Average write queue length when enqueuing -system.physmem.readRowHits 89612 # Number of row buffer hits during reads -system.physmem.writeRowHits 34842 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.47 # Row buffer hit rate for writes -system.physmem.avgGap 12932916.80 # Average gap between requests +system.physmem.avgWrQLen 0.16 # Average write queue length when enqueuing +system.physmem.readRowHits 89637 # Number of row buffer hits during reads +system.physmem.writeRowHits 34794 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.46 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.43 # Row buffer hit rate for writes +system.physmem.avgGap 12934724.60 # Average gap between requests system.physmem.pageHitRate 87.40 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 0.21 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 19524796 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 44746 # Transaction distribution -system.membus.trans_dist::ReadResp 44539 # Transaction distribution -system.membus.trans_dist::WriteReq 3750 # Transaction distribution -system.membus.trans_dist::WriteResp 3750 # Transaction distribution -system.membus.trans_dist::Writeback 44399 # Transaction distribution -system.membus.trans_dist::UpgradeReq 43 # Transaction distribution -system.membus.trans_dist::UpgradeResp 43 # Transaction distribution -system.membus.trans_dist::ReadExReq 56527 # Transaction distribution -system.membus.trans_dist::ReadExResp 56527 # Transaction distribution -system.membus.trans_dist::BadAddressError 207 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13312 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 189934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 414 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 203660 # Packet count per connected master and slave (bytes) +system.membus.throughput 19524219 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 44737 # Transaction distribution +system.membus.trans_dist::ReadResp 44533 # Transaction distribution +system.membus.trans_dist::WriteReq 3749 # Transaction distribution +system.membus.trans_dist::WriteResp 3749 # Transaction distribution +system.membus.trans_dist::Writeback 44365 # Transaction distribution +system.membus.trans_dist::UpgradeReq 45 # Transaction distribution +system.membus.trans_dist::UpgradeResp 45 # Transaction distribution +system.membus.trans_dist::ReadExReq 56547 # Transaction distribution +system.membus.trans_dist::ReadExResp 56547 # Transaction distribution +system.membus.trans_dist::BadAddressError 204 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13310 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 189932 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 408 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 203650 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 50712 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 50712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 254372 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15690 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6953984 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 6969674 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 254362 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15689 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6952704 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 6968393 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2159808 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 2159808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 9129482 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35968328 # Total data (bytes) +system.membus.tot_pkt_size::total 9128201 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35967240 # Total data (bytes) system.membus.snoop_data_through_bus 9984 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12460500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 12468500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 511769750 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 514332500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 256500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 252500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 762797456 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 764298954 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 153003500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 152995500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 337399 # number of replacements -system.l2c.tags.tagsinuse 65421.710089 # Cycle average of tags in use -system.l2c.tags.total_refs 2471820 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402562 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.140222 # Average number of references to valid blocks. +system.l2c.tags.replacements 337398 # number of replacements +system.l2c.tags.tagsinuse 65420.701532 # Cycle average of tags in use +system.l2c.tags.total_refs 2472173 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402561 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.141114 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54901.425298 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2456.924718 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2698.289857 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 528.309889 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 619.621947 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2142.597203 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2074.541175 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.837729 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.037490 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041173 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008061 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009455 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.032693 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.031655 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998256 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 520374 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 492975 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 124091 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 84248 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 292559 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 239147 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1753394 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835552 # number of Writeback hits -system.l2c.Writeback_hits::total 835552 # number of Writeback hits +system.l2c.tags.occ_blocks::writebacks 54886.932182 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2458.825580 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2703.778525 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 528.462620 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 622.296328 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2148.830278 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2071.576019 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.837508 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.037519 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.041256 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008064 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009495 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.032789 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.031610 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998241 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 520243 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 493553 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 124286 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 83912 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 292769 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 239004 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1753767 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835523 # number of Writeback hits +system.l2c.Writeback_hits::total 835523 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 7 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 92855 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 26292 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 67775 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186922 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 520374 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 585830 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 124091 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 110540 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 292559 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 306922 # number of demand (read+write) hits -system.l2c.demand_hits::total 1940316 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 520374 # number of overall hits -system.l2c.overall_hits::cpu0.data 585830 # number of overall hits -system.l2c.overall_hits::cpu1.inst 124091 # number of overall hits -system.l2c.overall_hits::cpu1.data 110540 # number of overall hits -system.l2c.overall_hits::cpu2.inst 292559 # number of overall hits -system.l2c.overall_hits::cpu2.data 306922 # number of overall hits -system.l2c.overall_hits::total 1940316 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 7646 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 238323 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2256 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 16912 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 4449 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 18154 # number of ReadReq misses -system.l2c.ReadReq_misses::total 287740 # number of ReadReq misses +system.l2c.SCUpgradeReq_hits::cpu2.data 1 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 92938 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 26217 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 67761 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 186916 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 520243 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 586491 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 124286 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 110129 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 292769 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 306765 # number of demand (read+write) hits +system.l2c.demand_hits::total 1940683 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 520243 # number of overall hits +system.l2c.overall_hits::cpu0.data 586491 # number of overall hits +system.l2c.overall_hits::cpu1.inst 124286 # number of overall hits +system.l2c.overall_hits::cpu1.data 110129 # number of overall hits +system.l2c.overall_hits::cpu2.inst 292769 # number of overall hits +system.l2c.overall_hits::cpu2.data 306765 # number of overall hits +system.l2c.overall_hits::total 1940683 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 7643 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 238324 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2257 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 16911 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 4452 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 18142 # number of ReadReq misses +system.l2c.ReadReq_misses::total 287729 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 10 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 18 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 76073 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 18069 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 21595 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 115737 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 7646 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 314396 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2256 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 34981 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 4449 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 39749 # number of demand (read+write) misses -system.l2c.demand_misses::total 403477 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 7646 # number of overall misses -system.l2c.overall_misses::cpu0.data 314396 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2256 # number of overall misses -system.l2c.overall_misses::cpu1.data 34981 # number of overall misses -system.l2c.overall_misses::cpu2.inst 4449 # number of overall misses -system.l2c.overall_misses::cpu2.data 39749 # number of overall misses -system.l2c.overall_misses::total 403477 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.inst 174436247 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 1133429750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 361724750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 1201174749 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2870765496 # number of ReadReq miss cycles +system.l2c.UpgradeReq_misses::cpu2.data 12 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 20 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 76060 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 18078 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 21606 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 115744 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 7643 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 314384 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2257 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 34989 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 4452 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 39748 # number of demand (read+write) misses +system.l2c.demand_misses::total 403473 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 7643 # number of overall misses +system.l2c.overall_misses::cpu0.data 314384 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2257 # number of overall misses +system.l2c.overall_misses::cpu1.data 34989 # number of overall misses +system.l2c.overall_misses::cpu2.inst 4452 # number of overall misses +system.l2c.overall_misses::cpu2.data 39748 # number of overall misses +system.l2c.overall_misses::total 403473 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.inst 176426247 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 1131345000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 358514250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 1201423499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2867708996 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu2.data 294997 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 294997 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1255826741 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1783349726 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 3039176467 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.inst 174436247 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2389256491 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 361724750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 2984524475 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 5909941963 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.inst 174436247 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2389256491 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 361724750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 2984524475 # number of overall miss cycles -system.l2c.overall_miss_latency::total 5909941963 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 528020 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 731298 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 126347 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 101160 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 297008 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 257301 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2041134 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 835552 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835552 # number of Writeback accesses(hits+misses) +system.l2c.ReadExReq_miss_latency::cpu1.data 1254698241 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1776085226 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 3030783467 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 176426247 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2386043241 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 358514250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 2977508725 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 5898492463 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 176426247 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2386043241 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 358514250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 2977508725 # number of overall miss cycles +system.l2c.overall_miss_latency::total 5898492463 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 527886 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 731877 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 126543 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 100823 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 297221 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 257146 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2041496 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 835523 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835523 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 13 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 25 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 168928 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 44361 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 89370 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 302659 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 528020 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 900226 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 126347 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 145521 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 297008 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 346671 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2343793 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 528020 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 900226 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 126347 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 145521 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 297008 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 346671 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2343793 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014481 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.325890 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.017856 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.167181 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 27 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu2.data 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 168998 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 44295 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 89367 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 302660 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 527886 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 900875 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 126543 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 145118 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 297221 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 346513 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2344156 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 527886 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 900875 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 126543 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 145118 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 297221 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 346513 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2344156 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014479 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.325634 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.017836 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.167730 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.inst 0.014979 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.070555 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.140971 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.070551 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.140940 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.769231 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.720000 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.450328 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.407317 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.241636 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.382401 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014481 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.349241 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.017856 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.240385 # miss rate for demand accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.800000 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.740741 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.450064 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.408127 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.241767 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.382423 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014479 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.348976 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.017836 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.241107 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.inst 0.014979 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.114659 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.172147 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014481 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.349241 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.017856 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.240385 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu2.data 0.114709 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.172119 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014479 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.348976 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.017836 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.241107 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.inst 0.014979 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.114659 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.172147 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77321.031472 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 67019.261471 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 81304.731400 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 66165.844938 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 9976.942712 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 29499.700000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 16388.722222 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69501.728983 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82581.603427 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 26259.333377 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 77321.031472 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 68301.549155 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 81304.731400 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 75084.265642 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 14647.531242 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 77321.031472 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 68301.549155 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 81304.731400 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 75084.265642 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 14647.531242 # average overall miss latency +system.l2c.overall_miss_rate::cpu2.data 0.114709 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.172119 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78168.474524 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 66899.946780 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 80528.807278 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 66223.321519 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 9966.701292 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 24583.083333 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 14749.850000 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69404.704115 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82203.333611 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 26185.231779 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 78168.474524 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 68194.096459 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 80528.807278 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 74909.648913 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 14619.299093 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 78168.474524 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 68194.096459 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 80528.807278 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 74909.648913 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 14619.299093 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -566,97 +566,97 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 75062 # number of writebacks -system.l2c.writebacks::total 75062 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu1.inst 2256 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 16912 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 4449 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 18154 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 41771 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 10 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 18069 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 21595 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 39664 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2256 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 34981 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 4449 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 39749 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 81435 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2256 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 34981 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 4449 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 39749 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 81435 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 146027753 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 921761250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 305687750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 999134251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 2372611004 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 259007 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 259007 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1029550759 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1518288274 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 2547839033 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 146027753 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1951312009 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 305687750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 2517422525 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 4920450037 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 146027753 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1951312009 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 305687750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 2517422525 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 4920450037 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 277798500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 291495500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 569294000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 343775500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 402311000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 746086500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 621574000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 693806500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1315380500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.017856 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.167181 # mshr miss rate for ReadReq accesses +system.l2c.writebacks::writebacks 75046 # number of writebacks +system.l2c.writebacks::total 75046 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu1.inst 2257 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 16911 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 4452 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 18142 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 41762 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 12 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 12 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 18078 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 21606 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 39684 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2257 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 34989 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 4452 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 39748 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 81446 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2257 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 34989 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 4452 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 39748 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 81446 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 147657253 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 919546000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 302425250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 999157501 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2368786004 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 279009 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 279009 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1027471259 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1510849774 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 2538321033 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 147657253 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1947017259 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 302425250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2510007275 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 4907107037 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 147657253 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1947017259 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 302425250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2510007275 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 4907107037 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 277801500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 291494000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 569295500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 343786500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 402097500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 745884000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 621588000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 693591500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1315179500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.017836 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.167730 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014979 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.070555 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.020465 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.769231 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.407317 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.241636 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.131052 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017856 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.240385 # mshr miss rate for demand accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.070551 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020457 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.444444 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.408127 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.241767 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.131117 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017836 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.241107 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014979 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.114659 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.034745 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017856 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.240385 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.114709 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034744 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017836 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.241107 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014979 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.114659 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.034745 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64728.613918 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54503.385170 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 68709.316700 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 55036.589787 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 56800.435805 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 25900.700000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 25900.700000 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56978.845481 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 70307.398657 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 64235.554483 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64728.613918 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55782.053372 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 68709.316700 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63332.977559 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 60421.809259 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64728.613918 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55782.053372 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 68709.316700 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63332.977559 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 60421.809259 # average overall mshr miss latency +system.l2c.overall_mshr_miss_rate::cpu2.data 0.114709 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034744 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65421.910944 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54375.613506 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 67930.199910 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 55074.275218 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 56721.086251 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 23250.750000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23250.750000 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56835.449663 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69927.324539 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63963.336181 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65421.910944 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55646.553460 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 67930.199910 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63148.014366 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 60249.822422 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65421.910944 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55646.553460 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 67930.199910 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63148.014366 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 60249.822422 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -668,14 +668,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254914 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254904 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1694870261000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254914 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078432 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078432 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1694870354000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254904 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078431 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078431 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -684,14 +684,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9304463 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9304463 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5314395237 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5314395237 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5323699700 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5323699700 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5323699700 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5323699700 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9303463 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9303463 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5314732731 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5314732731 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5324036194 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5324036194 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5324036194 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5324036194 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -708,19 +708,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53783.023121 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 53783.023121 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 127897.459497 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 127897.459497 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 127590.166567 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 127590.166567 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 127590.166567 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 127590.166567 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 168405 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53777.242775 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 53777.242775 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 127905.581705 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 127905.581705 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 127598.231132 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 127598.231132 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 127598.231132 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 127598.231132 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 168308 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 12345 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 12241 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.641555 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.749530 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -734,14 +734,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 16965 system.iocache.demand_mshr_misses::total 16965 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 16965 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 16965 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5715463 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5715463 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4435167237 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4435167237 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 4440882700 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4440882700 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 4440882700 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4440882700 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5714463 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5714463 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4435520731 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4435520731 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 4441235194 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4441235194 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 4441235194 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4441235194 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.406623 # mshr miss rate for WriteReq accesses @@ -750,14 +750,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 0.406591 system.iocache.demand_mshr_miss_rate::total 0.406591 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.406591 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82832.797101 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82832.797101 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 262498.060902 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 262498.060902 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 261767.326849 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 261767.326849 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 261767.326849 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 261767.326849 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82818.304348 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 82818.304348 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 262518.982659 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 262518.982659 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 261788.104568 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 261788.104568 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 261788.104568 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 261788.104568 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -775,22 +775,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4920992 # DTB read hits +system.cpu0.dtb.read_hits 4920578 # DTB read hits system.cpu0.dtb.read_misses 6099 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations -system.cpu0.dtb.read_accesses 428234 # DTB read accesses -system.cpu0.dtb.write_hits 3511178 # DTB write hits +system.cpu0.dtb.read_accesses 428233 # DTB read accesses +system.cpu0.dtb.write_hits 3510258 # DTB write hits system.cpu0.dtb.write_misses 670 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations system.cpu0.dtb.write_accesses 163777 # DTB write accesses -system.cpu0.dtb.data_hits 8432170 # DTB hits +system.cpu0.dtb.data_hits 8430836 # DTB hits system.cpu0.dtb.data_misses 6769 # DTB misses system.cpu0.dtb.data_acv 210 # DTB access violations -system.cpu0.dtb.data_accesses 592011 # DTB accesses -system.cpu0.itb.fetch_hits 2763046 # ITB hits +system.cpu0.dtb.data_accesses 592010 # DTB accesses +system.cpu0.itb.fetch_hits 2762930 # ITB hits system.cpu0.itb.fetch_misses 3034 # ITB misses system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2766080 # ITB accesses +system.cpu0.itb.fetch_accesses 2765964 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -803,51 +803,51 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928344318 # number of cpu cycles simulated +system.cpu0.numCycles 928345000 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 33880492 # Number of instructions committed -system.cpu0.committedOps 33880492 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 31739536 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 169894 # Number of float alu accesses -system.cpu0.num_func_calls 813170 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4699422 # number of instructions that are conditional controls -system.cpu0.num_int_insts 31739536 # number of integer instructions -system.cpu0.num_fp_insts 169894 # number of float instructions -system.cpu0.num_int_register_reads 44596322 # number of times the integer registers were read -system.cpu0.num_int_register_writes 23159667 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 87728 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 89270 # number of times the floating registers were written -system.cpu0.num_mem_refs 8462332 # number of memory refs -system.cpu0.num_load_insts 4942381 # Number of load instructions -system.cpu0.num_store_insts 3519951 # Number of store instructions -system.cpu0.num_idle_cycles 904625586.132235 # Number of idle cycles -system.cpu0.num_busy_cycles 23718731.867765 # Number of busy cycles +system.cpu0.committedInsts 33879417 # Number of instructions committed +system.cpu0.committedOps 33879417 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 31738664 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 170028 # Number of float alu accesses +system.cpu0.num_func_calls 812853 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4700164 # number of instructions that are conditional controls +system.cpu0.num_int_insts 31738664 # number of integer instructions +system.cpu0.num_fp_insts 170028 # number of float instructions +system.cpu0.num_int_register_reads 44595421 # number of times the integer registers were read +system.cpu0.num_int_register_writes 23158595 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 87794 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 89338 # number of times the floating registers were written +system.cpu0.num_mem_refs 8461010 # number of memory refs +system.cpu0.num_load_insts 4941975 # Number of load instructions +system.cpu0.num_store_insts 3519035 # Number of store instructions +system.cpu0.num_idle_cycles 904626845.998199 # Number of idle cycles +system.cpu0.num_busy_cycles 23718154.001801 # Number of busy cycles system.cpu0.not_idle_fraction 0.025549 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.974451 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6416 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211386 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6418 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211383 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 74805 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105698 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182585 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105697 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182584 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 73438 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73438 49.30% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 148958 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1819501633500 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38918500 0.00% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 365019000 0.02% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22792135500 1.24% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1842697706500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1819507118500 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38781000 0.00% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 365071000 0.02% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22785478000 1.24% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1842696448500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694791 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815828 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694797 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815833 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -883,10 +883,10 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175326 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175325 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -895,21 +895,21 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192241 # number of callpals executed +system.cpu0.kern.callpal::total 192238 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1909 -system.cpu0.kern.mode_good::user 1739 -system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322357 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1907 +system.cpu0.kern.mode_good::user 1738 +system.cpu0.kern.mode_good::idle 169 +system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391309 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29773270000 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2593332500 0.14% 1.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810331099500 98.24% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4177 # number of times the context was actually changed +system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391019 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29794763000 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2592746500 0.14% 1.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1810308934500 98.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -941,58 +941,59 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 110448008 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 784800 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 784578 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 3750 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 3750 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 371852 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 150627 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 133731 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 207 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 846719 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1369630 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 2216349 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27094720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55304714 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 82399434 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 203511688 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 10688 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2136322000 # Layer occupancy (ticks) +system.toL2Bus.throughput 110459996 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 784722 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 784503 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 3749 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 3749 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 371354 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 150558 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 133662 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 204 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 847542 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1368014 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 2215556 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27120896 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55237129 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 82358025 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 203533320 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 11008 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2134008000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1907046997 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1908780020 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2233138904 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2230620167 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1469141 # Throughput (bytes/s) +system.iobus.throughput 1469142 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 2975 # Transaction distribution system.iobus.trans_dist::ReadResp 2975 # Transaction distribution -system.iobus.trans_dist::WriteReq 20646 # Transaction distribution -system.iobus.trans_dist::WriteResp 20646 # Transaction distribution +system.iobus.trans_dist::WriteReq 20645 # Transaction distribution +system.iobus.trans_dist::WriteResp 20645 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2330 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 136 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8372 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8370 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2374 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 13312 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 13310 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 33930 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 33930 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 47242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 47240 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9320 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 544 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4186 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4185 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1548 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 15690 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 15689 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1082792 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1082792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1098482 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1098481 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 2707184 # Total data (bytes) system.iobus.reqLayer0.occupancy 2199000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) @@ -1000,368 +1001,384 @@ system.iobus.reqLayer1.occupancy 102000 # La system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6239000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6237000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 1789000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 153606200 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 153613694 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9562000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9561000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17411500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17409500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 950723 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.190316 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43428114 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 951234 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 45.654501 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 951005 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.190319 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 43429541 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 951516 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 45.642471 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 10399272250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 251.695807 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 99.603495 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 159.891014 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.491593 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.194538 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.312287 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 251.342896 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 99.592582 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 160.254842 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.490904 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.194517 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.312998 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998419 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 33359431 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7828902 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2239781 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43428114 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 33359431 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7828902 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2239781 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43428114 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 33359431 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7828902 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2239781 # number of overall hits -system.cpu0.icache.overall_hits::total 43428114 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 528040 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 126347 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 313191 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 967578 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 528040 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 126347 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 313191 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 967578 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 528040 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 126347 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 313191 # number of overall misses -system.cpu0.icache.overall_misses::total 967578 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1802440753 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4440627379 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6243068132 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1802440753 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4440627379 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6243068132 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1802440753 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4440627379 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6243068132 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 33887471 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7955249 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2552972 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 44395692 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 33887471 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7955249 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2552972 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 44395692 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 33887471 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7955249 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2552972 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 44395692 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015582 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015882 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122677 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.021794 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015582 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015882 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122677 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.021794 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015582 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015882 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122677 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.021794 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14265.797787 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14178.655769 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6452.263416 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14265.797787 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14178.655769 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6452.263416 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14265.797787 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14178.655769 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6452.263416 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4969 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 740 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 199 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.969849 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 740 # average number of cycles each access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 33358489 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7831408 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2239644 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 43429541 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 33358489 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7831408 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2239644 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 43429541 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 33358489 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7831408 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2239644 # number of overall hits +system.cpu0.icache.overall_hits::total 43429541 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 527907 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 126543 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 313729 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 968179 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 527907 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 126543 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 313729 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 968179 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 527907 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 126543 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 313729 # number of overall misses +system.cpu0.icache.overall_misses::total 968179 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1806945253 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4430503289 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6237448542 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1806945253 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4430503289 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6237448542 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1806945253 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4430503289 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6237448542 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 33886396 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 7957951 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 2553373 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 44397720 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 33886396 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 7957951 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 2553373 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 44397720 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 33886396 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7957951 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2553373 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 44397720 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015579 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015901 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122868 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.021807 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015579 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015901 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122868 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.021807 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015579 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015901 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122868 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.021807 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14279.298365 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14122.071243 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6442.453866 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14279.298365 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14122.071243 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6442.453866 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14279.298365 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14122.071243 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6442.453866 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3919 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 159 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.647799 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16174 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 16174 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 16174 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 16174 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 16174 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 16174 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 126347 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 297017 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 423364 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 126347 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 297017 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 423364 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 126347 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 297017 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 423364 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1548840247 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3650495745 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5199335992 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1548840247 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3650495745 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5199335992 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1548840247 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3650495745 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5199335992 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015882 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116342 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009536 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015882 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116342 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009536 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015882 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116342 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009536 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.623054 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12290.527966 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12281.006396 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.623054 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12290.527966 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12281.006396 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.623054 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12290.527966 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12281.006396 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16494 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16494 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16494 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16494 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16494 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16494 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 126543 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 297235 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 423778 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 126543 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 297235 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 423778 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 126543 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 297235 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 423778 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1552948747 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3649949474 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5202898221 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1552948747 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3649949474 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5202898221 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1552948747 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3649949474 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5202898221 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015901 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116409 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009545 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015901 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116409 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009545 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015901 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116409 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009545 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12272.103135 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12279.675926 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12277.414639 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12272.103135 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12279.675926 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12277.414639 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12272.103135 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12279.675926 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12277.414639 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1391697 # number of replacements +system.cpu0.dcache.tags.replacements 1391788 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13286622 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1392209 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.543554 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 13285278 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1392300 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.541965 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 248.161883 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 130.279675 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 133.556253 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.484691 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.254452 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.260852 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 249.411553 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 131.959093 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 130.627166 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.487132 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.257733 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.255131 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 4083341 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1084976 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2395652 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7563969 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3214796 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 832699 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1291573 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5339068 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117279 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19300 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47662 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184241 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126504 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21337 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 51447 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199288 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7298137 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1917675 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3687225 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12903037 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7298137 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1917675 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3687225 # number of overall hits -system.cpu0.dcache.overall_hits::total 12903037 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 721507 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 98995 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 533015 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1353517 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 168939 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 44362 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 596400 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 809701 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9791 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2165 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6803 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18759 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 890446 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 143357 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1129415 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2163218 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 890446 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 143357 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1129415 # number of overall misses -system.cpu0.dcache.overall_misses::total 2163218 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2262107000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9348260996 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11610367996 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1660998759 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18147263609 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 19808262368 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28538250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 102812500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 131350750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 3923105759 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 27495524605 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 31418630364 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 3923105759 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 27495524605 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 31418630364 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4804848 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1183971 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 2928667 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8917486 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3383735 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 877061 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1887973 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6148769 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 127070 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21465 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 54465 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203000 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126504 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21337 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits::cpu0.data 4082373 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1085171 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2396693 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7564237 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3213874 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 832734 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1291048 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5337656 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117262 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19372 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47406 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184040 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126440 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21396 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 51446 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7296247 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1917905 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3687741 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12901893 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7296247 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1917905 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3687741 # number of overall hits +system.cpu0.dcache.overall_hits::total 12901893 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 722135 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 98671 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 532767 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1353573 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 169009 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 44296 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 596502 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 809807 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9742 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2152 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6843 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 18737 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 1 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 891144 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 142967 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1129269 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2163380 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 891144 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 142967 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1129269 # number of overall misses +system.cpu0.dcache.overall_misses::total 2163380 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2255676500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9348290769 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11603967269 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1658917259 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18089996474 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 19748913733 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28489000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 102729249 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 131218249 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 13000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 3914593759 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 27438287243 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 31352881002 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 3914593759 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 27438287243 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 31352881002 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 4804508 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1183842 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 2929460 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8917810 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3382883 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 877030 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 1887550 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6147463 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 127004 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21524 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 54249 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 202777 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126440 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21396 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 51447 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199288 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8188583 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2061032 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 4816640 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15066255 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8188583 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2061032 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 4816640 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15066255 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150162 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083613 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.181999 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.151782 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049927 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050580 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.315894 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.131685 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077052 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100862 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.124906 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092409 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.108742 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069556 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.234482 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.143580 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108742 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069556 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.234482 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.143580 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22850.719733 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17538.457634 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8577.925505 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37441.926852 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30428.007393 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 24463.675317 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13181.639723 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15112.817874 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7002.012367 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27365.986725 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24344.926006 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14524.024099 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27365.986725 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24344.926006 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14524.024099 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 591087 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 822 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 17697 # number of cycles access was blocked +system.cpu0.dcache.StoreCondReq_accesses::total 199283 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 8187391 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 2060872 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 4817010 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 15065273 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8187391 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 2060872 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 4817010 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 15065273 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150304 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083348 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.181865 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.151783 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049960 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050507 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.316019 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.131730 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076706 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.099981 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.126141 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092402 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000019 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.108843 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069372 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.234434 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.143600 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108843 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069372 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.234434 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.143600 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22860.582137 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17546.677570 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 8572.841856 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37450.723745 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30326.799364 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 24387.185753 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13238.382900 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15012.311705 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7003.162139 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27381.100247 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24297.388171 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14492.544538 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27381.100247 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24297.388171 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14492.544538 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 584754 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 852 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 17600 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 33.400407 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 117.428571 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 33.224659 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 121.714286 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 835552 # number of writebacks -system.cpu0.dcache.writebacks::total 835552 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 280898 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 280898 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 507265 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 507265 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1373 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1373 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.writebacks::writebacks 835523 # number of writebacks +system.cpu0.dcache.writebacks::total 835523 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 280793 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 280793 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 507370 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 507370 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1423 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1423 # number of LoadLockedReq MSHR hits system.cpu0.dcache.demand_mshr_hits::cpu2.data 788163 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::total 788163 # number of demand (read+write) MSHR hits system.cpu0.dcache.overall_mshr_hits::cpu2.data 788163 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 788163 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 98995 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 252117 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 351112 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 44362 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 89135 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 133497 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2165 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5430 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7595 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 143357 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 341252 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 484609 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 143357 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 341252 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 484609 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2056105000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4263367239 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6319472239 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1563762241 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2632845749 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4196607990 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24206750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 66163500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90370250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3619867241 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6896212988 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10516080229 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3619867241 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6896212988 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10516080229 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 296519000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 310561500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 607080500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 364164500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 426924000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 791088500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 660683500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 737485500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1398169000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083613 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086086 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039373 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050580 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047212 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021711 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100862 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099697 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037414 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069556 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070849 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032165 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069556 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070849 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032165 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20769.786353 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16910.272766 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17998.451318 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35250.039245 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29537.732081 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31435.972269 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11180.946882 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12184.806630 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11898.650428 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25250.718423 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20208.564310 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21700.133982 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25250.718423 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20208.564310 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21700.133982 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 98671 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 251974 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 350645 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 44296 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 89132 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 133428 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2152 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5420 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7572 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 1 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 142967 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 341106 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 484073 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 142967 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 341106 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 484073 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2050323500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4260770982 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6311094482 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1561811741 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2625415492 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4187227233 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24184000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 65650250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89834250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 11000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3612135241 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6886186474 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10498321715 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3612135241 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6886186474 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10498321715 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 296522000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 310560000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 607082000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 364175500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 426698000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 790873500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 660697500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 737258000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1397955500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083348 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086014 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039320 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050507 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047221 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021705 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099981 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099910 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037342 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069372 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070813 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032132 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069372 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070813 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032132 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20779.393135 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16909.565995 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17998.529801 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35258.527655 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29455.363865 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31381.923082 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11237.918216 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12112.592251 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11864.005547 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25265.517504 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20187.819839 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21687.476300 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25265.517504 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20187.819839 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21687.476300 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1376,22 +1393,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1203387 # DTB read hits +system.cpu1.dtb.read_hits 1203332 # DTB read hits system.cpu1.dtb.read_misses 1366 # DTB read misses system.cpu1.dtb.read_acv 34 # DTB read access violations -system.cpu1.dtb.read_accesses 142939 # DTB read accesses -system.cpu1.dtb.write_hits 898859 # DTB write hits +system.cpu1.dtb.read_accesses 142940 # DTB read accesses +system.cpu1.dtb.write_hits 898898 # DTB write hits system.cpu1.dtb.write_misses 183 # DTB write misses system.cpu1.dtb.write_acv 22 # DTB write access violations system.cpu1.dtb.write_accesses 58529 # DTB write accesses -system.cpu1.dtb.data_hits 2102246 # DTB hits +system.cpu1.dtb.data_hits 2102230 # DTB hits system.cpu1.dtb.data_misses 1549 # DTB misses system.cpu1.dtb.data_acv 56 # DTB access violations -system.cpu1.dtb.data_accesses 201468 # DTB accesses -system.cpu1.itb.fetch_hits 859133 # ITB hits +system.cpu1.dtb.data_accesses 201469 # DTB accesses +system.cpu1.itb.fetch_hits 859402 # ITB hits system.cpu1.itb.fetch_misses 692 # ITB misses system.cpu1.itb.fetch_acv 30 # ITB acv -system.cpu1.itb.fetch_accesses 859825 # ITB accesses +system.cpu1.itb.fetch_accesses 860094 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1404,28 +1421,28 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953620014 # number of cpu cycles simulated +system.cpu1.numCycles 953617285 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7953643 # Number of instructions committed -system.cpu1.committedOps 7953643 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7410219 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45003 # Number of float alu accesses -system.cpu1.num_func_calls 212713 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1020267 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7410219 # number of integer instructions -system.cpu1.num_fp_insts 45003 # number of float instructions -system.cpu1.num_int_register_reads 10384111 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5386902 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24304 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24611 # number of times the floating registers were written -system.cpu1.num_mem_refs 2109479 # number of memory refs -system.cpu1.num_load_insts 1208276 # Number of load instructions -system.cpu1.num_store_insts 901203 # Number of store instructions -system.cpu1.num_idle_cycles 922135498.680812 # Number of idle cycles -system.cpu1.num_busy_cycles 31484515.319188 # Number of busy cycles -system.cpu1.not_idle_fraction 0.033016 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.966984 # Percentage of idle cycles +system.cpu1.committedInsts 7956345 # Number of instructions committed +system.cpu1.committedOps 7956345 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7412681 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 44901 # Number of float alu accesses +system.cpu1.num_func_calls 213028 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1020887 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7412681 # number of integer instructions +system.cpu1.num_fp_insts 44901 # number of float instructions +system.cpu1.num_int_register_reads 10388601 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5388855 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24208 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24605 # number of times the floating registers were written +system.cpu1.num_mem_refs 2109439 # number of memory refs +system.cpu1.num_load_insts 1208206 # Number of load instructions +system.cpu1.num_store_insts 901233 # Number of store instructions +system.cpu1.num_idle_cycles 922131579.439540 # Number of idle cycles +system.cpu1.num_busy_cycles 31485705.560460 # Number of busy cycles +system.cpu1.not_idle_fraction 0.033017 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.966983 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1443,35 +1460,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 9128355 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8449925 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 124319 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7461780 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6520544 # Number of BTB hits +system.cpu2.branchPred.lookups 9131296 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8453261 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 124867 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7606484 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6524985 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 87.385905 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 281902 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 13317 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 85.781880 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 282035 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 13344 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3185589 # DTB read hits -system.cpu2.dtb.read_misses 11798 # DTB read misses -system.cpu2.dtb.read_acv 121 # DTB read access violations -system.cpu2.dtb.read_accesses 217406 # DTB read accesses -system.cpu2.dtb.write_hits 2009886 # DTB write hits -system.cpu2.dtb.write_misses 2608 # DTB write misses -system.cpu2.dtb.write_acv 106 # DTB write access violations -system.cpu2.dtb.write_accesses 82301 # DTB write accesses -system.cpu2.dtb.data_hits 5195475 # DTB hits -system.cpu2.dtb.data_misses 14406 # DTB misses -system.cpu2.dtb.data_acv 227 # DTB access violations -system.cpu2.dtb.data_accesses 299707 # DTB accesses -system.cpu2.itb.fetch_hits 369992 # ITB hits -system.cpu2.itb.fetch_misses 5727 # ITB misses -system.cpu2.itb.fetch_acv 273 # ITB acv -system.cpu2.itb.fetch_accesses 375719 # ITB accesses +system.cpu2.dtb.read_hits 3186348 # DTB read hits +system.cpu2.dtb.read_misses 11810 # DTB read misses +system.cpu2.dtb.read_acv 124 # DTB read access violations +system.cpu2.dtb.read_accesses 217745 # DTB read accesses +system.cpu2.dtb.write_hits 2009701 # DTB write hits +system.cpu2.dtb.write_misses 2606 # DTB write misses +system.cpu2.dtb.write_acv 109 # DTB write access violations +system.cpu2.dtb.write_accesses 82375 # DTB write accesses +system.cpu2.dtb.data_hits 5196049 # DTB hits +system.cpu2.dtb.data_misses 14416 # DTB misses +system.cpu2.dtb.data_acv 233 # DTB access violations +system.cpu2.dtb.data_accesses 300120 # DTB accesses +system.cpu2.itb.fetch_hits 370442 # ITB hits +system.cpu2.itb.fetch_misses 5628 # ITB misses +system.cpu2.itb.fetch_acv 253 # ITB acv +system.cpu2.itb.fetch_accesses 376070 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1484,137 +1501,137 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 31308710 # number of cpu cycles simulated +system.cpu2.numCycles 31313073 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8320877 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 36988805 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 9128355 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6802446 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8846835 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 603748 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9639992 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 11047 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1973 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 63718 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 87241 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 497 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2552980 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 86276 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 27364450 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.351710 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.294118 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8328585 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 37006400 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 9131296 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6807020 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8851345 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 606644 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9641968 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 10046 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1931 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 63228 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 87070 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 340 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2553376 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 86779 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 27379324 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.351618 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.293970 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18517615 67.67% 67.67% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 268760 0.98% 68.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 429758 1.57% 70.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4997201 18.26% 88.48% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 759565 2.78% 91.26% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 164512 0.60% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 190396 0.70% 92.56% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 427414 1.56% 94.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1609229 5.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18527979 67.67% 67.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 269262 0.98% 68.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 428968 1.57% 70.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 5000608 18.26% 88.49% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 759354 2.77% 91.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 165275 0.60% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 190932 0.70% 92.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 427573 1.56% 94.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1609373 5.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 27364450 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.291560 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.181422 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8471005 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9721532 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8236973 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 308822 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 380199 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 165870 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12770 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36596033 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 40157 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 380199 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 8829996 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2781091 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5750095 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 8109315 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1267845 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35455371 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2432 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 230458 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 443882 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 23756988 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 44373855 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 44317462 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 52634 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 21971271 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1785717 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 500561 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 59005 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3706520 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3341982 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2099682 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 368903 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 258103 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32963824 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 619272 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 32519364 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 32677 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2138512 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1074729 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 437003 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 27364450 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.188380 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.575952 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 27379324 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.291613 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.181819 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8475609 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9724872 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 8241247 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 308907 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 382752 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 165606 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12712 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36612854 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 39749 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 382752 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 8834671 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2773280 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5760129 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 8113478 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1269087 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35472103 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2436 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 230799 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 444723 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 23769376 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 44394567 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 44338159 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 52651 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 21967508 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1801868 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 500326 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 58967 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3713170 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3346051 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2099971 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 366369 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 258671 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32979578 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 619087 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32529976 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 34753 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2147129 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1082645 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 436861 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 27379324 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.188122 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.575744 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15094542 55.16% 55.16% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3058510 11.18% 66.34% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1555503 5.68% 72.02% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5825063 21.29% 93.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 904805 3.31% 96.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 480018 1.75% 98.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 285628 1.04% 99.41% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 141467 0.52% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18914 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15104518 55.17% 55.17% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3059496 11.17% 66.34% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1557193 5.69% 72.03% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5827645 21.28% 93.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 904106 3.30% 96.62% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 480512 1.76% 98.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 285612 1.04% 99.41% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 141433 0.52% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18809 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 27364450 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 27379324 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 33388 13.55% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 112327 45.58% 59.13% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 100703 40.87% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 32920 13.41% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.41% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 112185 45.69% 59.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 100449 40.91% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 26855600 82.58% 82.59% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20032 0.06% 82.65% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 26864472 82.58% 82.59% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20045 0.06% 82.65% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.65% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8424 0.03% 82.68% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8419 0.03% 82.68% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.68% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.68% # Type of FU issued system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.68% # Type of FU issued @@ -1640,114 +1657,114 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.68% # Ty system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.68% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.68% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3311528 10.18% 92.87% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2031960 6.25% 99.11% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 288160 0.89% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3313279 10.19% 92.87% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2032055 6.25% 99.11% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 288046 0.89% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 32519364 # Type of FU issued -system.cpu2.iq.rate 1.038668 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 246418 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007578 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 92448223 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 35610975 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 32122316 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 234050 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 114559 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 110669 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 32641435 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 121907 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 186593 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32529976 # Type of FU issued +system.cpu2.iq.rate 1.038862 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 245554 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007549 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 92485827 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 35635212 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 32132884 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 233756 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 114401 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 110529 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32651329 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 121761 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 186414 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 407978 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1104 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4025 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 156833 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 413956 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1112 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 3936 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 157547 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4157 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 26970 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4151 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 27254 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 380199 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2010765 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 204147 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 34852291 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 222063 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3341982 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2099682 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 549953 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 141753 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 1988 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4025 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 63582 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 127875 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 191457 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 32361861 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3205658 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 157503 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 382752 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2003866 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 204399 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 34866454 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 220221 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3346051 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2099971 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 549960 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 142228 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 1969 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 3936 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 63951 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 128015 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 191966 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 32372492 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3206448 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 157484 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1269195 # number of nop insts executed -system.cpu2.iew.exec_refs 5222587 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7560841 # Number of branches executed -system.cpu2.iew.exec_stores 2016929 # Number of stores executed -system.cpu2.iew.exec_rate 1.033638 # Inst execution rate -system.cpu2.iew.wb_sent 32266608 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 32232985 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 18776213 # num instructions producing a value -system.cpu2.iew.wb_consumers 21965918 # num instructions consuming a value +system.cpu2.iew.exec_nop 1267789 # number of nop insts executed +system.cpu2.iew.exec_refs 5223192 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7564928 # Number of branches executed +system.cpu2.iew.exec_stores 2016744 # Number of stores executed +system.cpu2.iew.exec_rate 1.033833 # Inst execution rate +system.cpu2.iew.wb_sent 32276755 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 32243413 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18781769 # num instructions producing a value +system.cpu2.iew.wb_consumers 21976070 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.029521 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.854788 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.029711 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.854646 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2305690 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 182269 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 176747 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26984251 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.204438 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.848007 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2322975 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 182226 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 177336 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26996572 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.203754 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.846865 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16102351 59.67% 59.67% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2321930 8.60% 68.28% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1225737 4.54% 72.82% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5569081 20.64% 93.46% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 502606 1.86% 95.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 185666 0.69% 96.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 176683 0.65% 96.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 180209 0.67% 97.33% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 719988 2.67% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16110852 59.68% 59.68% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2323792 8.61% 68.29% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1227035 4.55% 72.83% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5572191 20.64% 93.47% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 501625 1.86% 95.33% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 185779 0.69% 96.02% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 177561 0.66% 96.67% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 179863 0.67% 97.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 717874 2.66% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26984251 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 32500866 # Number of instructions committed -system.cpu2.commit.committedOps 32500866 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26996572 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32497229 # Number of instructions committed +system.cpu2.commit.committedOps 32497229 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4876853 # Number of memory references committed -system.cpu2.commit.loads 2934004 # Number of loads committed -system.cpu2.commit.membars 63840 # Number of memory barriers committed -system.cpu2.commit.branches 7415854 # Number of branches committed -system.cpu2.commit.fp_insts 109494 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 31057555 # Number of committed integer instructions. -system.cpu2.commit.function_calls 228510 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 719988 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4874519 # Number of memory references committed +system.cpu2.commit.loads 2932095 # Number of loads committed +system.cpu2.commit.membars 63814 # Number of memory barriers committed +system.cpu2.commit.branches 7417113 # Number of branches committed +system.cpu2.commit.fp_insts 109328 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 31054650 # Number of committed integer instructions. +system.cpu2.commit.function_calls 228340 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 717874 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 60996891 # The number of ROB reads -system.cpu2.rob.rob_writes 69992925 # The number of ROB writes -system.cpu2.timesIdled 244953 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3944260 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1746464525 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 31337447 # Number of Instructions Simulated -system.cpu2.committedOps 31337447 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 31337447 # Number of Instructions Simulated -system.cpu2.cpi 0.999083 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.999083 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.000918 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.000918 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 42570866 # number of integer regfile reads -system.cpu2.int_regfile_writes 22648106 # number of integer regfile writes -system.cpu2.fp_regfile_reads 67644 # number of floating regfile reads -system.cpu2.fp_regfile_writes 67951 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5345306 # number of misc regfile reads -system.cpu2.misc_regfile_writes 257045 # number of misc regfile writes +system.cpu2.rob.rob_reads 61024976 # The number of ROB reads +system.cpu2.rob.rob_writes 70022633 # The number of ROB writes +system.cpu2.timesIdled 244840 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3933749 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1746460059 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 31334430 # Number of Instructions Simulated +system.cpu2.committedOps 31334430 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 31334430 # Number of Instructions Simulated +system.cpu2.cpi 0.999318 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.999318 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.000682 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.000682 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42582766 # number of integer regfile reads +system.cpu2.int_regfile_writes 22654603 # number of integer regfile writes +system.cpu2.fp_regfile_reads 67639 # number of floating regfile reads +system.cpu2.fp_regfile_writes 67817 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5347337 # number of misc regfile reads +system.cpu2.misc_regfile_writes 256988 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index d132fd20b..25f2809e1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -105,6 +113,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -169,6 +179,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -188,6 +199,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.checker.dtb +eventq_index=0 exitOnError=false function_trace=false function_trace_start=0 @@ -212,18 +224,21 @@ workload= [system.cpu.checker.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[5] [system.cpu.checker.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -242,18 +257,21 @@ midr=890224640 [system.cpu.checker.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[4] [system.cpu.checker.tracer] type=ExeTracer +eventq_index=0 [system.cpu.dcache] type=BaseCache @@ -261,6 +279,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -283,18 +302,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -303,15 +325,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -320,16 +345,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -338,22 +366,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -362,22 +394,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -386,10 +422,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -398,124 +436,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -524,10 +583,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -536,16 +597,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -554,10 +618,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -568,6 +634,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -590,14 +657,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -616,12 +686,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -632,6 +704,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -654,12 +727,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -669,19 +744,23 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -694,6 +773,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -716,6 +796,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -723,6 +804,7 @@ size=1024 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -734,6 +816,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -760,6 +843,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -771,19 +855,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -793,6 +881,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -802,6 +891,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -830,6 +920,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -839,8 +930,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -852,6 +975,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -867,6 +991,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -881,6 +1007,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -890,6 +1017,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -911,8 +1039,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -921,6 +1051,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -931,6 +1062,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -941,6 +1073,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -951,6 +1084,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -965,6 +1099,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -978,6 +1113,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -995,6 +1131,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -1007,6 +1144,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -1018,6 +1156,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -1028,6 +1167,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -1040,6 +1180,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -1053,6 +1194,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -1063,6 +1205,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -1073,6 +1216,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1083,6 +1227,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1095,6 +1240,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -1109,6 +1255,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -1121,6 +1268,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -1135,6 +1283,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1145,6 +1294,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1155,6 +1305,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1165,6 +1316,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1173,6 +1325,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1180,11 +1333,13 @@ port=3456 [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 8cfdfc3f7..d7c49d42e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.525141 # Number of seconds simulated -sim_ticks 2525141046500 # Number of ticks simulated -final_tick 2525141046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.525132 # Number of seconds simulated +sim_ticks 2525131633500 # Number of ticks simulated +final_tick 2525131633500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50522 # Simulator instruction rate (inst/s) -host_op_rate 65007 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2115457252 # Simulator tick rate (ticks/s) -host_mem_usage 427804 # Number of bytes of host memory used -host_seconds 1193.66 # Real time elapsed on the host -sim_insts 60305756 # Number of instructions simulated -sim_ops 77596741 # Number of ops (including micro ops) simulated +host_inst_rate 41051 # Simulator instruction rate (inst/s) +host_op_rate 52821 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1718892257 # Simulator tick rate (ticks/s) +host_mem_usage 447424 # Number of bytes of host memory used +host_seconds 1469.05 # Real time elapsed on the host +sim_insts 60305678 # Number of instructions simulated +sim_ops 77596684 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 796928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094736 # Number of bytes read from this memory system.physmem.bytes_read::total 129432144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784000 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu.inst 796928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796928 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784384 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800456 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142134 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 42 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12452 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142139 # Number of read requests responded to by this memory system.physmem.num_reads::total 15096843 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59125 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 59131 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47339005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3601548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51257392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498530 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1194417 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2692947 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47339005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4795965 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53950339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 813149 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47339181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3601688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51257583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498688 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1194422 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2693110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498688 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47339181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 315599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4796110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53950692 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15096843 # Number of read requests accepted -system.physmem.writeReqs 813143 # Number of write requests accepted +system.physmem.writeReqs 813149 # Number of write requests accepted system.physmem.readBursts 15096843 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813143 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writeBursts 813149 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 963738752 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 2459200 # Total number of bytes read from write queue system.physmem.bytesWritten 6902144 # Total number of bytes written to DRAM system.physmem.bytesReadSys 129432144 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6800072 # Total written bytes from the system interface side +system.physmem.bytesWrittenSys 6800456 # Total written bytes from the system interface side system.physmem.servicedByWrQ 38425 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 705284 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943582 # Per bank write bursts -system.physmem.perBankRdBursts::1 943145 # Per bank write bursts -system.physmem.perBankRdBursts::2 939291 # Per bank write bursts -system.physmem.perBankRdBursts::3 939307 # Per bank write bursts -system.physmem.perBankRdBursts::4 943115 # Per bank write bursts -system.physmem.perBankRdBursts::5 943141 # Per bank write bursts -system.physmem.perBankRdBursts::6 939138 # Per bank write bursts -system.physmem.perBankRdBursts::7 938546 # Per bank write bursts -system.physmem.perBankRdBursts::8 943996 # Per bank write bursts -system.physmem.perBankRdBursts::9 943390 # Per bank write bursts -system.physmem.perBankRdBursts::10 938426 # Per bank write bursts -system.physmem.perBankRdBursts::11 937974 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 4682 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943580 # Per bank write bursts +system.physmem.perBankRdBursts::1 943152 # Per bank write bursts +system.physmem.perBankRdBursts::2 939288 # Per bank write bursts +system.physmem.perBankRdBursts::3 939310 # Per bank write bursts +system.physmem.perBankRdBursts::4 943113 # Per bank write bursts +system.physmem.perBankRdBursts::5 943139 # Per bank write bursts +system.physmem.perBankRdBursts::6 939134 # Per bank write bursts +system.physmem.perBankRdBursts::7 938551 # Per bank write bursts +system.physmem.perBankRdBursts::8 944000 # Per bank write bursts +system.physmem.perBankRdBursts::9 943392 # Per bank write bursts +system.physmem.perBankRdBursts::10 938425 # Per bank write bursts +system.physmem.perBankRdBursts::11 937973 # Per bank write bursts system.physmem.perBankRdBursts::12 943928 # Per bank write bursts -system.physmem.perBankRdBursts::13 943533 # Per bank write bursts -system.physmem.perBankRdBursts::14 939234 # Per bank write bursts -system.physmem.perBankRdBursts::15 938672 # Per bank write bursts -system.physmem.perBankWrBursts::0 6704 # Per bank write bursts -system.physmem.perBankWrBursts::1 6457 # Per bank write bursts -system.physmem.perBankWrBursts::2 6598 # Per bank write bursts -system.physmem.perBankWrBursts::3 6635 # Per bank write bursts -system.physmem.perBankWrBursts::4 6561 # Per bank write bursts -system.physmem.perBankWrBursts::5 6794 # Per bank write bursts -system.physmem.perBankWrBursts::6 6789 # Per bank write bursts -system.physmem.perBankWrBursts::7 6723 # Per bank write bursts -system.physmem.perBankWrBursts::8 7136 # Per bank write bursts +system.physmem.perBankRdBursts::13 943534 # Per bank write bursts +system.physmem.perBankRdBursts::14 939230 # Per bank write bursts +system.physmem.perBankRdBursts::15 938669 # Per bank write bursts +system.physmem.perBankWrBursts::0 6703 # Per bank write bursts +system.physmem.perBankWrBursts::1 6464 # Per bank write bursts +system.physmem.perBankWrBursts::2 6595 # Per bank write bursts +system.physmem.perBankWrBursts::3 6634 # Per bank write bursts +system.physmem.perBankWrBursts::4 6559 # Per bank write bursts +system.physmem.perBankWrBursts::5 6792 # Per bank write bursts +system.physmem.perBankWrBursts::6 6793 # Per bank write bursts +system.physmem.perBankWrBursts::7 6730 # Per bank write bursts +system.physmem.perBankWrBursts::8 7130 # Per bank write bursts system.physmem.perBankWrBursts::9 6877 # Per bank write bursts -system.physmem.perBankWrBursts::10 6538 # Per bank write bursts -system.physmem.perBankWrBursts::11 6183 # Per bank write bursts -system.physmem.perBankWrBursts::12 7149 # Per bank write bursts -system.physmem.perBankWrBursts::13 6765 # Per bank write bursts -system.physmem.perBankWrBursts::14 7038 # Per bank write bursts -system.physmem.perBankWrBursts::15 6899 # Per bank write bursts +system.physmem.perBankWrBursts::10 6539 # Per bank write bursts +system.physmem.perBankWrBursts::11 6181 # Per bank write bursts +system.physmem.perBankWrBursts::12 7151 # Per bank write bursts +system.physmem.perBankWrBursts::13 6766 # Per bank write bursts +system.physmem.perBankWrBursts::14 7035 # Per bank write bursts +system.physmem.perBankWrBursts::15 6897 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2525139929000 # Total gap between requests +system.physmem.totGap 2525130505500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 36 # Read request sizes (log2) @@ -109,26 +109,26 @@ system.physmem.writePktSize::2 754018 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59125 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1163754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1108384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1064134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3627605 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2618920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2606295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2613037 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 53652 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 58180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 21151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 255 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59131 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1173486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1117689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1073548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3627714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2609756 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2597217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2603662 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 53378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20772 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 238 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -142,29 +142,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4807 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4799 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4794 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 138 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see @@ -174,521 +174,534 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86114 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11271.566528 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1003.490719 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16771.547354 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23576 27.38% 27.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14050 16.32% 43.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2599 3.02% 46.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2090 2.43% 49.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1311 1.52% 50.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1239 1.44% 52.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 869 1.01% 53.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1005 1.17% 54.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 571 0.66% 54.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 602 0.70% 55.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 523 0.61% 56.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 509 0.59% 56.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 284 0.33% 57.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 276 0.32% 57.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 154 0.18% 57.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 642 0.75% 58.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 97 0.11% 58.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 141 0.16% 58.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 78 0.09% 58.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 123 0.14% 58.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 49 0.06% 58.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 518 0.60% 59.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 316 0.37% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 18 0.02% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 102 0.12% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 211 0.25% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 23 0.03% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 55 0.06% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 327 0.38% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 31 0.04% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 124 0.14% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 3 0.00% 61.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 17 0.02% 61.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 9 0.01% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 99 0.11% 61.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 25 0.03% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 90 0.10% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 6 0.01% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 23 0.03% 61.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 2 0.00% 61.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 292 0.34% 61.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 16 0.02% 61.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 98 0.11% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 9 0.01% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 18 0.02% 61.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 8 0.01% 61.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 97 0.11% 62.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 158 0.18% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 373 0.43% 62.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 16 0.02% 62.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 116 0.13% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 99 0.11% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 86134 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11268.950798 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1000.903149 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16775.480046 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23607 27.41% 27.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14081 16.35% 43.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2628 3.05% 46.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2075 2.41% 49.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1317 1.53% 50.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1250 1.45% 52.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 847 0.98% 53.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 989 1.15% 54.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 557 0.65% 54.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 603 0.70% 55.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 514 0.60% 56.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 583 0.68% 56.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 284 0.33% 57.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 264 0.31% 57.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 155 0.18% 57.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 634 0.74% 58.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 90 0.10% 58.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 143 0.17% 58.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 77 0.09% 58.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 121 0.14% 59.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 52 0.06% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 516 0.60% 59.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 33 0.04% 59.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 269 0.31% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 22 0.03% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 94 0.11% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 142 0.16% 60.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 22 0.03% 60.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 57 0.07% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 390 0.45% 60.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 32 0.04% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 120 0.14% 61.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 5 0.01% 61.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 22 0.03% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 8 0.01% 61.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 107 0.12% 61.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 24 0.03% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 86 0.10% 61.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 7 0.01% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 27 0.03% 61.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 4 0.00% 61.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 358 0.42% 61.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 18 0.02% 61.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 154 0.18% 62.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 9 0.01% 62.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 15 0.02% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 8 0.01% 62.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 31 0.04% 62.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 11 0.01% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 39 0.05% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 15 0.02% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 368 0.43% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 15 0.02% 62.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 165 0.19% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 92 0.11% 63.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 19 0.02% 63.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 2 0.00% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 13 0.02% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 426 0.49% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 8 0.01% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 6 0.01% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 28 0.03% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 19 0.02% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 3 0.00% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 89 0.10% 63.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 63.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 10 0.01% 63.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 2 0.00% 63.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 131 0.15% 63.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 1 0.00% 63.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 15 0.02% 63.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 11 0.01% 64.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 413 0.48% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 1 0.00% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 2 0.00% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 87 0.10% 64.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 4 0.00% 64.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 12 0.01% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 5 0.01% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 145 0.17% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 1 0.00% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 24 0.03% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 8 0.01% 64.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 363 0.42% 65.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 3 0.00% 65.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 9 0.01% 65.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 10 0.01% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 1 0.00% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 98 0.11% 65.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 3 0.00% 65.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 9 0.01% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 82 0.10% 65.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 13 0.02% 65.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8135 1 0.00% 65.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 508 0.59% 66.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 76 0.09% 66.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 89 0.10% 66.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 74 0.09% 66.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 350 0.41% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9351 1 0.00% 66.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 17 0.02% 66.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9543 1 0.00% 66.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9607 3 0.00% 66.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9671 1 0.00% 66.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 138 0.16% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9799 1 0.00% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9863 1 0.00% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 79 0.09% 67.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 6 0.01% 67.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 402 0.47% 67.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 84 0.10% 67.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10567 1 0.00% 67.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 76 0.09% 67.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10951 3 0.00% 67.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 15 0.02% 67.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 1 0.00% 67.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 416 0.48% 68.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11399 1 0.00% 68.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 13 0.02% 68.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11719 2 0.00% 68.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 84 0.10% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 95 0.11% 63.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 2 0.00% 63.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 16 0.02% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 379 0.44% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 10 0.01% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 5 0.01% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 88 0.10% 63.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 21 0.02% 63.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 3 0.00% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 146 0.17% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 2 0.00% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 8 0.01% 64.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 2 0.00% 64.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 64 0.07% 64.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 1 0.00% 64.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 13 0.02% 64.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 11 0.01% 64.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 283 0.33% 64.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 1 0.00% 64.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 2 0.00% 64.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 88 0.10% 64.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 4 0.00% 64.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 11 0.01% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 6 0.01% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 153 0.18% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 1 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 78 0.09% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 9 0.01% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 368 0.43% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 2 0.00% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 11 0.01% 65.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 136 0.16% 65.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 9 0.01% 65.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 1 0.00% 65.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 88 0.10% 65.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 2 0.00% 65.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 9 0.01% 65.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 84 0.10% 65.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 11 0.01% 65.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8135 1 0.00% 65.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 389 0.45% 66.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 2 0.00% 66.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 79 0.09% 66.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 78 0.09% 66.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 130 0.15% 66.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9095 1 0.00% 66.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 355 0.41% 66.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9351 2 0.00% 66.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 73 0.08% 67.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9543 1 0.00% 67.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9607 4 0.00% 67.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9671 1 0.00% 67.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 140 0.16% 67.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9799 2 0.00% 67.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9927 1 0.00% 67.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 79 0.09% 67.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 4 0.00% 67.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 272 0.32% 67.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 15 0.02% 67.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10567 1 0.00% 67.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10631 1 0.00% 67.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 132 0.15% 67.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10951 3 0.00% 67.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 75 0.09% 67.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 373 0.43% 68.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11399 1 0.00% 68.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 86 0.10% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11655 1 0.00% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11719 2 0.00% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 77 0.09% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11911 2 0.00% 68.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 98 0.11% 68.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12167 5 0.01% 68.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 335 0.39% 69.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12423 3 0.00% 69.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 141 0.16% 69.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 79 0.09% 69.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 86 0.10% 69.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13127 1 0.00% 69.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 4 0.00% 69.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 286 0.33% 69.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 76 0.09% 69.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 74 0.09% 69.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13895 1 0.00% 69.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 91 0.11% 70.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 3 0.00% 70.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 284 0.33% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14471 2 0.00% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 139 0.16% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14727 4 0.00% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 146 0.17% 70.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14919 2 0.00% 70.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 13 0.02% 70.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15175 1 0.00% 70.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15303 2 0.00% 70.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 405 0.47% 71.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 17 0.02% 71.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 80 0.09% 71.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16071 1 0.00% 71.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 74 0.09% 71.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16263 11 0.01% 71.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 645 0.75% 72.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 72 0.08% 72.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16711 2 0.00% 72.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16839 1 0.00% 72.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 78 0.09% 72.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17095 1 0.00% 72.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 28 0.03% 72.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17287 5 0.01% 72.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 407 0.47% 72.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17543 2 0.00% 72.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 18 0.02% 72.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17735 2 0.00% 72.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17792-17799 3 0.00% 72.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17856-17863 1 0.00% 72.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 147 0.17% 73.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-17991 1 0.00% 73.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18112-18119 2 0.00% 73.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 144 0.17% 73.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 4 0.00% 73.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 279 0.32% 73.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 89 0.10% 73.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18880-18887 2 0.00% 73.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 73 0.08% 73.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19136-19143 1 0.00% 73.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 77 0.09% 73.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 5 0.01% 73.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 263 0.31% 74.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 82 0.10% 74.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 79 0.09% 74.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20096-20103 1 0.00% 74.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 140 0.16% 74.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20288-20295 1 0.00% 74.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 3 0.00% 74.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 343 0.40% 74.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20672-20679 1 0.00% 74.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 96 0.11% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20864-20871 2 0.00% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 82 0.10% 75.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21120-21127 1 0.00% 75.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 144 0.17% 68.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12103 1 0.00% 68.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12167 4 0.00% 68.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 340 0.39% 69.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12359 1 0.00% 69.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 2 0.00% 69.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 26 0.03% 69.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 18 0.02% 69.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12935 1 0.00% 69.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 2 0.00% 69.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 146 0.17% 69.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13127 1 0.00% 69.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 2 0.00% 69.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 339 0.39% 69.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 74 0.09% 69.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 78 0.09% 69.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13895 1 0.00% 69.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13959 1 0.00% 69.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 87 0.10% 70.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14151 2 0.00% 70.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 4 0.00% 70.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 340 0.39% 70.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 79 0.09% 70.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14727 4 0.00% 70.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 86 0.10% 70.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14919 2 0.00% 70.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 13 0.02% 70.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15303 1 0.00% 70.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 405 0.47% 71.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 83 0.10% 71.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 89 0.10% 71.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16071 1 0.00% 71.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 86 0.10% 71.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 12 0.01% 71.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 642 0.75% 72.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 86 0.10% 72.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16711 2 0.00% 72.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16775 1 0.00% 72.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 84 0.10% 72.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17095 1 0.00% 72.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 92 0.11% 72.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 4 0.00% 72.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17351 1 0.00% 72.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 410 0.48% 72.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17479 2 0.00% 72.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17543 3 0.00% 72.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 15 0.02% 72.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17735 1 0.00% 72.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17799 5 0.01% 72.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17863 1 0.00% 72.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 86 0.10% 73.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-17991 1 0.00% 73.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18048-18055 1 0.00% 73.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18112-18119 2 0.00% 73.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 83 0.10% 73.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 3 0.00% 73.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 331 0.38% 73.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 89 0.10% 73.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18880-18887 2 0.00% 73.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 83 0.10% 73.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19136-19143 1 0.00% 73.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 74 0.09% 73.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 3 0.00% 73.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 326 0.38% 74.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19591 3 0.00% 74.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19648-19655 1 0.00% 74.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 138 0.16% 74.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19840-19847 1 0.00% 74.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 15 0.02% 74.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 23 0.03% 74.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20288-20295 1 0.00% 74.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 3 0.00% 74.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 336 0.39% 74.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20608-20615 1 0.00% 74.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20672-20679 2 0.00% 74.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 143 0.17% 75.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20864-20871 3 0.00% 75.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 73 0.08% 75.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 14 0.02% 75.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 4 0.00% 75.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 401 0.47% 75.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21568-21575 1 0.00% 75.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21632-21639 1 0.00% 75.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 17 0.02% 75.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 2 0.00% 75.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 77 0.09% 75.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22144-22151 1 0.00% 75.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 84 0.10% 75.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 3 0.00% 75.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22464-22471 1 0.00% 75.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 400 0.46% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22656-22663 1 0.00% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22720-22727 2 0.00% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 80 0.09% 76.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22912-22919 1 0.00% 76.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22976-22983 2 0.00% 76.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 136 0.16% 76.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23104-23111 1 0.00% 76.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 21 0.02% 76.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23360-23367 3 0.00% 76.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23424-23431 2 0.00% 76.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 351 0.41% 76.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23687 2 0.00% 76.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 73 0.08% 77.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24007 2 0.00% 77.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 83 0.10% 77.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 83 0.10% 77.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24448-24455 4 0.00% 77.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 387 0.45% 77.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 78 0.09% 77.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24960-24967 1 0.00% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25024-25031 1 0.00% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 89 0.10% 77.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25280-25287 1 0.00% 77.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 72 0.08% 77.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 4 0.00% 77.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 349 0.41% 78.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 19 0.02% 78.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25984-25991 3 0.00% 78.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 133 0.15% 78.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26304-26311 2 0.00% 78.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 78 0.09% 78.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 1 0.00% 78.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 401 0.47% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26752-26759 2 0.00% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 82 0.10% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27008-27015 2 0.00% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 77 0.09% 79.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27200-27207 1 0.00% 79.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 15 0.02% 79.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 403 0.47% 79.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 11 0.01% 79.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27968-27975 2 0.00% 79.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28096-28103 1 0.00% 79.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 83 0.10% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 89 0.10% 75.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 3 0.00% 75.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21440-21447 1 0.00% 75.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 367 0.43% 75.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21568-21575 1 0.00% 75.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21632-21639 1 0.00% 75.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 76 0.09% 75.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21824-21831 1 0.00% 75.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 5 0.01% 75.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 129 0.15% 75.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22144-22151 1 0.00% 75.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 14 0.02% 75.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22336-22343 1 0.00% 75.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 3 0.00% 75.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22464-22471 2 0.00% 75.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 268 0.31% 76.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22720-22727 2 0.00% 76.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 78 0.09% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22912-22919 1 0.00% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22976-22983 2 0.00% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 143 0.17% 76.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23104-23111 1 0.00% 76.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23168-23175 1 0.00% 76.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 77 0.09% 76.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23360-23367 3 0.00% 76.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23424-23431 2 0.00% 76.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 350 0.41% 76.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23680-23687 1 0.00% 76.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 126 0.15% 77.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24007 2 0.00% 77.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 74 0.09% 77.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24192-24199 2 0.00% 77.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 82 0.10% 77.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 3 0.00% 77.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 270 0.31% 77.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 79 0.09% 77.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25024-25031 1 0.00% 77.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 77 0.09% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25216-25223 2 0.00% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25280-25287 1 0.00% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 133 0.15% 77.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 2 0.00% 77.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 355 0.41% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 72 0.08% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25984-25991 2 0.00% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 138 0.16% 78.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26311 2 0.00% 78.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 79 0.09% 78.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 2 0.00% 78.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 269 0.31% 79.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26752-26759 1 0.00% 79.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 14 0.02% 79.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27008-27015 4 0.00% 79.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27072-27079 1 0.00% 79.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 130 0.15% 79.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27200-27207 1 0.00% 79.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 74 0.09% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 367 0.43% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 85 0.10% 79.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-27975 2 0.00% 79.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28032-28039 2 0.00% 79.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28096-28103 1 0.00% 79.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 75 0.09% 79.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::28288-28295 2 0.00% 79.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28352-28359 1 0.00% 79.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 97 0.11% 80.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28480-28487 2 0.00% 80.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 2 0.00% 80.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 341 0.40% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28736-28743 1 0.00% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28800-28807 1 0.00% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28864-28871 2 0.00% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 143 0.17% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29056-29063 1 0.00% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 77 0.09% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29248-29255 2 0.00% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 85 0.10% 80.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29511 3 0.00% 80.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29575 2 0.00% 80.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 268 0.31% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 76 0.09% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 74 0.09% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30336-30343 2 0.00% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 92 0.11% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 4 0.00% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 271 0.31% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30848-30855 2 0.00% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30912-30919 1 0.00% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 145 0.17% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31111 2 0.00% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 148 0.17% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31296-31303 1 0.00% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31367 1 0.00% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 19 0.02% 82.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31552-31559 2 0.00% 82.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31680-31687 4 0.00% 82.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 398 0.46% 82.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31936-31943 1 0.00% 82.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 18 0.02% 82.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 78 0.09% 82.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 83 0.10% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 2 0.00% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 143 0.17% 80.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28480-28487 2 0.00% 80.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 4 0.00% 80.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 337 0.39% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28743 1 0.00% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28864-28871 2 0.00% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 26 0.03% 80.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 17 0.02% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29248-29255 2 0.00% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 139 0.16% 80.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 3 0.00% 80.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 4 0.00% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 329 0.38% 81.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 2 0.00% 81.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 70 0.08% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 79 0.09% 81.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 92 0.11% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 4 0.00% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 327 0.38% 81.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30848-30855 4 0.00% 81.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30919 2 0.00% 81.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 84 0.10% 81.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 89 0.10% 82.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31367 1 0.00% 82.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31424-31431 1 0.00% 82.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 19 0.02% 82.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 2 0.00% 82.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31680-31687 1 0.00% 82.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 406 0.47% 82.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 83 0.10% 82.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32064-32071 1 0.00% 82.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 2 0.00% 82.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 82 0.10% 82.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32448-32455 2 0.00% 82.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 93 0.11% 82.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::32576-32583 1 0.00% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 642 0.75% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 645 0.75% 83.56% # Bytes accessed per row activation system.physmem.bytesPerActivate::32832-32839 2 0.00% 83.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 73 0.08% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33216-33223 2 0.00% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 78 0.09% 83.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 4 0.00% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 27 0.03% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33607 2 0.00% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33735 1 0.00% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 406 0.47% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33920-33927 1 0.00% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 16 0.02% 84.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 144 0.17% 84.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 147 0.17% 84.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 269 0.31% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 87 0.10% 85.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 72 0.08% 85.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35456-35463 2 0.00% 85.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 77 0.09% 85.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35712-35719 1 0.00% 85.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 268 0.31% 85.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 81 0.09% 85.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 77 0.09% 85.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36480-36487 1 0.00% 85.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 144 0.17% 85.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36736-36743 2 0.00% 85.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 338 0.39% 86.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36992-36999 1 0.00% 86.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 91 0.11% 86.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 83 0.10% 86.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32896-32903 1 0.00% 83.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 83 0.10% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33088-33095 1 0.00% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33216-33223 2 0.00% 83.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 82 0.10% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 4 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33472-33479 1 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 95 0.11% 83.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33671 1 0.00% 83.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 411 0.48% 84.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 13 0.02% 84.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34112-34119 1 0.00% 84.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 83 0.10% 84.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 86 0.10% 84.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34688-34695 1 0.00% 84.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 328 0.38% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 86 0.10% 85.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35200-35207 1 0.00% 85.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 76 0.09% 85.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35456-35463 3 0.00% 85.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 72 0.08% 85.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35712-35719 1 0.00% 85.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 328 0.38% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 138 0.16% 85.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 1 0.00% 85.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 15 0.02% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36480-36487 3 0.00% 85.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 25 0.03% 85.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 337 0.39% 86.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36992-36999 2 0.00% 86.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 141 0.16% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37184-37191 1 0.00% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 73 0.08% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 3 0.00% 86.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::37568-37575 1 0.00% 86.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 11 0.01% 86.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 404 0.47% 86.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38016-38023 2 0.00% 86.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 15 0.02% 86.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38272-38279 1 0.00% 86.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38336-38343 1 0.00% 86.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 77 0.09% 87.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 1 0.00% 87.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 84 0.10% 87.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 401 0.47% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39040-39047 2 0.00% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39104-39111 1 0.00% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 77 0.09% 87.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 130 0.15% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 15 0.02% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 348 0.40% 88.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40064-40071 3 0.00% 88.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 71 0.08% 88.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 86 0.10% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 78 0.09% 88.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 387 0.45% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41152-41159 2 0.00% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 78 0.09% 89.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41344-41351 2 0.00% 89.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 83 0.10% 89.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 72 0.08% 89.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41856-41863 3 0.00% 89.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 347 0.40% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 18 0.02% 89.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 133 0.15% 89.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42624-42631 3 0.00% 89.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 79 0.09% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42816-42823 1 0.00% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 399 0.46% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 82 0.10% 90.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 76 0.09% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 2 0.00% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 20 0.02% 90.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 403 0.47% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 10 0.01% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 82 0.10% 86.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 365 0.42% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 2 0.00% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 75 0.09% 87.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38336-38343 1 0.00% 87.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 129 0.15% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38464-38471 1 0.00% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 2 0.00% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 14 0.02% 87.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 267 0.31% 87.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39104-39111 1 0.00% 87.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 77 0.09% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39296-39303 1 0.00% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 140 0.16% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 2 0.00% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 70 0.08% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 351 0.41% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40064-40071 1 0.00% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 129 0.15% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 76 0.09% 88.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 2 0.00% 88.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 80 0.09% 88.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40832-40839 2 0.00% 88.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 269 0.31% 88.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 2 0.00% 88.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 77 0.09% 89.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 75 0.09% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 2 0.00% 89.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 131 0.15% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41856-41863 3 0.00% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 349 0.41% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 70 0.08% 89.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 140 0.16% 89.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 2 0.00% 89.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 77 0.09% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 267 0.31% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43136-43143 3 0.00% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 14 0.02% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 127 0.15% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 1 0.00% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 80 0.09% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 364 0.42% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 1 0.00% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 83 0.10% 91.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 81 0.09% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44679 3 0.00% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 96 0.11% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 341 0.40% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 143 0.17% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 82 0.10% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 5 0.01% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 84 0.10% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45888-45895 1 0.00% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 261 0.30% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 73 0.08% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 68 0.08% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 91 0.11% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 272 0.32% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 142 0.16% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 144 0.17% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 25 0.03% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 395 0.46% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 16 0.02% 93.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 76 0.09% 93.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 71 0.08% 94.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 72 0.08% 94.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5013 5.82% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 73 0.08% 91.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 144 0.17% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44864-44871 2 0.00% 91.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 337 0.39% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 24 0.03% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 3 0.00% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 16 0.02% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 3 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 144 0.17% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 2 0.00% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 327 0.38% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 69 0.08% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 79 0.09% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 89 0.10% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 1 0.00% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 334 0.39% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 78 0.09% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 88 0.10% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 24 0.03% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 398 0.46% 93.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 83 0.10% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 77 0.09% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 72 0.08% 94.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 83 0.10% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 3 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5012 5.82% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation @@ -714,15 +727,15 @@ system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86114 # Bytes accessed per row activation -system.physmem.totQLat 365610387500 # Total ticks spent queuing -system.physmem.totMemAccLat 458189280000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::total 86134 # Bytes accessed per row activation +system.physmem.totQLat 365453646000 # Total ticks spent queuing +system.physmem.totMemAccLat 458164497250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 75292090000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17286802500 # Total ticks spent accessing banks -system.physmem.avgQLat 24279.47 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1147.98 # Average bank access latency per DRAM burst +system.physmem.totBankLat 17418761250 # Total ticks spent accessing banks +system.physmem.avgQLat 24269.06 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1156.75 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30427.45 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30425.81 # Average memory access latency per DRAM burst system.physmem.avgRdBW 381.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.26 # Average system read bandwidth in MiByte/s @@ -732,14 +745,14 @@ system.physmem.busUtil 3.00 # Da system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.84 # Average write queue length when enqueuing -system.physmem.readRowHits 14986740 # Number of row buffer hits during reads -system.physmem.writeRowHits 93410 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.83 # Average write queue length when enqueuing +system.physmem.readRowHits 14986798 # Number of row buffer hits during reads +system.physmem.writeRowHits 93332 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.60 # Row buffer hit rate for writes -system.physmem.avgGap 158714.15 # Average gap between requests +system.physmem.writeRowHitRate 86.53 # Row buffer hit rate for writes +system.physmem.avgGap 158713.50 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.73 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 1.72 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -752,50 +765,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54899945 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149440 # Transaction distribution -system.membus.trans_dist::ReadResp 16149440 # Transaction distribution +system.membus.throughput 54900302 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149434 # Transaction distribution +system.membus.trans_dist::ReadResp 16149434 # Transaction distribution system.membus.trans_dist::WriteReq 763332 # Transaction distribution system.membus.trans_dist::WriteResp 763332 # Transaction distribution -system.membus.trans_dist::Writeback 59125 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution +system.membus.trans_dist::Writeback 59131 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4679 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution -system.membus.trans_dist::ReadExReq 131442 # Transaction distribution -system.membus.trans_dist::ReadExResp 131442 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4682 # Transaction distribution +system.membus.trans_dist::ReadExReq 131448 # Transaction distribution +system.membus.trans_dist::ReadExResp 131448 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885779 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272485 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885801 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272507 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34156901 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34156923 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694552 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092441 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694936 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092825 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138630105 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138630105 # Total data (bytes) +system.membus.tot_pkt_size::total 138630489 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138630489 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486773500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486873500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3686000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3694000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17363455000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17363465500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4733701508 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4733669250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33738367951 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33737503451 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -803,7 +816,7 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48285606 # Throughput (bytes/s) +system.iobus.throughput 48285786 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution system.iobus.trans_dist::WriteReq 8157 # Transaction distribution @@ -913,22 +926,22 @@ system.iobus.reqLayer25.occupancy 14942208000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40921194049 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40921719549 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu.branchPred.lookups 14384905 # Number of BP lookups -system.cpu.branchPred.condPredicted 11471084 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 703956 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9467627 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7657685 # Number of BTB hits +system.cpu.branchPred.lookups 14384927 # Number of BP lookups +system.cpu.branchPred.condPredicted 11469310 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704177 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9471049 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7661571 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.882834 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1397242 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72494 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.894640 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398227 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72610 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14986852 # DTB read hits -system.cpu.checker.dtb.read_misses 7306 # DTB read misses -system.cpu.checker.dtb.write_hits 11227410 # DTB write hits +system.cpu.checker.dtb.read_hits 14986834 # DTB read hits +system.cpu.checker.dtb.read_misses 7307 # DTB read misses +system.cpu.checker.dtb.write_hits 11227416 # DTB write hits system.cpu.checker.dtb.write_misses 2191 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -939,13 +952,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 179 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994158 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229601 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994141 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229607 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26214262 # DTB hits -system.cpu.checker.dtb.misses 9497 # DTB misses -system.cpu.checker.dtb.accesses 26223759 # DTB accesses -system.cpu.checker.itb.inst_hits 61479743 # ITB inst hits +system.cpu.checker.dtb.hits 26214250 # DTB hits +system.cpu.checker.dtb.misses 9498 # DTB misses +system.cpu.checker.dtb.accesses 26223748 # DTB accesses +system.cpu.checker.itb.inst_hits 61479663 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -962,36 +975,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61484214 # ITB inst accesses -system.cpu.checker.itb.hits 61479743 # DTB hits +system.cpu.checker.itb.inst_accesses 61484134 # ITB inst accesses +system.cpu.checker.itb.hits 61479663 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61484214 # DTB accesses -system.cpu.checker.numCycles 77882535 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61484134 # DTB accesses +system.cpu.checker.numCycles 77882476 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51179212 # DTB read hits -system.cpu.dtb.read_misses 64531 # DTB read misses -system.cpu.dtb.write_hits 11698539 # DTB write hits -system.cpu.dtb.write_misses 15837 # DTB write misses +system.cpu.dtb.read_hits 51182106 # DTB read hits +system.cpu.dtb.read_misses 64421 # DTB read misses +system.cpu.dtb.write_hits 11699698 # DTB write hits +system.cpu.dtb.write_misses 15824 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6568 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2411 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6560 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2374 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 404 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1396 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51243743 # DTB read accesses -system.cpu.dtb.write_accesses 11714376 # DTB write accesses +system.cpu.dtb.perms_faults 1314 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51246527 # DTB read accesses +system.cpu.dtb.write_accesses 11715522 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62877751 # DTB hits -system.cpu.dtb.misses 80368 # DTB misses -system.cpu.dtb.accesses 62958119 # DTB accesses -system.cpu.itb.inst_hits 11513998 # ITB inst hits -system.cpu.itb.inst_misses 11344 # ITB inst misses +system.cpu.dtb.hits 62881804 # DTB hits +system.cpu.dtb.misses 80245 # DTB misses +system.cpu.dtb.accesses 62962049 # DTB accesses +system.cpu.itb.inst_hits 11522583 # ITB inst hits +system.cpu.itb.inst_misses 11276 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -1000,148 +1013,148 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4962 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4956 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2968 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3012 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11525342 # ITB inst accesses -system.cpu.itb.hits 11513998 # DTB hits -system.cpu.itb.misses 11344 # DTB misses -system.cpu.itb.accesses 11525342 # DTB accesses -system.cpu.numCycles 474882944 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11533859 # ITB inst accesses +system.cpu.itb.hits 11522583 # DTB hits +system.cpu.itb.misses 11276 # DTB misses +system.cpu.itb.accesses 11533859 # DTB accesses +system.cpu.numCycles 474898657 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29745457 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90266235 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14384905 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9054927 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20140969 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4652912 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 123687 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96003967 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87891 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2685420 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11510536 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 707949 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5425 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151996950 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.740543 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.094686 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29752889 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90273347 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14384927 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9059798 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20146705 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4653497 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122274 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96010555 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 88482 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2690288 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 446 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11519088 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 708911 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5337 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 152021113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.740504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.094585 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131871277 86.76% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1302073 0.86% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1710886 1.13% 88.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2295409 1.51% 90.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2102442 1.38% 91.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1107607 0.73% 92.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2555872 1.68% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 743971 0.49% 94.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8307413 5.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131890125 86.76% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1304050 0.86% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1713045 1.13% 88.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2295968 1.51% 90.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2102742 1.38% 91.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107769 0.73% 92.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2555355 1.68% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 744146 0.49% 94.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8307913 5.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151996950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 152021113 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.030291 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.190081 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31502209 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 98125273 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18366247 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 966197 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3037024 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1956644 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171990 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107262918 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568386 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3037024 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33252800 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39466554 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52672825 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17523888 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6043859 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102275198 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20557 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4063584 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106014240 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 466907038 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432047963 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10635 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78387438 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27626801 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830029 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736499 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12184256 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19715159 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13304037 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1977063 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2478152 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95106473 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1982467 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122897190 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 166901 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18919534 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47250176 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 500160 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151996950 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.808550 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.527901 # Number of insts issued each cycle +system.cpu.fetch.rate 0.190090 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31508438 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 98138099 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18373215 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 963804 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3037557 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1957081 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171807 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107274658 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 567663 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3037557 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33258738 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39476292 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52673596 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17529662 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6045268 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102285915 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004806 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4066044 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 644 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106018919 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 466959682 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432092489 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10446 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78387358 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27631560 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830464 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736820 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12181979 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19715902 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13307123 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1978281 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2470778 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95109477 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1982753 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122906700 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167286 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18927569 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47237054 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 500451 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 152021113 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.808484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.527863 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108284402 71.24% 71.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13439431 8.84% 80.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6944257 4.57% 84.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5857722 3.85% 88.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12372410 8.14% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2808060 1.85% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1695891 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 467423 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127354 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108300469 71.24% 71.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13447891 8.85% 80.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6945073 4.57% 84.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5857007 3.85% 88.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12370739 8.14% 96.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2808869 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1695394 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 467391 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128280 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151996950 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 152021113 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62444 0.71% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8371933 94.63% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412257 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61937 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 6 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8370529 94.64% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412377 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57615534 46.88% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93100 0.08% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57620183 46.88% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93128 0.08% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued @@ -1154,397 +1167,397 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 33 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 25 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 20 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2115 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 25 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 20 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52504661 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12318028 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52507579 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319960 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122897190 # Type of FU issued -system.cpu.iq.rate 0.258795 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8846641 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071984 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 406861293 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116024937 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85463742 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23592 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12620 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10347 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131367569 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12596 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623590 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122906700 # Type of FU issued +system.cpu.iq.rate 0.258806 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8844849 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071964 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406902990 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116036304 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85470220 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23531 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12536 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10316 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131375312 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12571 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623425 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4061151 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6344 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30249 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1572309 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4061911 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6363 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30197 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1575391 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107765 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 681284 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107753 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 681273 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3037024 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30702730 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434457 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97310809 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 203906 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19715159 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13304037 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1409970 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113496 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3538 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30249 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 349429 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269322 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 618751 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120821579 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51866256 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2075611 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3037557 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30701555 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434229 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97313991 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205819 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19715902 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13307123 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410230 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30197 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350181 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268988 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619169 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120829627 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51869148 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2077073 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221869 # number of nop insts executed -system.cpu.iew.exec_refs 64076774 # number of memory reference insts executed -system.cpu.iew.exec_branches 11475076 # Number of branches executed -system.cpu.iew.exec_stores 12210518 # Number of stores executed -system.cpu.iew.exec_rate 0.254424 # Inst execution rate -system.cpu.iew.wb_sent 119883669 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85474089 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47026181 # num instructions producing a value -system.cpu.iew.wb_consumers 87876552 # num instructions consuming a value +system.cpu.iew.exec_nop 221761 # number of nop insts executed +system.cpu.iew.exec_refs 64080783 # number of memory reference insts executed +system.cpu.iew.exec_branches 11475005 # Number of branches executed +system.cpu.iew.exec_stores 12211635 # Number of stores executed +system.cpu.iew.exec_rate 0.254432 # Inst execution rate +system.cpu.iew.wb_sent 119890224 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85480536 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47031033 # num instructions producing a value +system.cpu.iew.wb_consumers 87879900 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179990 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535139 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179997 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535174 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18658160 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 534513 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 148959926 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.521933 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.510472 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18664214 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482302 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 534875 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 148983556 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521850 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.510275 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121529130 81.59% 81.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13302723 8.93% 90.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3899356 2.62% 93.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2115942 1.42% 94.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1939571 1.30% 95.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 978607 0.66% 96.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1596110 1.07% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 718014 0.48% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2880473 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121547303 81.58% 81.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13306218 8.93% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3902162 2.62% 93.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2119528 1.42% 94.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1937783 1.30% 95.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 976082 0.66% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1595601 1.07% 97.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718241 0.48% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2880638 1.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 148959926 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60456137 # Number of instructions committed -system.cpu.commit.committedOps 77747122 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 148983556 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60456059 # Number of instructions committed +system.cpu.commit.committedOps 77747065 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385736 # Number of memory references committed -system.cpu.commit.loads 15654008 # Number of loads committed -system.cpu.commit.membars 403573 # Number of memory barriers committed -system.cpu.commit.branches 9961077 # Number of branches committed +system.cpu.commit.refs 27385723 # Number of memory references committed +system.cpu.commit.loads 15653991 # Number of loads committed +system.cpu.commit.membars 403571 # Number of memory barriers committed +system.cpu.commit.branches 9961071 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68852562 # Number of committed integer instructions. -system.cpu.commit.function_calls 991208 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2880473 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68852511 # Number of committed integer instructions. +system.cpu.commit.function_calls 991207 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2880638 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 240636318 # The number of ROB reads -system.cpu.rob.rob_writes 195934369 # The number of ROB writes -system.cpu.timesIdled 1776906 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322885994 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575316115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60305756 # Number of Instructions Simulated -system.cpu.committedOps 77596741 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60305756 # Number of Instructions Simulated -system.cpu.cpi 7.874587 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.874587 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126991 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126991 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 547208472 # number of integer regfile reads -system.cpu.int_regfile_writes 87526189 # number of integer regfile writes -system.cpu.fp_regfile_reads 8624 # number of floating regfile reads -system.cpu.fp_regfile_writes 3008 # number of floating regfile writes -system.cpu.misc_regfile_reads 30165107 # number of misc regfile reads +system.cpu.rob.rob_reads 240665808 # The number of ROB reads +system.cpu.rob.rob_writes 195946920 # The number of ROB writes +system.cpu.timesIdled 1776652 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322877544 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575281578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60305678 # Number of Instructions Simulated +system.cpu.committedOps 77596684 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60305678 # Number of Instructions Simulated +system.cpu.cpi 7.874858 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.874858 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126986 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126986 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 547244885 # number of integer regfile reads +system.cpu.int_regfile_writes 87532646 # number of integer regfile writes +system.cpu.fp_regfile_reads 8511 # number of floating regfile reads +system.cpu.fp_regfile_writes 2972 # number of floating regfile writes +system.cpu.misc_regfile_reads 30145050 # number of misc regfile reads system.cpu.misc_regfile_writes 831837 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58889875 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658094 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658093 # Transaction distribution +system.cpu.toL2Bus.throughput 58898886 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658060 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658059 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607699 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2967 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246142 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246142 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961671 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796233 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31091 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128199 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7917194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62737088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85515993 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148510785 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148510785 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 194456 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128799181 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 607897 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2956 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2969 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246128 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246128 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961789 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796637 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30578 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 127052 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7916056 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62740736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85535129 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41644 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 210260 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148527769 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148527769 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 199672 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3129078659 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474440753 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474541718 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2550199081 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2550360089 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20321978 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20171491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74655295 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74593037 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980741 # number of replacements -system.cpu.icache.tags.tagsinuse 511.579116 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10449649 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981253 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.649291 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 980798 # number of replacements +system.cpu.icache.tags.tagsinuse 511.579102 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10457750 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981310 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.656928 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 6918450250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.579116 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.579102 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10449649 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10449649 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10449649 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10449649 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10449649 # number of overall hits -system.cpu.icache.overall_hits::total 10449649 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060761 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060761 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060761 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060761 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060761 # number of overall misses -system.cpu.icache.overall_misses::total 1060761 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14273214680 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14273214680 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14273214680 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14273214680 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14273214680 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14273214680 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11510410 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11510410 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11510410 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11510410 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11510410 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11510410 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092157 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092157 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092157 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092157 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092157 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092157 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13455.636736 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13455.636736 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13455.636736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13455.636736 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6677 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 10457750 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10457750 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10457750 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10457750 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10457750 # number of overall hits +system.cpu.icache.overall_hits::total 10457750 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1061214 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1061214 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1061214 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1061214 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1061214 # number of overall misses +system.cpu.icache.overall_misses::total 1061214 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14272429649 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14272429649 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14272429649 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14272429649 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14272429649 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14272429649 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11518964 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11518964 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11518964 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11518964 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11518964 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11518964 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092128 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092128 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092128 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092128 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092128 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092128 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13449.153186 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13449.153186 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13449.153186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13449.153186 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5990 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 323 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 322 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.671827 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.602484 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79476 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79476 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79476 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79476 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79476 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79476 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981285 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 981285 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 981285 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 981285 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981285 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981285 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587356987 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11587356987 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587356987 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11587356987 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587356987 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11587356987 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79868 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79868 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79868 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79868 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79868 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79868 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981346 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 981346 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 981346 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 981346 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 981346 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 981346 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11584683024 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11584683024 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11584683024 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11584683024 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11584683024 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11584683024 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8658250 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8658250 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8658250 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 8658250 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085252 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085252 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085252 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11808.350262 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11808.350262 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085194 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.085194 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.085194 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11804.891469 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11804.891469 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11804.891469 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11804.891469 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11804.891469 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11804.891469 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 64371 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51366.694603 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1888244 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129769 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.550810 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2490009951000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36925.668640 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 27.934134 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.003945 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8175.587712 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6237.500172 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563441 # Average percentage of cache occupancy +system.cpu.l2cache.tags.tagsinuse 51362.964424 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1886397 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129765 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.537025 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2489982729000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36926.272860 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 27.936805 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000373 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8173.687928 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6235.066458 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.563450 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000426 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124750 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.095177 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.783794 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53605 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10777 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 967799 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387031 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1419212 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607699 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607699 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 40 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 40 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112944 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112944 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 53605 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10777 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 967799 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 499975 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1532156 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 53605 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10777 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 967799 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 499975 # number of overall hits -system.cpu.l2cache.overall_hits::total 1532156 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12350 # number of ReadReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124721 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.095140 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.783737 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52523 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10409 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 967861 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387146 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1417939 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607897 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607897 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 112916 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112916 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 52523 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10409 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 967861 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 500062 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1530855 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 52523 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10409 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 967861 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 500062 # number of overall hits +system.cpu.l2cache.overall_hits::total 1530855 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 42 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12345 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 10721 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23115 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23110 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2915 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2915 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133198 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133198 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12350 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143919 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156313 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12350 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143919 # number of overall misses -system.cpu.l2cache.overall_misses::total 156313 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3352500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 233000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 906466500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 812441248 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1722493248 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 465980 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 465980 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10117185994 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10117185994 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3352500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 233000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 906466500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10929627242 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11839679242 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3352500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 233000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 906466500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10929627242 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11839679242 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53646 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10780 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 980149 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 397752 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1442327 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607699 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607699 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2955 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2955 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246142 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246142 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53646 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10780 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 980149 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 643894 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1688469 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53646 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10780 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 980149 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 643894 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1688469 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000764 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000278 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012600 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026954 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016026 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986464 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986464 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541143 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541143 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000764 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000278 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012600 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223513 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092577 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000764 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000278 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012600 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223513 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092577 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 81768.292683 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77666.666667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73398.097166 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75780.360787 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74518.418689 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 159.855918 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 159.855918 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75955.990285 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75955.990285 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81768.292683 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77666.666667 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73398.097166 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75942.907066 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75743.407407 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81768.292683 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77666.666667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73398.097166 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75942.907066 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75743.407407 # average overall miss latency +system.cpu.l2cache.ReadExReq_misses::cpu.data 133212 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133212 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 42 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12345 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143933 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156322 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 42 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 12345 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143933 # number of overall misses +system.cpu.l2cache.overall_misses::total 156322 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3605250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 158000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 903018500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 812779249 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1719560999 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 510978 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 510978 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10116159486 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10116159486 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3605250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 158000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 903018500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10928938735 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11835720485 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3605250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 158000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 903018500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10928938735 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11835720485 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52565 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10411 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 980206 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 397867 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1441049 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607897 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607897 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2956 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2956 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246128 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246128 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52565 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10411 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 980206 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 643995 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1687177 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52565 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10411 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 980206 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 643995 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1687177 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000799 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000192 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012594 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026946 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016037 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986130 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986130 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.230769 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541231 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541231 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000799 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000192 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012594 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223500 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.092653 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000799 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000192 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012594 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223500 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.092653 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85839.285714 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73148.521669 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75811.887790 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74407.658979 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 175.292624 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 175.292624 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75940.301820 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75940.301820 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85839.285714 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73148.521669 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75930.736766 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75713.722221 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85839.285714 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73148.521669 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75930.736766 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75713.722221 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1553,109 +1566,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59125 # number of writebacks -system.cpu.l2cache.writebacks::total 59125 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 59131 # number of writebacks +system.cpu.l2cache.writebacks::total 59131 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12339 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10656 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23039 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 42 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12334 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10655 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23033 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2915 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2915 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133198 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133198 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12339 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143854 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156237 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12339 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143854 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156237 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2846500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 196000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 750549750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 675500748 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1429092998 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133212 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133212 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 42 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12334 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143867 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156245 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 42 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12334 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143867 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156245 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3085750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 133500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 747187750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 675762749 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1426169749 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29153914 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29153914 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8456317006 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8456317006 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2846500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 196000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 750549750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9131817754 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9885410004 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2846500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 196000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 750549750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9131817754 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9885410004 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8455143514 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8455143514 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3085750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 133500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 747187750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9130906263 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9881313263 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3085750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 133500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 747187750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9130906263 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9881313263 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6187249 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166934965500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941152749 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17442637817 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17442637817 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166935059000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941246249 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17442653817 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17442653817 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6187249 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184377603317 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184383790566 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026791 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015973 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986464 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986464 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541143 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541143 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092532 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092532 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.437394 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63391.586712 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62029.298060 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184377712817 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184383900066 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026780 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015983 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986130 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986130 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541231 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541231 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223398 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092607 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223398 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092607 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60579.515972 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63422.125669 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61918.540746 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342710 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342710 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63486.816664 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63486.816664 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63471.335270 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63471.335270 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60579.515972 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63467.690735 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63242.428641 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60579.515972 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63467.690735 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63242.428641 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1665,161 +1678,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643382 # number of replacements +system.cpu.dcache.tags.replacements 643483 # number of replacements system.cpu.dcache.tags.tagsinuse 511.993331 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21503755 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 643894 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.396421 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 21507621 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 643995 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.397186 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 42430250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13751955 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13751955 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258296 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258296 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242828 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242828 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21010251 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21010251 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21010251 # number of overall hits -system.cpu.dcache.overall_hits::total 21010251 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737736 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737736 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963735 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963735 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13555 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13555 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3701471 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3701471 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3701471 # number of overall misses -system.cpu.dcache.overall_misses::total 3701471 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10012711310 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10012711310 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 141368125836 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 141368125836 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185715250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 185715250 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 151380837146 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 151380837146 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 151380837146 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 151380837146 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14489691 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14489691 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222031 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222031 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256383 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256383 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24711722 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24711722 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24711722 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24711722 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050915 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050915 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289936 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289936 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052870 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052870 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149786 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149786 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149786 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149786 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13572.214600 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13572.214600 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47699.313817 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47699.313817 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13700.866839 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13700.866839 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40897.480257 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40897.480257 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33174 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 27500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2643 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.551646 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 96.491228 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13755484 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13755484 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258628 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258628 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242811 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242811 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247593 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247593 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21014112 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21014112 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21014112 # number of overall hits +system.cpu.dcache.overall_hits::total 21014112 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737297 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737297 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963410 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2963410 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13576 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13576 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3700707 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3700707 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3700707 # number of overall misses +system.cpu.dcache.overall_misses::total 3700707 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10005137822 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10005137822 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 141347559382 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 141347559382 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185728250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 185728250 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 206503 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 206503 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 151352697204 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 151352697204 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 151352697204 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 151352697204 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14492781 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14492781 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222038 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222038 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256387 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256387 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247606 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247606 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24714819 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24714819 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24714819 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24714819 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050873 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050873 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289904 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289904 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052951 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052951 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000053 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000053 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149736 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149736 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149736 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149736 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13570.023779 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13570.023779 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47697.604915 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47697.604915 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13680.631261 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13680.631261 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15884.846154 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15884.846154 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40898.319484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40898.319484 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32831 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 27415 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2635 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.459583 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 98.261649 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607699 # number of writebacks -system.cpu.dcache.writebacks::total 607699 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 352116 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 352116 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714717 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714717 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3066833 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3066833 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3066833 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3066833 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385620 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385620 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249018 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249018 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4970319128 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4970319128 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11601864538 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11601864538 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572183666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16572183666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572183666 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16572183666 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328180000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328180000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841518267 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841518267 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169698267 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169698267 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026613 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026613 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024361 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024361 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047628 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047628 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.writebacks::writebacks 607897 # number of writebacks +system.cpu.dcache.writebacks::total 607897 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351582 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351582 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714405 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714405 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1345 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1345 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065987 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065987 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065987 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065987 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385715 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385715 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249005 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249005 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12231 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12231 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634720 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634720 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634720 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634720 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4972029375 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4972029375 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11600619783 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11600619783 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 180497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 180497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572649158 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16572649158 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572649158 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16572649158 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328280000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328280000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841536765 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841536765 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169816765 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169816765 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024360 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024360 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047705 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047705 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000053 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000053 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12889.163238 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12889.163238 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46590.465500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46590.465500 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11957.333552 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.333552 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12890.422657 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12890.422657 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46587.898970 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46587.898970 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11937.821928 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11937.821928 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13884.384615 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13884.384615 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1841,16 +1854,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1499087755049 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1499087755049 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1499067779549 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1499067779549 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83033 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 7ff8826e3..98e6f2256 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -105,6 +113,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -169,6 +179,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -184,6 +195,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -206,18 +218,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -226,15 +241,18 @@ port=system.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 +eventq_index=0 [system.cpu0.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu0.fuPool.FUList0.opList [system.cpu0.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -243,16 +261,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 [system.cpu0.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu0.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -261,22 +282,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 [system.cpu0.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu0.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu0.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -285,22 +310,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 [system.cpu0.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu0.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu0.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -309,10 +338,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList4.opList [system.cpu0.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -321,124 +352,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 [system.cpu0.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu0.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu0.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu0.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu0.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu0.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu0.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu0.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu0.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu0.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu0.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu0.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu0.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu0.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu0.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu0.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu0.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu0.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -447,10 +499,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList6.opList [system.cpu0.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -459,16 +513,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 [system.cpu0.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu0.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -477,10 +534,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu0.fuPool.FUList8.opList [system.cpu0.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -491,6 +550,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -513,14 +573,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -539,18 +602,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=DerivO3CPU @@ -581,6 +647,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -645,6 +713,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -660,6 +729,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -682,18 +752,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[7] @@ -702,15 +775,18 @@ port=system.toL2Bus.slave[7] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 +eventq_index=0 [system.cpu1.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu1.fuPool.FUList0.opList [system.cpu1.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -719,16 +795,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 [system.cpu1.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu1.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -737,22 +816,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 [system.cpu1.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu1.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu1.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -761,22 +844,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 [system.cpu1.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu1.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu1.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -785,10 +872,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList4.opList [system.cpu1.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -797,124 +886,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 [system.cpu1.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu1.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu1.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu1.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu1.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu1.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu1.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu1.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu1.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu1.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu1.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu1.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu1.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu1.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu1.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu1.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu1.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu1.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -923,10 +1033,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList6.opList [system.cpu1.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -935,16 +1047,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 [system.cpu1.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu1.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -953,10 +1068,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu1.fuPool.FUList8.opList [system.cpu1.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -967,6 +1084,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -989,14 +1107,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -1015,31 +1136,37 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[6] [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -1052,6 +1179,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -1074,6 +1202,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -1083,6 +1212,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -1105,6 +1235,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -1112,6 +1243,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1123,6 +1255,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1149,6 +1282,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -1160,19 +1294,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -1182,6 +1320,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -1191,6 +1330,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -1219,6 +1359,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -1228,8 +1369,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -1241,6 +1414,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -1256,6 +1430,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -1270,6 +1446,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -1279,6 +1456,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -1300,8 +1478,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -1310,6 +1490,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -1320,6 +1501,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -1330,6 +1512,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -1340,6 +1523,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -1354,6 +1538,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -1367,6 +1552,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -1384,6 +1570,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -1396,6 +1583,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -1407,6 +1595,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -1417,6 +1606,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -1429,6 +1619,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -1442,6 +1633,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -1452,6 +1644,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -1462,6 +1655,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1472,6 +1666,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1484,6 +1679,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -1498,6 +1694,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -1510,6 +1707,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -1524,6 +1722,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1534,6 +1733,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1544,6 +1744,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1554,6 +1755,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1562,6 +1764,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1570,6 +1773,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1579,11 +1783,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 22f0dd0ff..fbdae72ae 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.104766 # Number of seconds simulated -sim_ticks 1104765949000 # Number of ticks simulated -final_tick 1104765949000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1104766159000 # Number of ticks simulated +final_tick 1104766159000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62642 # Simulator instruction rate (inst/s) -host_op_rate 80640 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1123477436 # Simulator tick rate (ticks/s) -host_mem_usage 430892 # Number of bytes of host memory used -host_seconds 983.35 # Real time elapsed on the host -sim_insts 61598253 # Number of instructions simulated -sim_ops 79296895 # Number of ops (including micro ops) simulated +host_inst_rate 49697 # Simulator instruction rate (inst/s) +host_op_rate 63978 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 891289209 # Simulator tick rate (ticks/s) +host_mem_usage 450492 # Number of bytes of host memory used +host_seconds 1239.51 # Real time elapsed on the host +sim_insts 61600257 # Number of instructions simulated +sim_ops 79301805 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 408192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4366132 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 406848 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5251248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 409280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4366772 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 405824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5250416 # Number of bytes read from this memory system.physmem.bytes_read::total 59192932 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 408192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 406848 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 815040 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4268480 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu0.inst 409280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 405824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4267520 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7295824 # Number of bytes written to this memory +system.physmem.bytes_written::total 7294864 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6378 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68293 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6357 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82077 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6395 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68303 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6341 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82064 # Number of read requests responded to by this memory system.physmem.num_reads::total 6257980 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66695 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 66680 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823531 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44134945 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823516 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44134936 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 753 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 369483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3952088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 368266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4753267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53579613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 369483 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 368266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 737749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3863696 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 370468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3952666 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 367339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4752513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53579603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 370468 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 367339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 737807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3862827 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 15388 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 2724870 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6603954 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3863696 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44134945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 6603084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3862827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44134936 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 753 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 369483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3967476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 368266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7478138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60183567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 370468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3968054 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 367339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7477383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60182687 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 6257980 # Number of read requests accepted -system.physmem.writeReqs 823531 # Number of write requests accepted +system.physmem.writeReqs 823516 # Number of write requests accepted system.physmem.readBursts 6257980 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 823531 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 398200448 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2310272 # Total number of bytes read from write queue -system.physmem.bytesWritten 7402624 # Total number of bytes written to DRAM +system.physmem.writeBursts 823516 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 398158784 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2351936 # Total number of bytes read from write queue +system.physmem.bytesWritten 7399168 # Total number of bytes written to DRAM system.physmem.bytesReadSys 59192932 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7295824 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 36098 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 707850 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12605 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 391110 # Per bank write bursts -system.physmem.perBankRdBursts::1 390863 # Per bank write bursts -system.physmem.perBankRdBursts::2 386866 # Per bank write bursts -system.physmem.perBankRdBursts::3 386878 # Per bank write bursts -system.physmem.perBankRdBursts::4 391778 # Per bank write bursts -system.physmem.perBankRdBursts::5 391417 # Per bank write bursts -system.physmem.perBankRdBursts::6 386925 # Per bank write bursts -system.physmem.perBankRdBursts::7 386783 # Per bank write bursts -system.physmem.perBankRdBursts::8 391442 # Per bank write bursts -system.physmem.perBankRdBursts::9 391216 # Per bank write bursts -system.physmem.perBankRdBursts::10 386574 # Per bank write bursts -system.physmem.perBankRdBursts::11 385570 # Per bank write bursts -system.physmem.perBankRdBursts::12 390981 # Per bank write bursts -system.physmem.perBankRdBursts::13 390596 # Per bank write bursts -system.physmem.perBankRdBursts::14 386700 # Per bank write bursts -system.physmem.perBankRdBursts::15 386183 # Per bank write bursts -system.physmem.perBankWrBursts::0 7188 # Per bank write bursts -system.physmem.perBankWrBursts::1 7193 # Per bank write bursts -system.physmem.perBankWrBursts::2 7297 # Per bank write bursts -system.physmem.perBankWrBursts::3 7231 # Per bank write bursts -system.physmem.perBankWrBursts::4 7835 # Per bank write bursts -system.physmem.perBankWrBursts::5 7450 # Per bank write bursts -system.physmem.perBankWrBursts::6 7370 # Per bank write bursts -system.physmem.perBankWrBursts::7 7176 # Per bank write bursts -system.physmem.perBankWrBursts::8 7508 # Per bank write bursts -system.physmem.perBankWrBursts::9 7517 # Per bank write bursts -system.physmem.perBankWrBursts::10 6849 # Per bank write bursts -system.physmem.perBankWrBursts::11 6596 # Per bank write bursts -system.physmem.perBankWrBursts::12 7160 # Per bank write bursts -system.physmem.perBankWrBursts::13 6824 # Per bank write bursts -system.physmem.perBankWrBursts::14 7287 # Per bank write bursts -system.physmem.perBankWrBursts::15 7185 # Per bank write bursts +system.physmem.bytesWrittenSys 7294864 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 36749 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 707898 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 12570 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 391105 # Per bank write bursts +system.physmem.perBankRdBursts::1 391040 # Per bank write bursts +system.physmem.perBankRdBursts::2 387008 # Per bank write bursts +system.physmem.perBankRdBursts::3 386856 # Per bank write bursts +system.physmem.perBankRdBursts::4 391768 # Per bank write bursts +system.physmem.perBankRdBursts::5 391357 # Per bank write bursts +system.physmem.perBankRdBursts::6 387221 # Per bank write bursts +system.physmem.perBankRdBursts::7 386642 # Per bank write bursts +system.physmem.perBankRdBursts::8 391438 # Per bank write bursts +system.physmem.perBankRdBursts::9 391160 # Per bank write bursts +system.physmem.perBankRdBursts::10 385906 # Per bank write bursts +system.physmem.perBankRdBursts::11 385319 # Per bank write bursts +system.physmem.perBankRdBursts::12 390977 # Per bank write bursts +system.physmem.perBankRdBursts::13 390642 # Per bank write bursts +system.physmem.perBankRdBursts::14 386557 # Per bank write bursts +system.physmem.perBankRdBursts::15 386235 # Per bank write bursts +system.physmem.perBankWrBursts::0 7173 # Per bank write bursts +system.physmem.perBankWrBursts::1 7194 # Per bank write bursts +system.physmem.perBankWrBursts::2 7298 # Per bank write bursts +system.physmem.perBankWrBursts::3 7217 # Per bank write bursts +system.physmem.perBankWrBursts::4 7815 # Per bank write bursts +system.physmem.perBankWrBursts::5 7451 # Per bank write bursts +system.physmem.perBankWrBursts::6 7359 # Per bank write bursts +system.physmem.perBankWrBursts::7 7185 # Per bank write bursts +system.physmem.perBankWrBursts::8 7499 # Per bank write bursts +system.physmem.perBankWrBursts::9 7507 # Per bank write bursts +system.physmem.perBankWrBursts::10 6838 # Per bank write bursts +system.physmem.perBankWrBursts::11 6616 # Per bank write bursts +system.physmem.perBankWrBursts::12 7156 # Per bank write bursts +system.physmem.perBankWrBursts::13 6834 # Per bank write bursts +system.physmem.perBankWrBursts::14 7291 # Per bank write bursts +system.physmem.perBankWrBursts::15 7179 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1104764856500 # Total gap between requests +system.physmem.totGap 1104765054500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 105 # Read request sizes (log2) @@ -126,29 +126,29 @@ system.physmem.writePktSize::2 756836 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66695 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 548369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 494073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 445478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1468713 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1058783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1047686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1043195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25365 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 25416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 9815 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 9549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 9391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 14 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66680 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 551365 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 495534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 447275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1468617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1056766 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1046048 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1041328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 24902 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24744 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 9495 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8808 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -159,547 +159,563 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 71125 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 5702.673097 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 368.783347 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 12967.835637 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 25909 36.43% 36.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14850 20.88% 57.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 3162 4.45% 61.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2234 3.14% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1545 2.17% 67.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1302 1.83% 68.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 996 1.40% 70.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1191 1.67% 71.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 629 0.88% 72.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 663 0.93% 73.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 567 0.80% 74.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 536 0.75% 75.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 288 0.40% 75.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 263 0.37% 76.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 175 0.25% 76.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 373 0.52% 76.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 125 0.18% 77.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 132 0.19% 77.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 91 0.13% 77.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 197 0.28% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 57 0.08% 77.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 541 0.76% 78.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 41 0.06% 78.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 225 0.32% 78.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 27 0.04% 78.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 110 0.15% 79.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 22 0.03% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 111 0.16% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 16 0.02% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 61 0.09% 79.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 13 0.02% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 267 0.38% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 16 0.02% 79.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 40 0.06% 79.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 17 0.02% 79.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 50 0.07% 79.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 11 0.02% 79.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 22 0.03% 79.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 7 0.01% 79.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 43 0.06% 80.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 4 0.01% 80.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 15 0.02% 80.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 8 0.01% 80.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 32 0.04% 80.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 7 0.01% 80.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 30 0.04% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 5 0.01% 80.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 157 0.22% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 6 0.01% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 17 0.02% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 2 0.00% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 36 0.05% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 9 0.01% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 17 0.02% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 7 0.01% 80.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 88 0.12% 80.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 7 0.01% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 27 0.04% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 8 0.01% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 39 0.05% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 6 0.01% 80.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 18 0.03% 80.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 4 0.01% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 181 0.25% 81.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 9 0.01% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 12 0.02% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 12 0.02% 81.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 102 0.14% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 17 0.02% 81.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 25 0.04% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 7 0.01% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 11 0.02% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 5 0.01% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 3 0.00% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 10 0.01% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 19 0.03% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 2 0.00% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 6 0.01% 81.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 5 0.01% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 161 0.23% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 6 0.01% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 13 0.02% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 9 0.01% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 14 0.02% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 3 0.00% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 16 0.02% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 3 0.00% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 18 0.03% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 5 0.01% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 8 0.01% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 5 0.01% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 150 0.21% 81.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 2 0.00% 81.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 12 0.02% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 13 0.02% 82.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 95 0.13% 82.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 7 0.01% 82.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 6 0.01% 82.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 23 0.03% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 70891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 5720.862056 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 370.371771 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 12983.455583 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 25780 36.37% 36.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14831 20.92% 57.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 3170 4.47% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2175 3.07% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1493 2.11% 66.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1297 1.83% 68.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 1053 1.49% 70.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1149 1.62% 71.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 657 0.93% 72.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 651 0.92% 73.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 556 0.78% 74.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 523 0.74% 75.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 304 0.43% 75.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 266 0.38% 76.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 142 0.20% 76.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 425 0.60% 76.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 119 0.17% 77.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 139 0.20% 77.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 90 0.13% 77.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 153 0.22% 77.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 51 0.07% 77.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 550 0.78% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 38 0.05% 78.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 222 0.31% 78.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 29 0.04% 78.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 108 0.15% 78.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 16 0.02% 78.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 111 0.16% 79.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 28 0.04% 79.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 57 0.08% 79.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 19 0.03% 79.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 237 0.33% 79.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 12 0.02% 79.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 45 0.06% 79.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 10 0.01% 79.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 54 0.08% 79.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 16 0.02% 79.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 29 0.04% 79.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 2 0.00% 79.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 27 0.04% 79.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 2 0.00% 79.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 17 0.02% 79.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 5 0.01% 79.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 28 0.04% 79.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 7 0.01% 79.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 22 0.03% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 5 0.01% 80.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 178 0.25% 80.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 2 0.00% 80.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 13 0.02% 80.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 3 0.00% 80.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 91 0.13% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 6 0.01% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 20 0.03% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 6 0.01% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 46 0.06% 80.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 11 0.02% 80.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 27 0.04% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 5 0.01% 80.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 37 0.05% 80.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 12 0.02% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 18 0.03% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 12 0.02% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 201 0.28% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 6 0.01% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 17 0.02% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 8 0.01% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 92 0.13% 81.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 19 0.03% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 20 0.03% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 13 0.02% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 19 0.03% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 2 0.00% 81.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 6 0.01% 81.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 10 0.01% 81.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 20 0.03% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 4 0.01% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 13 0.02% 81.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 3 0.00% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 93 0.13% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 4 0.01% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 15 0.02% 81.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 8 0.01% 81.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 84 0.12% 81.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 5 0.01% 81.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 9 0.01% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 5 0.01% 81.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 19 0.03% 81.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 2 0.00% 81.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 7 0.01% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 2 0.00% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 138 0.19% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 4 0.01% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 11 0.02% 81.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 12 0.02% 81.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 85 0.12% 82.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 8 0.01% 82.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 6 0.01% 82.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 5 0.01% 82.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 96 0.14% 82.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::6464-6471 4 0.01% 82.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 11 0.02% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 3 0.00% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 112 0.16% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 9 0.01% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 20 0.03% 82.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 8 0.01% 82.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 28 0.04% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 5 0.01% 82.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 4 0.01% 82.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 2 0.00% 82.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 94 0.13% 82.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 6 0.01% 82.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 10 0.01% 82.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 92 0.13% 82.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 3 0.00% 82.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 10 0.01% 82.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 3 0.00% 82.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 20 0.03% 82.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 2 0.00% 82.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 2 0.00% 82.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 4 0.01% 82.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 30 0.04% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 6 0.01% 82.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 8 0.01% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8135 1 0.00% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 249 0.35% 83.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 1 0.00% 83.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 31 0.04% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8647 1 0.00% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 16 0.02% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 3 0.00% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8903 1 0.00% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 75 0.11% 83.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 1 0.00% 83.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 93 0.13% 83.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9415 1 0.00% 83.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 20 0.03% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9607 1 0.00% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 102 0.14% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9863 1 0.00% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9927 1 0.00% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 14 0.02% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 3 0.00% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 94 0.13% 83.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10375 1 0.00% 83.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 94 0.13% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 15 0.02% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10823 1 0.00% 84.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10887 1 0.00% 84.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 6 0.01% 84.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11079 2 0.00% 84.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 1 0.00% 84.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 147 0.21% 84.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11335 3 0.00% 84.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 15 0.02% 84.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11591 1 0.00% 84.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 1 0.00% 84.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11840-11847 1 0.00% 84.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 79 0.11% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12103 1 0.00% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12231 1 0.00% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 162 0.23% 84.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 20 0.03% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12679 1 0.00% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12743 1 0.00% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 68 0.10% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12871 1 0.00% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12935 1 0.00% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 20 0.03% 84.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 148 0.21% 85.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13447 1 0.00% 85.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13511 1 0.00% 85.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 19 0.03% 85.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13703 1 0.00% 85.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 18 0.03% 85.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 11 0.02% 85.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 228 0.32% 85.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 27 0.04% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 14 0.02% 85.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14919 1 0.00% 85.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14983 1 0.00% 85.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 73 0.10% 85.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15175 2 0.00% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 1 0.00% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 145 0.20% 85.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 10 0.01% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15687 1 0.00% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15751 1 0.00% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 20 0.03% 85.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16071 1 0.00% 85.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 17 0.02% 85.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16263 1 0.00% 85.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16327 1 0.00% 85.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 273 0.38% 86.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16455 1 0.00% 86.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16519 1 0.00% 86.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 20 0.03% 86.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16711 1 0.00% 86.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 21 0.03% 86.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 13 0.02% 86.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17287 1 0.00% 86.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17351 1 0.00% 86.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 156 0.22% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17472-17479 2 0.00% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17543 1 0.00% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 80 0.11% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17792-17799 1 0.00% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17856-17863 1 0.00% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 14 0.02% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 31 0.04% 86.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 2 0.00% 86.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 1 0.00% 86.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18368-18375 1 0.00% 86.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 219 0.31% 87.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18496-18503 1 0.00% 87.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 6 0.01% 87.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18752-18759 1 0.00% 87.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 15 0.02% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19008-19015 1 0.00% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19072-19079 4 0.01% 87.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 13 0.02% 87.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19264-19271 1 0.00% 87.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 140 0.20% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19591 1 0.00% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19648-19655 1 0.00% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 17 0.02% 87.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19840-19847 2 0.00% 87.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 68 0.10% 87.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20032-20039 1 0.00% 87.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20096-20103 1 0.00% 87.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 17 0.02% 87.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 2 0.00% 87.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20416-20423 1 0.00% 87.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 157 0.22% 87.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 82 0.12% 87.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 4 0.01% 87.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 14 0.02% 87.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 2 0.00% 87.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21440-21447 2 0.00% 87.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 145 0.20% 88.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21632-21639 1 0.00% 88.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21696-21703 1 0.00% 88.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 4 0.01% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21824-21831 1 0.00% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 1 0.00% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 14 0.02% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22144-22151 2 0.00% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 92 0.13% 88.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 1 0.00% 88.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22464-22471 2 0.00% 88.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 85 0.12% 88.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 14 0.02% 88.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22848-22855 1 0.00% 88.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 102 0.14% 88.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23104-23111 2 0.00% 88.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23232-23239 1 0.00% 88.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 21 0.03% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23488-23495 1 0.00% 88.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 91 0.13% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23616-23623 1 0.00% 88.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23744-23751 4 0.01% 88.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 75 0.11% 88.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23872-23879 2 0.00% 88.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24007 1 0.00% 88.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 21 0.03% 88.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 31 0.04% 88.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24448-24455 1 0.00% 88.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24512-24519 1 0.00% 88.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 139 0.20% 89.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24704-24711 1 0.00% 89.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24768-24775 1 0.00% 89.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 29 0.04% 89.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24896-24903 2 0.00% 89.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 18 0.03% 89.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25280-25287 1 0.00% 89.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 77 0.11% 89.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 2 0.00% 89.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 90 0.13% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 19 0.03% 89.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 104 0.15% 89.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 14 0.02% 89.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 1 0.00% 89.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 87 0.12% 89.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26816-26823 2 0.00% 89.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 94 0.13% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 12 0.02% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27200-27207 1 0.00% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27264-27271 2 0.00% 89.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27328-27335 1 0.00% 89.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 5 0.01% 89.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27520-27527 1 0.00% 89.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27584-27591 1 0.00% 89.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 143 0.20% 90.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27776-27783 1 0.00% 90.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 12 0.02% 82.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 4 0.01% 82.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 80 0.11% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 5 0.01% 82.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 21 0.03% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 6 0.01% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 25 0.04% 82.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 5 0.01% 82.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 3 0.00% 82.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 5 0.01% 82.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 24 0.03% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 4 0.01% 82.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 11 0.02% 82.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 94 0.13% 82.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 1 0.00% 82.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 12 0.02% 82.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 4 0.01% 82.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 79 0.11% 82.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 3 0.00% 82.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 3 0.00% 82.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 2 0.00% 82.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 32 0.05% 82.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 4 0.01% 82.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 8 0.01% 82.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 266 0.38% 83.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 2 0.00% 83.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 25 0.04% 83.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 67 0.09% 83.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8775 3 0.00% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8839 1 0.00% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 85 0.12% 83.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9159 1 0.00% 83.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 19 0.03% 83.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9287 1 0.00% 83.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9351 1 0.00% 83.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 13 0.02% 83.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9543 1 0.00% 83.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 69 0.10% 83.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9799 1 0.00% 83.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9863 2 0.00% 83.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9927 1 0.00% 83.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 92 0.13% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10183 1 0.00% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 80 0.11% 83.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 87 0.12% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10567 1 0.00% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10631 2 0.00% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10695 1 0.00% 84.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 16 0.02% 84.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 75 0.11% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 1 0.00% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 80 0.11% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11335 2 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11399 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11456-11463 1 0.00% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 15 0.02% 84.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 10 0.01% 84.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 70 0.10% 84.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12103 1 0.00% 84.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12167 1 0.00% 84.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12231 1 0.00% 84.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 175 0.25% 84.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12359 1 0.00% 84.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 22 0.03% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12679 1 0.00% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 37 0.05% 84.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 84.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 80 0.11% 84.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 161 0.23% 85.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 8 0.01% 85.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13703 1 0.00% 85.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 12 0.02% 85.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13895 2 0.00% 85.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13959 2 0.00% 85.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 25 0.04% 85.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14151 1 0.00% 85.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 1 0.00% 85.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 180 0.25% 85.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14407 1 0.00% 85.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14535 1 0.00% 85.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 23 0.03% 85.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14663 1 0.00% 85.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 2 0.00% 85.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14983 1 0.00% 85.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15047 1 0.00% 85.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 22 0.03% 85.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 1 0.00% 85.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 213 0.30% 85.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15559 1 0.00% 85.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 15 0.02% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15687 2 0.00% 85.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 5 0.01% 85.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15943 1 0.00% 85.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16007 1 0.00% 85.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 4 0.01% 85.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16199 3 0.00% 85.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16327 1 0.00% 85.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 278 0.39% 86.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16583 1 0.00% 86.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 6 0.01% 86.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 6 0.01% 86.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 16 0.02% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17223 2 0.00% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 4 0.01% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 216 0.30% 86.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17600-17607 4 0.01% 86.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 28 0.04% 86.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 6 0.01% 86.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18112-18119 2 0.00% 86.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 20 0.03% 86.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 1 0.00% 86.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 175 0.25% 86.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18560-18567 1 0.00% 86.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 21 0.03% 86.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18752-18759 2 0.00% 86.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 11 0.02% 86.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 1 0.00% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 12 0.02% 86.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 2 0.00% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19392-19399 2 0.00% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 153 0.22% 87.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19591 1 0.00% 87.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19648-19655 2 0.00% 87.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 76 0.11% 87.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19776-19783 4 0.01% 87.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19840-19847 1 0.00% 87.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19904-19911 1 0.00% 87.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 33 0.05% 87.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 20 0.03% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20288-20295 1 0.00% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 1 0.00% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20416-20423 1 0.00% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 171 0.24% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20608-20615 1 0.00% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 75 0.11% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20928-20935 1 0.00% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 12 0.02% 87.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21056-21063 1 0.00% 87.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 17 0.02% 87.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 3 0.00% 87.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 73 0.10% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21568-21575 1 0.00% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21632-21639 1 0.00% 87.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21696-21703 1 0.00% 87.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 72 0.10% 87.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21824-21831 2 0.00% 87.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 1 0.00% 87.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 12 0.02% 88.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22080-22087 1 0.00% 88.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22144-22151 1 0.00% 88.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22208-22215 2 0.00% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 88 0.12% 88.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22464-22471 2 0.00% 88.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 73 0.10% 88.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22656-22663 3 0.00% 88.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 94 0.13% 88.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22848-22855 1 0.00% 88.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 67 0.09% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23168-23175 1 0.00% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 10 0.01% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23360-23367 1 0.00% 88.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23424-23431 1 0.00% 88.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23488-23495 1 0.00% 88.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 18 0.03% 88.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23680-23687 2 0.00% 88.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23744-23751 1 0.00% 88.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 82 0.12% 88.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 73 0.10% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 24 0.03% 88.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 1 0.00% 88.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24512-24519 1 0.00% 88.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 150 0.21% 88.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24704-24711 1 0.00% 89.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24768-24775 1 0.00% 89.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 25 0.04% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24960-24967 1 0.00% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 68 0.10% 89.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 86 0.12% 89.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25536-25543 1 0.00% 89.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 20 0.03% 89.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25792-25799 1 0.00% 89.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 14 0.02% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25984-25991 3 0.00% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26048-26055 1 0.00% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 69 0.10% 89.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26176-26183 2 0.00% 89.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26247 2 0.00% 89.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26311 2 0.00% 89.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 93 0.13% 89.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26432-26439 1 0.00% 89.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 2 0.00% 89.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 75 0.11% 89.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26688-26695 1 0.00% 89.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 84 0.12% 89.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27072-27079 1 0.00% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 14 0.02% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27264-27271 1 0.00% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27328-27335 2 0.00% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 75 0.11% 89.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 1 0.00% 89.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 77 0.11% 90.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27712-27719 1 0.00% 90.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27840-27847 1 0.00% 90.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::27904-27911 16 0.02% 90.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27968-27975 2 0.00% 90.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 5 0.01% 90.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28224-28231 2 0.00% 90.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 82 0.12% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28032-28039 1 0.00% 90.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28096-28103 1 0.00% 90.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 8 0.01% 90.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28224-28231 2 0.00% 90.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 1 0.00% 90.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 75 0.11% 90.17% # Bytes accessed per row activation system.physmem.bytesPerActivate::28480-28487 1 0.00% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 1 0.00% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 157 0.22% 90.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28736-28743 2 0.00% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28800-28807 1 0.00% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28864-28871 1 0.00% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 22 0.03% 90.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 2 0.00% 90.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 67 0.09% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29376-29383 1 0.00% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 16 0.02% 90.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29511 1 0.00% 90.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29575 3 0.00% 90.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 139 0.20% 90.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 3 0.00% 90.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 13 0.02% 90.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30016-30023 1 0.00% 90.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30080-30087 2 0.00% 90.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 17 0.02% 90.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30279 4 0.01% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 11 0.02% 90.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30528-30535 2 0.00% 90.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 1 0.00% 90.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 213 0.30% 91.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30848-30855 2 0.00% 91.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30912-30919 2 0.00% 91.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 26 0.04% 91.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31040-31047 1 0.00% 91.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31168-31175 1 0.00% 91.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 17 0.02% 91.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31367 1 0.00% 91.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 70 0.10% 91.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 1 0.00% 91.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 147 0.21% 91.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31808-31815 1 0.00% 91.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 14 0.02% 91.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32064-32071 1 0.00% 91.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32135 1 0.00% 91.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 20 0.03% 91.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32320-32327 1 0.00% 91.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32384-32391 2 0.00% 91.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32448-32455 1 0.00% 91.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 14 0.02% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32640-32647 1 0.00% 91.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32704-32711 1 0.00% 91.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 271 0.38% 91.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 14 0.02% 91.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 20 0.03% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 1 0.00% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 20 0.03% 92.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33607 1 0.00% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33671 4 0.01% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33735 1 0.00% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 153 0.22% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33856-33863 1 0.00% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 71 0.10% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34112-34119 1 0.00% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34176-34183 1 0.00% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 15 0.02% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34368-34375 1 0.00% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34432-34439 2 0.00% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 26 0.04% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34624-34631 2 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 211 0.30% 92.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 7 0.01% 92.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 15 0.02% 92.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35456-35463 1 0.00% 92.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 13 0.02% 92.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 136 0.19% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 19 0.03% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36288-36295 1 0.00% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 67 0.09% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36480-36487 1 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 18 0.03% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36736-36743 1 0.00% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 155 0.22% 93.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 79 0.11% 93.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37312-37319 1 0.00% 93.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 3 0.00% 93.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37440-37447 1 0.00% 93.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37568-37575 1 0.00% 93.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 12 0.02% 93.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37696-37703 1 0.00% 93.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 140 0.20% 93.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38016-38023 1 0.00% 93.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 3 0.00% 93.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 13 0.02% 93.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 1 0.00% 93.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 93 0.13% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 85 0.12% 93.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 15 0.02% 93.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39360-39367 2 0.00% 93.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 104 0.15% 94.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39616-39623 1 0.00% 94.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 19 0.03% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 90 0.13% 94.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 75 0.11% 94.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 16 0.02% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40576-40583 2 0.00% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 30 0.04% 94.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40832-40839 1 0.00% 94.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 138 0.19% 94.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 29 0.04% 94.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41280-41287 1 0.00% 94.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 18 0.03% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41536-41543 1 0.00% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41600-41607 1 0.00% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41664-41671 1 0.00% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 74 0.10% 94.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41792-41799 2 0.00% 94.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41920-41927 2 0.00% 94.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 90 0.13% 94.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42176-42183 1 0.00% 94.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 19 0.03% 94.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 98 0.14% 95.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42695 1 0.00% 95.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 15 0.02% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28615 1 0.00% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 176 0.25% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28743 1 0.00% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 20 0.03% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28992-28999 1 0.00% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29056-29063 2 0.00% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 1 0.00% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 31 0.04% 90.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29248-29255 1 0.00% 90.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29312-29319 2 0.00% 90.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29376-29383 3 0.00% 90.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 76 0.11% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 1 0.00% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 149 0.21% 90.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 1 0.00% 90.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 1 0.00% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 13 0.02% 90.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30080-30087 2 0.00% 90.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 7 0.01% 90.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30272-30279 1 0.00% 90.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 23 0.03% 90.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30528-30535 2 0.00% 90.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30656-30663 1 0.00% 90.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 175 0.25% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30784-30791 2 0.00% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30919 6 0.01% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 19 0.03% 91.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31168-31175 1 0.00% 91.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 4 0.01% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31367 1 0.00% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 24 0.03% 91.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 2 0.00% 91.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31680-31687 1 0.00% 91.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 210 0.30% 91.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31808-31815 1 0.00% 91.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31936-31943 1 0.00% 91.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 12 0.02% 91.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 5 0.01% 91.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32391 1 0.00% 91.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 5 0.01% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32704-32711 2 0.00% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 275 0.39% 91.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 4 0.01% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33159 1 0.00% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 5 0.01% 91.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 1 0.00% 91.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33472-33479 1 0.00% 91.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 21 0.03% 92.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 1 0.00% 92.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33671 4 0.01% 92.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 214 0.30% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33920-33927 1 0.00% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33984-33991 1 0.00% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 20 0.03% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34176-34183 1 0.00% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 2 0.00% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 21 0.03% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 167 0.24% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 18 0.03% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35200-35207 1 0.00% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 7 0.01% 92.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35456-35463 1 0.00% 92.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35520-35527 1 0.00% 92.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 13 0.02% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35648-35655 1 0.00% 92.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35712-35719 1 0.00% 92.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 147 0.21% 92.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35968-35975 1 0.00% 92.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 73 0.10% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36160-36167 1 0.00% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 1 0.00% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 29 0.04% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36416-36423 1 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36480-36487 1 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 20 0.03% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36800-36807 1 0.00% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 174 0.25% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 72 0.10% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 7 0.01% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 17 0.02% 93.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37696-37703 2 0.00% 93.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 76 0.11% 93.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 72 0.10% 93.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38336-38343 1 0.00% 93.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 12 0.02% 93.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38592-38599 1 0.00% 93.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 83 0.12% 93.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 77 0.11% 93.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39040-39047 2 0.00% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 93 0.13% 94.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39360-39367 1 0.00% 94.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 65 0.09% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 1 0.00% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 10 0.01% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 17 0.02% 94.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40000-40007 2 0.00% 94.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40128-40135 1 0.00% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 82 0.12% 94.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40256-40263 1 0.00% 94.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 67 0.09% 94.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 94.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 23 0.03% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40896-40903 1 0.00% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 150 0.21% 94.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41024-41031 1 0.00% 94.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41088-41095 1 0.00% 94.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 23 0.03% 94.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41280-41287 1 0.00% 94.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41344-41351 2 0.00% 94.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 70 0.10% 94.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41536-41543 1 0.00% 94.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41664-41671 1 0.00% 94.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 82 0.12% 94.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41792-41799 1 0.00% 94.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 16 0.02% 94.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 13 0.02% 94.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42368-42375 1 0.00% 94.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 66 0.09% 95.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 95.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 92 0.13% 95.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::42816-42823 1 0.00% 95.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42880-42887 2 0.00% 95.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 82 0.12% 95.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43200-43207 1 0.00% 95.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 90 0.13% 95.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43392-43399 1 0.00% 95.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 12 0.02% 95.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43712-43719 1 0.00% 95.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 4 0.01% 95.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 144 0.20% 95.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44096-44103 2 0.00% 95.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 12 0.02% 95.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44416-44423 2 0.00% 95.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44480-44487 1 0.00% 95.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 5 0.01% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 85 0.12% 95.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 155 0.22% 95.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45120-45127 1 0.00% 95.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45191 1 0.00% 95.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 16 0.02% 96.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45440-45447 1 0.00% 96.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45504-45511 2 0.00% 96.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 71 0.10% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45632-45639 2 0.00% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45760-45767 1 0.00% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 19 0.03% 96.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45888-45895 1 0.00% 96.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 138 0.19% 96.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 14 0.02% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46528-46535 1 0.00% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 15 0.02% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 10 0.01% 96.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47040-47047 1 0.00% 96.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 214 0.30% 96.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 31 0.04% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47488-47495 1 0.00% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 15 0.02% 96.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47680-47687 1 0.00% 96.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 70 0.10% 96.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 1 0.00% 96.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 146 0.21% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 10 0.01% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 20 0.03% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 13 0.02% 97.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48832-48839 2 0.00% 97.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 13 0.02% 97.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 5 0.01% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 2 0.00% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 1979 2.78% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42944-42951 1 0.00% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 75 0.11% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 86 0.12% 95.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 12 0.02% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 2 0.00% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 74 0.10% 95.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 2 0.00% 95.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 73 0.10% 95.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 3 0.00% 95.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 95.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 16 0.02% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 9 0.01% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44608-44615 2 0.00% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 74 0.10% 95.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 4 0.01% 95.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 173 0.24% 96.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45120-45127 1 0.00% 96.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 96.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 19 0.03% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45504-45511 1 0.00% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 34 0.05% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 2 0.00% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 76 0.11% 96.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 150 0.21% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46208-46215 1 0.00% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 8 0.01% 96.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46528-46535 1 0.00% 96.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 9 0.01% 96.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 17 0.02% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 174 0.25% 96.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 22 0.03% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47488-47495 1 0.00% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 2 0.00% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 3 0.00% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 21 0.03% 96.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 208 0.29% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 1 0.00% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 12 0.02% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 4 0.01% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 10 0.01% 97.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 4 0.01% 97.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 3 0.00% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 3 0.00% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 3 0.00% 97.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 2000 2.82% 99.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49792-49799 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49280-49287 1 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49664-49671 2 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50048-50055 2 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::50176-50183 2 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50304-50311 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::50368-50375 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50432-50439 2 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50496-50503 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::50752-50759 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50880-50887 4 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50944-50951 3 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51008-51015 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51207 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51264-51271 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51328-51335 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51463 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51648-51655 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51712-51719 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50944-50951 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51328-51335 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 4 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51520-51527 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51584-51591 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51648-51655 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51712-51719 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51904-51911 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51968-51975 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::52160-52167 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52352-52359 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52672-52679 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 71125 # Bytes accessed per row activation -system.physmem.totQLat 151840872500 # Total ticks spent queuing -system.physmem.totMemAccLat 191562815000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 31109410000 # Total ticks spent in databus transfers -system.physmem.totBankLat 8612532500 # Total ticks spent accessing banks -system.physmem.avgQLat 24404.33 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1384.23 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::52416-52423 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 70891 # Bytes accessed per row activation +system.physmem.totQLat 151784626000 # Total ticks spent queuing +system.physmem.totMemAccLat 191524282250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 31106155000 # Total ticks spent in databus transfers +system.physmem.totBankLat 8633501250 # Total ticks spent accessing banks +system.physmem.avgQLat 24397.84 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1387.75 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30788.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 360.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30785.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 360.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 6.70 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 53.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 6.60 # Average system write bandwidth in MiByte/s @@ -708,14 +724,14 @@ system.physmem.busUtil 2.87 # Da system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.06 # Average write queue length when enqueuing -system.physmem.readRowHits 6168484 # Number of row buffer hits during reads -system.physmem.writeRowHits 97939 # Number of row buffer hits during writes +system.physmem.avgWrQLen 10.13 # Average write queue length when enqueuing +system.physmem.readRowHits 6167948 # Number of row buffer hits during reads +system.physmem.writeRowHits 98004 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.14 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.66 # Row buffer hit rate for writes -system.physmem.avgGap 156006.94 # Average gap between requests +system.physmem.writeRowHitRate 84.77 # Row buffer hit rate for writes +system.physmem.avgGap 156007.30 # Average gap between requests system.physmem.pageHitRate 98.88 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 3.92 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 3.90 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -734,286 +750,286 @@ system.realview.nvmem.bw_inst_read::total 406 # I system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 62369736 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7306752 # Transaction distribution -system.membus.trans_dist::ReadResp 7306752 # Transaction distribution -system.membus.trans_dist::WriteReq 767894 # Transaction distribution -system.membus.trans_dist::WriteResp 767894 # Transaction distribution -system.membus.trans_dist::Writeback 66695 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33888 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17695 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12605 # Transaction distribution -system.membus.trans_dist::ReadExReq 138070 # Transaction distribution -system.membus.trans_dist::ReadExResp 137680 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382518 # Packet count per connected master and slave (bytes) +system.membus.throughput 62368825 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7306736 # Transaction distribution +system.membus.trans_dist::ReadResp 7306736 # Transaction distribution +system.membus.trans_dist::WriteReq 767886 # Transaction distribution +system.membus.trans_dist::WriteResp 767886 # Transaction distribution +system.membus.trans_dist::Writeback 66680 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33856 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17703 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12570 # Transaction distribution +system.membus.trans_dist::ReadExReq 138080 # Transaction distribution +system.membus.trans_dist::ReadExResp 137692 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382504 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11642 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 842 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971209 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4366229 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971133 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4366129 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12189696 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12189696 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 16555925 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389781 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 16555825 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389767 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23284 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23264 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1684 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729972 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20145177 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729012 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20144183 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 48758784 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 68903961 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 68903961 # Total data (bytes) +system.membus.tot_pkt_size::total 68902967 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 68902967 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487006499 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486954500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9880000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9891500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 749500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 747500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 8612723499 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 8614133500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4837509170 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4838543340 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 13760375954 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 13759512942 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) system.l2c.tags.replacements 72740 # number of replacements -system.l2c.tags.tagsinuse 53853.567584 # Cycle average of tags in use -system.l2c.tags.total_refs 1839137 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 53860.173191 # Cycle average of tags in use +system.l2c.tags.total_refs 1837966 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 137924 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.334423 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 13.325933 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39512.680536 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.162068 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.257969 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4009.847433 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2829.767621 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.955070 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3709.355619 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3778.541270 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.602916 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000079 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.061185 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043179 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000121 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.056600 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.057656 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.821740 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 22065 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4358 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 386342 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166614 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30647 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5089 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 590258 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 198399 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1403772 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 581386 # number of Writeback hits -system.l2c.Writeback_hits::total 581386 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1334 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 750 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2084 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 191 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 137 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 328 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48317 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58643 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106960 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 22065 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4358 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 386342 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214931 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30647 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5089 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 590258 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 257042 # number of demand (read+write) hits -system.l2c.demand_hits::total 1510732 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22065 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4358 # number of overall hits -system.l2c.overall_hits::cpu0.inst 386342 # number of overall hits -system.l2c.overall_hits::cpu0.data 214931 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30647 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5089 # number of overall hits -system.l2c.overall_hits::cpu1.inst 590258 # number of overall hits -system.l2c.overall_hits::cpu1.data 257042 # number of overall hits -system.l2c.overall_hits::total 1510732 # number of overall hits +system.l2c.tags.occ_blocks::writebacks 39518.362493 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.391068 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.010261 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4016.186215 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2832.215798 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.504423 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3702.179063 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3777.323870 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.603002 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000082 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.061282 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043216 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000130 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.056491 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.057637 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.821841 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 22002 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4348 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 385872 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166544 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 31083 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5052 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 589425 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 198327 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1402653 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 581363 # number of Writeback hits +system.l2c.Writeback_hits::total 581363 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1344 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 738 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2082 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 204 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 140 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 344 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48345 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58632 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106977 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 22002 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4348 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 385872 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 214889 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 31083 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5052 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 589425 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 256959 # number of demand (read+write) hits +system.l2c.demand_hits::total 1509630 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 22002 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4348 # number of overall hits +system.l2c.overall_hits::cpu0.inst 385872 # number of overall hits +system.l2c.overall_hits::cpu0.data 214889 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 31083 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5052 # number of overall hits +system.l2c.overall_hits::cpu1.inst 589425 # number of overall hits +system.l2c.overall_hits::cpu1.data 256959 # number of overall hits +system.l2c.overall_hits::total 1509630 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6260 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6384 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6325 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6267 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25263 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5164 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3801 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8965 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 637 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 413 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1050 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63263 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 77007 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140270 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu0.inst 6278 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6388 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 13 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 6308 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 6245 # number of ReadReq misses +system.l2c.ReadReq_misses::total 25248 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5144 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3776 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8920 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 633 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 420 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1053 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63281 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 77008 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140289 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 13 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6260 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69647 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6325 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 83274 # number of demand (read+write) misses -system.l2c.demand_misses::total 165533 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6278 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69669 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6308 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 83253 # number of demand (read+write) misses +system.l2c.demand_misses::total 165537 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 13 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6260 # number of overall misses -system.l2c.overall_misses::cpu0.data 69647 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6325 # number of overall misses -system.l2c.overall_misses::cpu1.data 83274 # number of overall misses -system.l2c.overall_misses::total 165533 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1016250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 477500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 449841750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 482248247 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 862750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 476239250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 488675250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1899360997 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 8963096 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 12325976 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 21289072 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 488979 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2955872 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3444851 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4446470608 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 6273738055 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10720208663 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 1016250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 477500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 449841750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4928718855 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 862750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 476239250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 6762413305 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 12619569660 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 1016250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 477500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 449841750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 4928718855 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 862750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 476239250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 6762413305 # number of overall miss cycles -system.l2c.overall_miss_latency::total 12619569660 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 22078 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 4361 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 392602 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 172998 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 30658 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 5089 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 596583 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 204666 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1429035 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 581386 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 581386 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6498 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4551 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 11049 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 828 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 550 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1378 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111580 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 135650 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247230 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 22078 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 4361 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 392602 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 284578 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 30658 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 5089 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 596583 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 340316 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1676265 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 22078 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 4361 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 392602 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 284578 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 30658 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5089 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 596583 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 340316 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1676265 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000589 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000688 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015945 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036902 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000359 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010602 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.030621 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.017678 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.794706 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.835201 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.811386 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.769324 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.750909 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.761974 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.566974 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.567689 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.567366 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000589 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000688 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015945 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.244738 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000359 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010602 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.244696 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.098751 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000589 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000688 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015945 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.244738 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000359 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010602 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.244696 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.098751 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 78173.076923 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 159166.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71859.704473 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 75540.138941 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 78431.818182 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75294.743083 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 77975.945428 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 75183.509362 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1735.688613 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3242.824520 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2374.687340 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 767.627943 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 7157.075061 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3280.810476 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70285.484533 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81469.711260 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 76425.526934 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 78173.076923 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 159166.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 71859.704473 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 70767.137924 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 78431.818182 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 75294.743083 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 81206.778887 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 76235.975062 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 78173.076923 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 159166.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 71859.704473 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 70767.137924 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 78431.818182 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 75294.743083 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 81206.778887 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 76235.975062 # average overall miss latency +system.l2c.overall_misses::cpu0.inst 6278 # number of overall misses +system.l2c.overall_misses::cpu0.data 69669 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 13 # number of overall misses +system.l2c.overall_misses::cpu1.inst 6308 # number of overall misses +system.l2c.overall_misses::cpu1.data 83253 # number of overall misses +system.l2c.overall_misses::total 165537 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1043750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 232500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 459739750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 479407748 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1279750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 475943000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 485330750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1902977248 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 8942096 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 12221481 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 21163577 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 441981 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2952874 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 3394855 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4424511594 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 6267545062 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10692056656 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 1043750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 232500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 459739750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 4903919342 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1279750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 475943000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 6752875812 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 12595033904 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 1043750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 232500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 459739750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 4903919342 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1279750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 475943000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 6752875812 # number of overall miss cycles +system.l2c.overall_miss_latency::total 12595033904 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 22015 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 4351 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 392150 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 172932 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 31096 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 5052 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 595733 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 204572 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1427901 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 581363 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 581363 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6488 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4514 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 11002 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 837 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 560 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1397 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111626 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 135640 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247266 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 22015 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 4351 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 392150 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 284558 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 31096 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5052 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 595733 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 340212 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1675167 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 22015 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 4351 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 392150 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 284558 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 31096 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5052 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 595733 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 340212 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1675167 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000591 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000689 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.016009 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036939 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000418 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010589 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.030527 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.017682 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.792848 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836509 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.810762 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.756272 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.750000 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.753758 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.566902 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.567738 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.567361 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000591 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000689 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.016009 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.244832 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000418 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010589 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.244709 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.098818 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000591 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000689 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.016009 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.244832 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000418 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010589 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.244709 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.098818 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80288.461538 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 77500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73230.288308 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 75048.175955 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 98442.307692 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75450.697527 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 77715.092074 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 75371.405577 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1738.354588 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3236.621028 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2372.598318 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 698.232227 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 7030.652381 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3223.983856 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69918.484126 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81388.233197 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 76214.504744 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 80288.461538 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 77500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 73230.288308 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 70388.829207 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 98442.307692 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 75450.697527 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 81112.702389 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 76085.913747 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 80288.461538 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 77500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 73230.288308 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 70388.829207 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 98442.307692 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 75450.697527 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 81112.702389 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 76085.913747 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1022,168 +1038,168 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 66695 # number of writebacks -system.l2c.writebacks::total 66695 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 27 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 39 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 27 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 39 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 27 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 77 # number of overall MSHR hits +system.l2c.writebacks::writebacks 66680 # number of writebacks +system.l2c.writebacks::total 66680 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 25 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 25 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 25 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 13 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6257 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6345 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6317 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 6240 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25186 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 5164 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3801 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8965 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 637 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 413 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1050 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 63263 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 77007 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140270 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6274 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6350 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 13 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6301 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 6220 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25174 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 5144 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3776 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8920 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 633 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 420 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1053 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 63281 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 77008 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140289 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 13 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6257 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 69608 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6317 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 83247 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 165456 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6274 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 69631 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 13 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6301 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 83228 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 165463 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 13 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6257 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 69608 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6317 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 83247 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 165456 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 853750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 440500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 370880500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 400730997 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 728750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 396408250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 408765250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1578807997 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51771606 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38348722 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 90120328 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6378635 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4156405 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 10535040 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3652529888 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5315357439 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8967887327 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 853750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 440500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 370880500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 4053260885 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 728750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 396408250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 5724122689 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 10546695324 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 853750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 440500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 370880500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 4053260885 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 728750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 396408250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 5724122689 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 10546695324 # number of overall MSHR miss cycles +system.l2c.overall_mshr_misses::cpu0.inst 6274 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 69631 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 13 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 6301 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 83228 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 165463 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 881250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 196000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 380499000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 397371498 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1120250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 396299500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 405553250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1581920748 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51551580 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38112192 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 89663772 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6339632 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4220416 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10560048 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3630585396 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5309182934 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8939768330 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 881250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 196000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 380499000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 4027956894 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1120250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 396299500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 5714736184 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 10521689078 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 881250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 196000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 380499000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 4027956894 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1120250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 396299500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 5714736184 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 10521689078 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6382249 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12399939239 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12399518741 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2397749 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154603749244 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167012468481 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1006407999 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16511968075 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 17518376074 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154603727234 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167012025973 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1005734999 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16506425201 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17512160200 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6382249 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13406347238 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13405253740 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2397749 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171115717319 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 184530844555 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000589 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000688 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015937 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036677 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000359 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010589 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030489 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017624 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.794706 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.835201 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.811386 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.769324 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.750909 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.761974 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566974 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567689 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.567366 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000589 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000688 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015937 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.244601 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000359 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010589 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.244617 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.098705 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000589 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000688 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015937 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.244601 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000359 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010589 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.244617 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.098705 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59274.492568 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63156.973522 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62752.611999 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65507.251603 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 62685.936512 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10025.485283 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10089.113917 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.462688 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10013.555730 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10063.934625 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10033.371429 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57735.641497 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69024.341151 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63933.038618 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59274.492568 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58229.813886 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62752.611999 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68760.708362 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 63743.202567 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59274.492568 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58229.813886 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62752.611999 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68760.708362 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 63743.202567 # average overall mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171110152435 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184524186173 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000591 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000689 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015999 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036720 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000418 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010577 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030405 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017630 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.792848 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836509 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.810762 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.756272 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.750000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.753758 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566902 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567738 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567361 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000591 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000689 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015999 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244699 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000418 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010577 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244636 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098774 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000591 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000689 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015999 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244699 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000418 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010577 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244636 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098774 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67788.461538 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 65333.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60646.955690 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62578.188661 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 86173.076923 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62894.699254 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65201.487138 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62839.467228 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10021.691291 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10093.271186 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10051.992377 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.216430 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10048.609524 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10028.535613 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57372.440322 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68943.264778 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63723.943645 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67788.461538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 65333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60646.955690 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57847.178613 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 86173.076923 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62894.699254 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68663.625030 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 63589.376948 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67788.461538 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 65333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60646.955690 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57847.178613 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 86173.076923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62894.699254 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68663.625030 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63589.376948 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1204,61 +1220,61 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 136691596 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2708551 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2708550 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767894 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767894 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 581386 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 33382 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18023 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51405 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 258959 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 258959 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 785985 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073715 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13547 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55934 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1193885 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4802054 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14684 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 71694 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8011498 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25134272 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34847315 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17444 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88312 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38184256 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47797126 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20356 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 122632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 146211713 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 146211713 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4800508 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4894625900 # Layer occupancy (ticks) +system.toL2Bus.throughput 136617428 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2707473 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2707472 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767886 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767886 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 581363 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 33341 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18047 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 51388 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 258982 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 258982 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 785116 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073701 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13590 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55763 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1192186 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4801848 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14637 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 72416 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8009257 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25105344 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34847157 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17404 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88060 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38129856 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47787842 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20208 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 124384 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 146120255 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 146120255 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4810056 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4893985918 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1771371395 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1769514129 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1514575770 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1514543493 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9208452 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9260456 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 34011429 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 33892454 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2689519761 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 2685747678 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 3237226447 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 3237154790 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 9617950 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 9609448 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 41300207 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 41592193 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 46298101 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7278157 # Transaction distribution -system.iobus.trans_dist::ReadResp 7278157 # Transaction distribution -system.iobus.trans_dist::WriteReq 7950 # Transaction distribution -system.iobus.trans_dist::WriteResp 7950 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30460 # Packet count per connected master and slave (bytes) +system.iobus.throughput 46298079 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7278155 # Transaction distribution +system.iobus.trans_dist::ReadResp 7278155 # Transaction distribution +system.iobus.trans_dist::WriteReq 7945 # Transaction distribution +system.iobus.trans_dist::WriteResp 7945 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30446 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8022 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 724 # Packet count per connected master and slave (bytes) @@ -1281,11 +1297,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382518 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382504 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12189696 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 14572214 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40178 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 14572200 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40164 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1448 # Cumulative packet size per connected master and slave (bytes) @@ -1308,12 +1324,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389781 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389767 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 51148565 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 51148565 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21360000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 51148551 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 51148551 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21348000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 4017000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1361,42 +1377,42 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6094848000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374568000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374559000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 16664438046 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 16664463058 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 6002691 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4577903 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 294712 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3771820 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2913648 # Number of BTB hits +system.cpu0.branchPred.lookups 5998612 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4575425 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 295221 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3794321 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2910648 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.247801 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 672509 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28479 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 76.710642 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 672923 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29222 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8905508 # DTB read hits -system.cpu0.dtb.read_misses 28991 # DTB read misses -system.cpu0.dtb.write_hits 5140500 # DTB write hits -system.cpu0.dtb.write_misses 5723 # DTB write misses +system.cpu0.dtb.read_hits 8906772 # DTB read hits +system.cpu0.dtb.read_misses 28714 # DTB read misses +system.cpu0.dtb.write_hits 5141355 # DTB write hits +system.cpu0.dtb.write_misses 5491 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1824 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 969 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 309 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1825 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 924 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 308 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 556 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8934499 # DTB read accesses -system.cpu0.dtb.write_accesses 5146223 # DTB write accesses +system.cpu0.dtb.perms_faults 586 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8935486 # DTB read accesses +system.cpu0.dtb.write_accesses 5146846 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14046008 # DTB hits -system.cpu0.dtb.misses 34714 # DTB misses -system.cpu0.dtb.accesses 14080722 # DTB accesses -system.cpu0.itb.inst_hits 4219281 # ITB inst hits -system.cpu0.itb.inst_misses 5089 # ITB inst misses +system.cpu0.dtb.hits 14048127 # DTB hits +system.cpu0.dtb.misses 34205 # DTB misses +system.cpu0.dtb.accesses 14082332 # DTB accesses +system.cpu0.itb.inst_hits 4217878 # ITB inst hits +system.cpu0.itb.inst_misses 5102 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1405,530 +1421,530 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1343 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1349 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1465 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1453 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4224370 # ITB inst accesses -system.cpu0.itb.hits 4219281 # DTB hits -system.cpu0.itb.misses 5089 # DTB misses -system.cpu0.itb.accesses 4224370 # DTB accesses -system.cpu0.numCycles 69432037 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4222980 # ITB inst accesses +system.cpu0.itb.hits 4217878 # DTB hits +system.cpu0.itb.misses 5102 # DTB misses +system.cpu0.itb.accesses 4222980 # DTB accesses +system.cpu0.numCycles 69399845 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11713503 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32019404 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6002691 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3586157 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7516730 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1449804 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 61386 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 19631994 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 46872 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1335943 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4217707 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157539 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2075 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41351812 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.000563 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.381156 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11707943 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32011744 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5998612 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3583571 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7516048 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1450698 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 61322 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 19616707 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4844 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 46699 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1334001 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 291 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4216315 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157019 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2077 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41328581 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.001115 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.381687 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33842541 81.84% 81.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 565579 1.37% 83.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 816874 1.98% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 676358 1.64% 86.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 772843 1.87% 88.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 558608 1.35% 90.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 669211 1.62% 91.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 351371 0.85% 92.51% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3098427 7.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33820062 81.83% 81.83% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 563590 1.36% 83.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 816833 1.98% 85.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 678550 1.64% 86.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 773451 1.87% 88.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 557877 1.35% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 667950 1.62% 91.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 351268 0.85% 92.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3099000 7.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41351812 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.086454 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.461162 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12216999 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20826551 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6820783 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 510850 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 976629 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 935170 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64759 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40012064 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213022 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 976629 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12786291 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5985032 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12800887 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6711570 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2091403 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38907337 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1875 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 435425 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1163203 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 107 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39252215 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175728295 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 161804372 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 3955 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30935092 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8317122 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411284 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370379 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5367119 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7645996 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5688511 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1121166 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1220161 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36823164 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895382 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37236653 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 80347 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6279547 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13158300 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256522 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41351812 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.900484 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.514831 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41328581 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.086436 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.461265 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12211654 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20807916 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6822131 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 509652 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 977228 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 934234 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64577 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40012411 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 212282 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 977228 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12781253 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5974864 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12788176 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6710782 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2096278 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38908722 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1870 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 435924 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1167673 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 74 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39248766 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175739111 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 161807828 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 3998 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30938690 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8310075 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411292 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370393 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5377655 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7648768 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5690459 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1124911 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1238842 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36825251 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895403 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37248866 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80758 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6273186 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13119240 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256527 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41328581 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.901286 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.515261 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26282952 63.56% 63.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5688374 13.76% 77.32% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3116432 7.54% 84.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2466494 5.96% 90.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2112034 5.11% 95.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 939185 2.27% 98.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 506930 1.23% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 184996 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54415 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26256934 63.53% 63.53% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5686623 13.76% 77.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3113893 7.53% 84.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2469463 5.98% 90.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2128203 5.15% 95.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 923425 2.23% 98.19% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 509489 1.23% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 185211 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 55340 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41351812 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41328581 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27736 2.59% 2.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 453 0.04% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 842113 78.49% 81.12% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 202594 18.88% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 26660 2.48% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 451 0.04% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 843359 78.54% 81.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 203361 18.94% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22326150 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46947 0.13% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52279 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22336119 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46932 0.13% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9362954 25.14% 85.37% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5447671 14.63% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9364529 25.14% 85.37% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5448283 14.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37236653 # Type of FU issued -system.cpu0.iq.rate 0.536304 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1072896 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028813 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 117004426 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44005967 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34332716 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8422 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4624 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3857 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38252914 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4421 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 307648 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37248866 # Type of FU issued +system.cpu0.iq.rate 0.536728 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1073831 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028829 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 117006401 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44001611 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34345325 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8483 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4644 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3871 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38265951 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4467 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 306869 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1368398 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2491 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13086 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 537466 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1369766 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2413 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12945 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 538318 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192854 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5939 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192768 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5933 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 976629 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4337522 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 100010 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37836354 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 83498 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7645996 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5688511 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571219 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39755 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6621 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13086 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 149491 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117486 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 266977 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36859042 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9220953 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 377611 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 977228 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4326370 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 99368 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37837801 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 83554 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7648768 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5690459 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571361 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39650 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5884 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12945 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150463 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117241 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 267704 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36870822 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9222297 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 378044 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 117808 # number of nop insts executed -system.cpu0.iew.exec_refs 14621413 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4853789 # Number of branches executed -system.cpu0.iew.exec_stores 5400460 # Number of stores executed -system.cpu0.iew.exec_rate 0.530865 # Inst execution rate -system.cpu0.iew.wb_sent 36664720 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34336573 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18306413 # num instructions producing a value -system.cpu0.iew.wb_consumers 35193198 # num instructions consuming a value +system.cpu0.iew.exec_nop 117147 # number of nop insts executed +system.cpu0.iew.exec_refs 14623543 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4855012 # Number of branches executed +system.cpu0.iew.exec_stores 5401246 # Number of stores executed +system.cpu0.iew.exec_rate 0.531281 # Inst execution rate +system.cpu0.iew.wb_sent 36677243 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34349196 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18314277 # num instructions producing a value +system.cpu0.iew.wb_consumers 35200184 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.494535 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520169 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.494946 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520289 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6085996 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638860 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 231074 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40375183 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.775004 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.739173 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6083137 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638876 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 231723 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40351353 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.775579 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.741147 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28737053 71.18% 71.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5697190 14.11% 85.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1882101 4.66% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 980199 2.43% 92.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 786708 1.95% 94.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 526531 1.30% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 398386 0.99% 96.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 216969 0.54% 97.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1150046 2.85% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28712298 71.16% 71.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5699883 14.13% 85.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1888088 4.68% 89.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 980743 2.43% 92.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 789976 1.96% 94.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 505077 1.25% 95.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 395357 0.98% 96.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 219519 0.54% 97.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1160412 2.88% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40375183 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23683551 # Number of instructions committed -system.cpu0.commit.committedOps 31290943 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40351353 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23685352 # Number of instructions committed +system.cpu0.commit.committedOps 31295648 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11428643 # Number of memory references committed -system.cpu0.commit.loads 6277598 # Number of loads committed -system.cpu0.commit.membars 229694 # Number of memory barriers committed -system.cpu0.commit.branches 4245889 # Number of branches committed +system.cpu0.commit.refs 11431143 # Number of memory references committed +system.cpu0.commit.loads 6279002 # Number of loads committed +system.cpu0.commit.membars 229688 # Number of memory barriers committed +system.cpu0.commit.branches 4246153 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27646853 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489416 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1150046 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27651273 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489419 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1160412 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75750709 # The number of ROB reads -system.cpu0.rob.rob_writes 75732466 # The number of ROB writes -system.cpu0.timesIdled 364061 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 28080225 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2140058132 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23602809 # Number of Instructions Simulated -system.cpu0.committedOps 31210201 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23602809 # Number of Instructions Simulated -system.cpu0.cpi 2.941685 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.941685 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.339941 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.339941 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171807193 # number of integer regfile reads -system.cpu0.int_regfile_writes 34081987 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3237 # number of floating regfile reads -system.cpu0.fp_regfile_writes 886 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13003191 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451099 # number of misc regfile writes -system.cpu0.icache.tags.replacements 392605 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.965142 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 3793600 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 393117 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.650053 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7051834000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.965142 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997979 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997979 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3793600 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3793600 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3793600 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3793600 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3793600 # number of overall hits -system.cpu0.icache.overall_hits::total 3793600 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 423979 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 423979 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 423979 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 423979 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 423979 # number of overall misses -system.cpu0.icache.overall_misses::total 423979 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5892352014 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5892352014 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5892352014 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5892352014 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5892352014 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5892352014 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4217579 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4217579 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4217579 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4217579 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4217579 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4217579 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100527 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100527 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100527 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100527 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100527 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100527 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13897.744969 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13897.744969 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13897.744969 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13897.744969 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13897.744969 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13897.744969 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3802 # number of cycles access was blocked +system.cpu0.rob.rob_reads 75718589 # The number of ROB reads +system.cpu0.rob.rob_writes 75736714 # The number of ROB writes +system.cpu0.timesIdled 363087 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 28071264 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2140090760 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23604610 # Number of Instructions Simulated +system.cpu0.committedOps 31214906 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23604610 # Number of Instructions Simulated +system.cpu0.cpi 2.940097 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.940097 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.340125 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.340125 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171854579 # number of integer regfile reads +system.cpu0.int_regfile_writes 34094081 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3288 # number of floating regfile reads +system.cpu0.fp_regfile_writes 904 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13012931 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451079 # number of misc regfile writes +system.cpu0.icache.tags.replacements 392190 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.931857 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 3792228 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 392702 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.656758 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7054061250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.931857 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997914 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997914 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3792228 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3792228 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3792228 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3792228 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3792228 # number of overall hits +system.cpu0.icache.overall_hits::total 3792228 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 423961 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 423961 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 423961 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 423961 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 423961 # number of overall misses +system.cpu0.icache.overall_misses::total 423961 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5895815248 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5895815248 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5895815248 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5895815248 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5895815248 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5895815248 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4216189 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4216189 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4216189 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4216189 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4216189 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4216189 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100556 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100556 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100556 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100556 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100556 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100556 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13906.503777 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13906.503777 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13906.503777 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13906.503777 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13906.503777 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13906.503777 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3717 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 164 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 174 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.182927 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 21.362069 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30839 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30839 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30839 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30839 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30839 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30839 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393140 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 393140 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 393140 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 393140 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 393140 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 393140 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4794002596 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4794002596 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4794002596 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4794002596 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4794002596 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4794002596 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8923000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8923000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8923000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8923000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093215 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093215 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093215 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093215 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093215 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093215 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12194.135921 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12194.135921 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12194.135921 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12194.135921 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12194.135921 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12194.135921 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31238 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 31238 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 31238 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 31238 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 31238 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 31238 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 392723 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 392723 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 392723 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 392723 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 392723 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 392723 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4798060362 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4798060362 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4798060362 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4798060362 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4798060362 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4798060362 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8923500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8923500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8923500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8923500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093146 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093146 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093146 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093146 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093146 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093146 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12217.416250 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12217.416250 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12217.416250 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12217.416250 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12217.416250 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12217.416250 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 276287 # number of replacements -system.cpu0.dcache.tags.tagsinuse 459.684046 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9258198 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 276799 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.447368 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 276315 # number of replacements +system.cpu0.dcache.tags.tagsinuse 459.475838 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9261350 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 276827 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.455371 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 43491250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 459.684046 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.897820 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.897820 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5778274 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5778274 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3158747 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3158747 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139141 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139141 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137092 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137092 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8937021 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8937021 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8937021 # number of overall hits -system.cpu0.dcache.overall_hits::total 8937021 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 392090 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 392090 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1584925 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1584925 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8730 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8730 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7451 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7451 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1977015 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1977015 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1977015 # number of overall misses -system.cpu0.dcache.overall_misses::total 1977015 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5539255201 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5539255201 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 79907349135 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 79907349135 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 90050735 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 90050735 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45818635 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 45818635 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 85446604336 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 85446604336 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 85446604336 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 85446604336 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6170364 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6170364 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4743672 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4743672 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147871 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 147871 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144543 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144543 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10914036 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10914036 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10914036 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10914036 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063544 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063544 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.334114 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.334114 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059038 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059038 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051549 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051549 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181144 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.181144 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181144 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.181144 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14127.509503 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14127.509503 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50417.116983 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50417.116983 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10315.089920 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10315.089920 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6149.326936 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6149.326936 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43220.008111 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 43220.008111 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43220.008111 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 43220.008111 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9481 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 10276 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 609 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 131 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.568144 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 78.442748 # average number of cycles each access was blocked +system.cpu0.dcache.tags.occ_blocks::cpu0.data 459.475838 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.897414 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.897414 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5781234 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5781234 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3158881 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3158881 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139214 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139214 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137082 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137082 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8940115 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8940115 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8940115 # number of overall hits +system.cpu0.dcache.overall_hits::total 8940115 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 391237 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 391237 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1585894 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1585894 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8707 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8707 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7466 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7466 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1977131 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1977131 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1977131 # number of overall misses +system.cpu0.dcache.overall_misses::total 1977131 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5519617945 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5519617945 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 79664471073 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 79664471073 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 90084987 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 90084987 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45897132 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 45897132 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 85184089018 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 85184089018 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 85184089018 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 85184089018 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6172471 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6172471 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744775 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4744775 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147921 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 147921 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144548 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144548 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10917246 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10917246 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10917246 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10917246 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063384 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063384 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.334240 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.334240 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.058863 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058863 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051651 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051651 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181102 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.181102 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181102 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.181102 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14108.118468 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14108.118468 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50233.162540 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50233.162540 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10346.271621 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10346.271621 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6147.486204 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6147.486204 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43084.696471 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 43084.696471 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43084.696471 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 43084.696471 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 10884 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 8688 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 601 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 128 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.109817 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 67.875000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256484 # number of writebacks -system.cpu0.dcache.writebacks::total 256484 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203289 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 203289 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454440 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1454440 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 445 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 445 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657729 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1657729 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657729 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1657729 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188801 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188801 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130485 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130485 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8285 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8285 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7449 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7449 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319286 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319286 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319286 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319286 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2419086873 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2419086873 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5310990170 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5310990170 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68672765 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 68672765 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30919365 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30919365 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7730077043 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7730077043 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7730077043 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7730077043 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504888791 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504888791 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1131913883 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1131913883 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14636802674 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14636802674 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030598 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030598 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.writebacks::writebacks 256502 # number of writebacks +system.cpu0.dcache.writebacks::total 256502 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202469 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 202469 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1455378 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1455378 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 427 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 427 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657847 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1657847 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657847 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1657847 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188768 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188768 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130516 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130516 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8280 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8280 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7466 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7466 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319284 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319284 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319284 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319284 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2415025620 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2415025620 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5290299960 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5290299960 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68915513 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 68915513 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30963868 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30963868 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7705325580 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7705325580 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7705325580 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7705325580 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504357282 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504357282 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1131166881 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1131166881 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14635524163 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14635524163 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030582 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030582 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027507 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027507 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056029 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056029 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051535 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051535 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029255 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029255 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029255 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029255 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12812.892268 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12812.892268 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40701.921064 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40701.921064 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8288.806880 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8288.806880 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4150.807491 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4150.807491 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24210.510461 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24210.510461 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24210.510461 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24210.510461 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055976 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055976 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051651 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051651 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029246 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029246 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029246 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029246 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12793.617668 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12793.617668 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40533.727359 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40533.727359 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8323.129589 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8323.129589 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4147.316903 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4147.316903 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24133.140339 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24133.140339 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24133.140339 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24133.140339 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1936,38 +1952,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 8781819 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7169373 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 406881 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5765537 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 4953289 # Number of BTB hits +system.cpu1.branchPred.lookups 8777296 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7163659 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 407085 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5785994 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 4951432 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 85.912015 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 772113 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42948 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 85.576169 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 773226 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42749 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42694682 # DTB read hits -system.cpu1.dtb.read_misses 36199 # DTB read misses -system.cpu1.dtb.write_hits 6825983 # DTB write hits -system.cpu1.dtb.write_misses 10603 # DTB write misses +system.cpu1.dtb.read_hits 42697243 # DTB read hits +system.cpu1.dtb.read_misses 36228 # DTB read misses +system.cpu1.dtb.write_hits 6821056 # DTB write hits +system.cpu1.dtb.write_misses 10680 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2017 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2691 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 287 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2016 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2677 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 313 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 664 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42730881 # DTB read accesses -system.cpu1.dtb.write_accesses 6836586 # DTB write accesses +system.cpu1.dtb.perms_faults 642 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42733471 # DTB read accesses +system.cpu1.dtb.write_accesses 6831736 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49520665 # DTB hits -system.cpu1.dtb.misses 46802 # DTB misses -system.cpu1.dtb.accesses 49567467 # DTB accesses -system.cpu1.itb.inst_hits 7578103 # ITB inst hits -system.cpu1.itb.inst_misses 5415 # ITB inst misses +system.cpu1.dtb.hits 49518299 # DTB hits +system.cpu1.dtb.misses 46908 # DTB misses +system.cpu1.dtb.accesses 49565207 # DTB accesses +system.cpu1.itb.inst_hits 7578630 # ITB inst hits +system.cpu1.itb.inst_misses 5358 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1976,114 +1992,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1532 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1531 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1496 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1501 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7583518 # ITB inst accesses -system.cpu1.itb.hits 7578103 # DTB hits -system.cpu1.itb.misses 5415 # DTB misses -system.cpu1.itb.accesses 7583518 # DTB accesses -system.cpu1.numCycles 409882606 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7583988 # ITB inst accesses +system.cpu1.itb.hits 7578630 # DTB hits +system.cpu1.itb.misses 5358 # DTB misses +system.cpu1.itb.accesses 7583988 # DTB accesses +system.cpu1.numCycles 409868912 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 18878139 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 60299044 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8781819 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5725402 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13123323 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3309042 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 63154 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 78443797 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5020 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42366 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1440662 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7576329 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 547353 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2737 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114261108 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.645293 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.969526 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 18867977 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 60276924 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8777296 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5724658 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13120224 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3305222 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 63128 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 78446194 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5050 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 41923 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1438516 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7576833 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 547191 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2712 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114243922 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.645142 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.969298 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 101145087 88.52% 88.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796077 0.70% 89.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 936773 0.82% 90.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1687391 1.48% 91.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1395150 1.22% 92.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 571856 0.50% 93.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1930284 1.69% 94.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 409373 0.36% 95.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5389117 4.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 101131185 88.52% 88.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 796172 0.70% 89.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 937688 0.82% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1689020 1.48% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1395475 1.22% 92.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 568258 0.50% 93.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1928403 1.69% 94.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410429 0.36% 95.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5387292 4.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114261108 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.021425 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.147113 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 20196476 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 79405562 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 11967958 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 523276 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2167836 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1103528 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98181 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 69822224 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 326370 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2167836 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 21386304 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 34427825 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40782107 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11206546 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4290490 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 65904089 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18821 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 671145 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3046869 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 355 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 69217965 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 302501585 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 280690851 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6493 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49057579 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20160386 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 444741 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 387793 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7877859 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 12590402 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7938263 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1041211 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1447247 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 60694774 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1157845 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 87723814 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94478 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13427979 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 35976172 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 277080 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114261108 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.767749 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.513486 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114243922 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.021415 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.147064 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20194584 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 79395702 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 11966487 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 522966 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2164183 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1104463 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98170 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 69803405 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 327162 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2164183 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 21384110 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 34428627 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40773355 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11205851 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4287796 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 65891244 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18827 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 669159 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3045569 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 1057 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 69207054 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 302452168 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 280640301 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6501 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49057788 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20149266 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444930 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 388060 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7871220 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12589854 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7931577 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1030582 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1486229 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 60667262 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1158299 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 87712047 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 93594 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13406861 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 35899906 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 277508 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114243922 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.767761 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.513174 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 84436887 73.90% 73.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8271726 7.24% 81.14% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4125209 3.61% 84.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3692140 3.23% 87.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10373138 9.08% 97.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1967895 1.72% 98.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1041724 0.91% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 276233 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 76156 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 84413448 73.89% 73.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8278708 7.25% 81.14% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4125885 3.61% 84.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3695285 3.23% 87.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10373691 9.08% 97.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1966586 1.72% 98.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1039954 0.91% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 274624 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 75741 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114261108 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114243922 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32226 0.41% 0.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 994 0.01% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32139 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 997 0.01% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available @@ -2111,13 +2127,13 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7551636 95.89% 96.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 290793 3.69% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7551678 95.88% 96.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 291209 3.70% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 314062 0.36% 0.36% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 36606472 41.73% 42.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59249 0.07% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36599204 41.73% 42.08% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59264 0.07% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.15% # Type of FU issued @@ -2130,376 +2146,376 @@ system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.15% # Ty system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1508 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43568189 49.67% 91.82% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7174305 8.18% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1508 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43568617 49.67% 91.83% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7169368 8.17% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 87723814 # Type of FU issued -system.cpu1.iq.rate 0.214022 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7875649 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.089778 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 297709996 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 75289267 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53144243 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15477 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8000 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6803 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 95277128 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8273 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 341654 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 87712047 # Type of FU issued +system.cpu1.iq.rate 0.214000 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7876023 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.089794 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 297668917 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 75240910 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53134013 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15426 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7990 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6798 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 95265766 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8242 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 342419 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2834942 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3919 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17226 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1098203 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2834348 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3679 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17028 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1091492 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31919752 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 674526 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31919677 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 675013 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2167836 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 26657812 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 361941 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 61957280 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 112544 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 12590402 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7938263 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869014 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 64925 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4205 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17226 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 200285 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 154811 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 355096 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 85998990 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43064757 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1724824 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2164183 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 26656099 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 359793 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 61930029 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 112185 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12589854 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7931577 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869499 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 63855 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3879 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17028 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 201052 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 154389 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 355441 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 85989380 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43067298 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1722667 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104661 # number of nop insts executed -system.cpu1.iew.exec_refs 50176981 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6911907 # Number of branches executed -system.cpu1.iew.exec_stores 7112224 # Number of stores executed -system.cpu1.iew.exec_rate 0.209814 # Inst execution rate -system.cpu1.iew.wb_sent 85240093 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53151046 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29713379 # num instructions producing a value -system.cpu1.iew.wb_consumers 52980753 # num instructions consuming a value +system.cpu1.iew.exec_nop 104468 # number of nop insts executed +system.cpu1.iew.exec_refs 50174734 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6912361 # Number of branches executed +system.cpu1.iew.exec_stores 7107436 # Number of stores executed +system.cpu1.iew.exec_rate 0.209797 # Inst execution rate +system.cpu1.iew.wb_sent 85230326 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53140811 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29705560 # num instructions producing a value +system.cpu1.iew.wb_consumers 52974804 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.129674 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560833 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.129653 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560749 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13311701 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880765 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 310263 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 112093272 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.429609 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.397405 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13285222 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880791 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 310591 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 112079739 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.429663 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.397726 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 95372912 85.08% 85.08% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8221460 7.33% 92.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2092695 1.87% 94.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1254196 1.12% 95.40% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1248841 1.11% 96.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 572620 0.51% 97.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 992421 0.89% 97.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 531111 0.47% 98.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1807016 1.61% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 95362610 85.08% 85.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8223786 7.34% 92.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2087568 1.86% 94.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1250330 1.12% 95.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1251085 1.12% 96.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 572828 0.51% 97.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 991388 0.88% 97.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 531334 0.47% 98.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1808810 1.61% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 112093272 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38065083 # Number of instructions committed -system.cpu1.commit.committedOps 48156333 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 112079739 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38065286 # Number of instructions committed +system.cpu1.commit.committedOps 48156538 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16595520 # Number of memory references committed -system.cpu1.commit.loads 9755460 # Number of loads committed +system.cpu1.commit.refs 16595591 # Number of memory references committed +system.cpu1.commit.loads 9755506 # Number of loads committed system.cpu1.commit.membars 190120 # Number of memory barriers committed -system.cpu1.commit.branches 5967695 # Number of branches committed +system.cpu1.commit.branches 5967745 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42691207 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534629 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1807016 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42691339 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534627 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1808810 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 170710273 # The number of ROB reads -system.cpu1.rob.rob_writes 125186848 # The number of ROB writes -system.cpu1.timesIdled 1415125 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 295621498 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1799013115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37995444 # Number of Instructions Simulated -system.cpu1.committedOps 48086694 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37995444 # Number of Instructions Simulated -system.cpu1.cpi 10.787678 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.787678 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092698 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092698 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 384930549 # number of integer regfile reads -system.cpu1.int_regfile_writes 55277579 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5074 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2336 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18448778 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405411 # number of misc regfile writes -system.cpu1.icache.tags.replacements 596659 # number of replacements -system.cpu1.icache.tags.tagsinuse 480.521199 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 6934084 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 597171 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 11.611555 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 74930526000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.521199 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938518 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.938518 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 6934084 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6934084 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6934084 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6934084 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 6934084 # number of overall hits -system.cpu1.icache.overall_hits::total 6934084 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 642197 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 642197 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 642197 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 642197 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 642197 # number of overall misses -system.cpu1.icache.overall_misses::total 642197 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8716898620 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8716898620 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8716898620 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8716898620 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8716898620 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8716898620 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7576281 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7576281 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7576281 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7576281 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7576281 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7576281 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084764 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.084764 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084764 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.084764 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084764 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.084764 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13573.558612 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13573.558612 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13573.558612 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13573.558612 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13573.558612 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13573.558612 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 3156 # number of cycles access was blocked +system.cpu1.rob.rob_reads 170668638 # The number of ROB reads +system.cpu1.rob.rob_writes 125130415 # The number of ROB writes +system.cpu1.timesIdled 1414400 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 295624990 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1799026779 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37995647 # Number of Instructions Simulated +system.cpu1.committedOps 48086899 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37995647 # Number of Instructions Simulated +system.cpu1.cpi 10.787260 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.787260 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092702 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092702 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 384897666 # number of integer regfile reads +system.cpu1.int_regfile_writes 55271640 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5031 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2324 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18454230 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405462 # number of misc regfile writes +system.cpu1.icache.tags.replacements 595825 # number of replacements +system.cpu1.icache.tags.tagsinuse 480.685801 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 6935518 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 596337 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 11.630199 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 74918873000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.685801 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938839 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.938839 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 6935518 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6935518 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6935518 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6935518 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 6935518 # number of overall hits +system.cpu1.icache.overall_hits::total 6935518 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 641267 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 641267 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 641267 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 641267 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 641267 # number of overall misses +system.cpu1.icache.overall_misses::total 641267 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8704460293 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8704460293 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8704460293 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8704460293 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8704460293 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8704460293 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7576785 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7576785 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7576785 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7576785 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7576785 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7576785 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084636 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.084636 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084636 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.084636 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084636 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.084636 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13573.847232 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13573.847232 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13573.847232 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13573.847232 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13573.847232 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13573.847232 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2595 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 190 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 176 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.610526 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.744318 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44987 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44987 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44987 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44987 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44987 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44987 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597210 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 597210 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 597210 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 597210 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 597210 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 597210 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7115046481 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7115046481 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7115046481 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7115046481 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7115046481 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7115046481 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44906 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44906 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44906 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44906 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44906 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44906 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596361 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 596361 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 596361 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 596361 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 596361 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 596361 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7105400062 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7105400062 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7105400062 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7105400062 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7105400062 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7105400062 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3356250 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3356250 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3356250 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 3356250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078826 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078826 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078826 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.078826 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078826 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.078826 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11913.810018 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11913.810018 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11913.810018 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11913.810018 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11913.810018 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11913.810018 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078709 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078709 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078709 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.078709 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078709 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.078709 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11914.595458 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11914.595458 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11914.595458 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11914.595458 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11914.595458 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11914.595458 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 360813 # number of replacements -system.cpu1.dcache.tags.tagsinuse 473.792536 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 12672687 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 361164 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.088456 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 70971728000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.792536 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.925376 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.925376 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8306232 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8306232 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4138701 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4138701 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97355 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 97355 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94895 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 94895 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12444933 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12444933 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12444933 # number of overall hits -system.cpu1.dcache.overall_hits::total 12444933 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 398716 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 398716 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1557859 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1557859 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13937 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13937 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10575 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10575 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1956575 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1956575 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1956575 # number of overall misses -system.cpu1.dcache.overall_misses::total 1956575 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6078170016 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6078170016 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 80199088679 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 80199088679 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 128606244 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 128606244 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 52837907 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 52837907 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 86277258695 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 86277258695 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 86277258695 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 86277258695 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8704948 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8704948 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5696560 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5696560 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111292 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 111292 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105470 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 105470 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14401508 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14401508 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14401508 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14401508 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045803 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045803 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273474 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.273474 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125229 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125229 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100265 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100265 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135859 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135859 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135859 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135859 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.359434 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15244.359434 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 51480.325677 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 51480.325677 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9227.684868 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9227.684868 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 4996.492388 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 4996.492388 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 44096.065162 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 44096.065162 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 44096.065162 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 44096.065162 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 31164 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 18449 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3306 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 166 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.426497 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 111.138554 # average number of cycles each access was blocked +system.cpu1.dcache.tags.replacements 360794 # number of replacements +system.cpu1.dcache.tags.tagsinuse 473.291027 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 12676660 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 361148 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.101011 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 70967078000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.291027 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.924397 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.924397 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8309635 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8309635 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4139080 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4139080 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97568 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 97568 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94890 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 94890 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12448715 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12448715 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12448715 # number of overall hits +system.cpu1.dcache.overall_hits::total 12448715 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 397211 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 397211 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1557491 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1557491 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13987 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13987 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10584 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10584 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1954702 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1954702 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1954702 # number of overall misses +system.cpu1.dcache.overall_misses::total 1954702 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6036826508 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6036826508 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 80166814063 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 80166814063 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129072992 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 129072992 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53027415 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 53027415 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 86203640571 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 86203640571 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 86203640571 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 86203640571 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8706846 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8706846 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5696571 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5696571 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111555 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111555 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105474 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105474 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14403417 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14403417 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14403417 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14403417 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045621 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045621 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273409 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273409 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125382 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125382 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100347 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100347 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135711 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135711 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135711 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135711 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15198.034566 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15198.034566 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 51471.767133 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 51471.767133 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9228.068349 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9228.068349 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5010.148810 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5010.148810 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 44100.656044 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 44100.656044 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 44100.656044 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 44100.656044 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 29197 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 19426 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3289 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.877166 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 115.630952 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324902 # number of writebacks -system.cpu1.dcache.writebacks::total 324902 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170345 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 170345 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1396167 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1396167 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1435 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1435 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566512 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1566512 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566512 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1566512 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228371 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 228371 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161692 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161692 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12502 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12502 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10574 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10574 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 390063 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 390063 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 390063 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 390063 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2847018297 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2847018297 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7247965426 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7247965426 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87929505 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87929505 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31688093 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31688093 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 10094983723 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 10094983723 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 10094983723 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 10094983723 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168925175261 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168925175261 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25838951416 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25838951416 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194764126677 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194764126677 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026235 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026235 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028384 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028384 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112335 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112335 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100256 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100256 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027085 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027085 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027085 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027085 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12466.636731 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12466.636731 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44825.751589 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44825.751589 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7033.235082 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7033.235082 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 2996.793361 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 2996.793361 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25880.392970 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25880.392970 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25880.392970 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25880.392970 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324862 # number of writebacks +system.cpu1.dcache.writebacks::total 324862 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 168849 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 168849 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395866 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1395866 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1456 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1456 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1564715 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1564715 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1564715 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1564715 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228362 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228362 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161625 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161625 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12531 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12531 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10581 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10581 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389987 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389987 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389987 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389987 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2843265804 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2843265804 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7240277216 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7240277216 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88160756 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88160756 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31863585 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31863585 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 10083543020 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 10083543020 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 10083543020 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 10083543020 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168925167755 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168925167755 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25834747063 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25834747063 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194759914818 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194759914818 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026228 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026228 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028372 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028372 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112330 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112330 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100319 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100319 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027076 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027076 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027076 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027076 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12450.695843 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12450.695843 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44796.765451 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44796.765451 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7035.412657 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7035.412657 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3011.396371 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3011.396371 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25856.100383 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25856.100383 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25856.100383 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25856.100383 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2521,18 +2537,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 612781961046 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 612781961046 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 612781961046 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 612781961046 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 612762276058 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 612762276058 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 612762276058 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 612762276058 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41730 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41714 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48851 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48863 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index f1e51a584..49d73e9a8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -105,6 +113,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -169,6 +179,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -184,6 +195,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -206,18 +218,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -226,15 +241,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -243,16 +261,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -261,22 +282,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -285,22 +310,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -309,10 +338,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -321,124 +352,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -447,10 +499,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -459,16 +513,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -477,10 +534,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -491,6 +550,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -513,14 +573,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -539,12 +602,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -555,6 +620,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -577,12 +643,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -592,19 +660,23 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -617,6 +689,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -639,6 +712,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -646,6 +720,7 @@ size=1024 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -657,6 +732,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -683,6 +759,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -694,19 +771,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -716,6 +797,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -725,6 +807,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -753,6 +836,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -762,8 +846,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -775,6 +891,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -790,6 +907,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -804,6 +923,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -813,6 +933,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -834,8 +955,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -844,6 +967,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -854,6 +978,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -864,6 +989,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -874,6 +1000,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -888,6 +1015,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -901,6 +1029,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -918,6 +1047,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -930,6 +1060,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -941,6 +1072,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -951,6 +1083,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -963,6 +1096,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -976,6 +1110,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -986,6 +1121,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -996,6 +1132,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1006,6 +1143,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1018,6 +1156,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -1032,6 +1171,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -1044,6 +1184,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -1058,6 +1199,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1068,6 +1210,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1078,6 +1221,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1088,6 +1232,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1096,6 +1241,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1103,11 +1249,13 @@ port=3456 [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index b60e42a06..65955f345 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.525141 # Number of seconds simulated -sim_ticks 2525141046500 # Number of ticks simulated -final_tick 2525141046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.525132 # Number of seconds simulated +sim_ticks 2525131633500 # Number of ticks simulated +final_tick 2525131633500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61643 # Simulator instruction rate (inst/s) -host_op_rate 79318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2581152882 # Simulator tick rate (ticks/s) -host_mem_usage 426780 # Number of bytes of host memory used -host_seconds 978.30 # Real time elapsed on the host -sim_insts 60305756 # Number of instructions simulated -sim_ops 77596741 # Number of ops (including micro ops) simulated +host_inst_rate 49653 # Simulator instruction rate (inst/s) +host_op_rate 63890 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2079077169 # Simulator tick rate (ticks/s) +host_mem_usage 446400 # Number of bytes of host memory used +host_seconds 1214.54 # Real time elapsed on the host +sim_insts 60305678 # Number of instructions simulated +sim_ops 77596684 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 796928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094736 # Number of bytes read from this memory system.physmem.bytes_read::total 129432144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784000 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu.inst 796928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796928 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784384 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800456 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142134 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 42 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12452 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142139 # Number of read requests responded to by this memory system.physmem.num_reads::total 15096843 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59125 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 59131 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47339005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3601548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51257392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498530 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1194417 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2692947 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47339005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4795965 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53950339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 813149 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47339181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3601688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51257583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498688 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1194422 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2693110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498688 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47339181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 315599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4796110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53950692 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15096843 # Number of read requests accepted -system.physmem.writeReqs 813143 # Number of write requests accepted +system.physmem.writeReqs 813149 # Number of write requests accepted system.physmem.readBursts 15096843 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813143 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writeBursts 813149 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 963738752 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 2459200 # Total number of bytes read from write queue system.physmem.bytesWritten 6902144 # Total number of bytes written to DRAM system.physmem.bytesReadSys 129432144 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6800072 # Total written bytes from the system interface side +system.physmem.bytesWrittenSys 6800456 # Total written bytes from the system interface side system.physmem.servicedByWrQ 38425 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 705284 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943582 # Per bank write bursts -system.physmem.perBankRdBursts::1 943145 # Per bank write bursts -system.physmem.perBankRdBursts::2 939291 # Per bank write bursts -system.physmem.perBankRdBursts::3 939307 # Per bank write bursts -system.physmem.perBankRdBursts::4 943115 # Per bank write bursts -system.physmem.perBankRdBursts::5 943141 # Per bank write bursts -system.physmem.perBankRdBursts::6 939138 # Per bank write bursts -system.physmem.perBankRdBursts::7 938546 # Per bank write bursts -system.physmem.perBankRdBursts::8 943996 # Per bank write bursts -system.physmem.perBankRdBursts::9 943390 # Per bank write bursts -system.physmem.perBankRdBursts::10 938426 # Per bank write bursts -system.physmem.perBankRdBursts::11 937974 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 4682 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943580 # Per bank write bursts +system.physmem.perBankRdBursts::1 943152 # Per bank write bursts +system.physmem.perBankRdBursts::2 939288 # Per bank write bursts +system.physmem.perBankRdBursts::3 939310 # Per bank write bursts +system.physmem.perBankRdBursts::4 943113 # Per bank write bursts +system.physmem.perBankRdBursts::5 943139 # Per bank write bursts +system.physmem.perBankRdBursts::6 939134 # Per bank write bursts +system.physmem.perBankRdBursts::7 938551 # Per bank write bursts +system.physmem.perBankRdBursts::8 944000 # Per bank write bursts +system.physmem.perBankRdBursts::9 943392 # Per bank write bursts +system.physmem.perBankRdBursts::10 938425 # Per bank write bursts +system.physmem.perBankRdBursts::11 937973 # Per bank write bursts system.physmem.perBankRdBursts::12 943928 # Per bank write bursts -system.physmem.perBankRdBursts::13 943533 # Per bank write bursts -system.physmem.perBankRdBursts::14 939234 # Per bank write bursts -system.physmem.perBankRdBursts::15 938672 # Per bank write bursts -system.physmem.perBankWrBursts::0 6704 # Per bank write bursts -system.physmem.perBankWrBursts::1 6457 # Per bank write bursts -system.physmem.perBankWrBursts::2 6598 # Per bank write bursts -system.physmem.perBankWrBursts::3 6635 # Per bank write bursts -system.physmem.perBankWrBursts::4 6561 # Per bank write bursts -system.physmem.perBankWrBursts::5 6794 # Per bank write bursts -system.physmem.perBankWrBursts::6 6789 # Per bank write bursts -system.physmem.perBankWrBursts::7 6723 # Per bank write bursts -system.physmem.perBankWrBursts::8 7136 # Per bank write bursts +system.physmem.perBankRdBursts::13 943534 # Per bank write bursts +system.physmem.perBankRdBursts::14 939230 # Per bank write bursts +system.physmem.perBankRdBursts::15 938669 # Per bank write bursts +system.physmem.perBankWrBursts::0 6703 # Per bank write bursts +system.physmem.perBankWrBursts::1 6464 # Per bank write bursts +system.physmem.perBankWrBursts::2 6595 # Per bank write bursts +system.physmem.perBankWrBursts::3 6634 # Per bank write bursts +system.physmem.perBankWrBursts::4 6559 # Per bank write bursts +system.physmem.perBankWrBursts::5 6792 # Per bank write bursts +system.physmem.perBankWrBursts::6 6793 # Per bank write bursts +system.physmem.perBankWrBursts::7 6730 # Per bank write bursts +system.physmem.perBankWrBursts::8 7130 # Per bank write bursts system.physmem.perBankWrBursts::9 6877 # Per bank write bursts -system.physmem.perBankWrBursts::10 6538 # Per bank write bursts -system.physmem.perBankWrBursts::11 6183 # Per bank write bursts -system.physmem.perBankWrBursts::12 7149 # Per bank write bursts -system.physmem.perBankWrBursts::13 6765 # Per bank write bursts -system.physmem.perBankWrBursts::14 7038 # Per bank write bursts -system.physmem.perBankWrBursts::15 6899 # Per bank write bursts +system.physmem.perBankWrBursts::10 6539 # Per bank write bursts +system.physmem.perBankWrBursts::11 6181 # Per bank write bursts +system.physmem.perBankWrBursts::12 7151 # Per bank write bursts +system.physmem.perBankWrBursts::13 6766 # Per bank write bursts +system.physmem.perBankWrBursts::14 7035 # Per bank write bursts +system.physmem.perBankWrBursts::15 6897 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2525139929000 # Total gap between requests +system.physmem.totGap 2525130505500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 36 # Read request sizes (log2) @@ -109,26 +109,26 @@ system.physmem.writePktSize::2 754018 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59125 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1163754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1108384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1064134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3627605 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2618920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2606295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2613037 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 53652 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 58180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 21151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 255 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59131 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1173486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1117689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1073548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3627714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2609756 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2597217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2603662 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 53378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20772 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 238 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -142,29 +142,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4807 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4799 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4794 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 138 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see @@ -174,521 +174,534 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86114 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11271.566528 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1003.490719 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16771.547354 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23576 27.38% 27.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14050 16.32% 43.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2599 3.02% 46.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2090 2.43% 49.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1311 1.52% 50.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1239 1.44% 52.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 869 1.01% 53.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1005 1.17% 54.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 571 0.66% 54.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 602 0.70% 55.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 523 0.61% 56.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 509 0.59% 56.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 284 0.33% 57.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 276 0.32% 57.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 154 0.18% 57.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 642 0.75% 58.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 97 0.11% 58.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 141 0.16% 58.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 78 0.09% 58.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 123 0.14% 58.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 49 0.06% 58.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 518 0.60% 59.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 316 0.37% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 18 0.02% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 102 0.12% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 211 0.25% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 23 0.03% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 55 0.06% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 327 0.38% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 31 0.04% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 124 0.14% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 3 0.00% 61.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 17 0.02% 61.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 9 0.01% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 99 0.11% 61.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 25 0.03% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 90 0.10% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 6 0.01% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 23 0.03% 61.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 2 0.00% 61.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 292 0.34% 61.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 16 0.02% 61.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 98 0.11% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 9 0.01% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 18 0.02% 61.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 8 0.01% 61.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 97 0.11% 62.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 158 0.18% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 373 0.43% 62.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 16 0.02% 62.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 116 0.13% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 99 0.11% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 86134 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11268.950798 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1000.903149 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16775.480046 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23607 27.41% 27.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14081 16.35% 43.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2628 3.05% 46.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2075 2.41% 49.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1317 1.53% 50.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1250 1.45% 52.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 847 0.98% 53.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 989 1.15% 54.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 557 0.65% 54.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 603 0.70% 55.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 514 0.60% 56.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 583 0.68% 56.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 284 0.33% 57.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 264 0.31% 57.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 155 0.18% 57.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 634 0.74% 58.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 90 0.10% 58.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 143 0.17% 58.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 77 0.09% 58.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 121 0.14% 59.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 52 0.06% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 516 0.60% 59.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 33 0.04% 59.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 269 0.31% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 22 0.03% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 94 0.11% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 142 0.16% 60.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 22 0.03% 60.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 57 0.07% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 390 0.45% 60.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 32 0.04% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 120 0.14% 61.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 5 0.01% 61.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 22 0.03% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 8 0.01% 61.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 107 0.12% 61.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 24 0.03% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 86 0.10% 61.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 7 0.01% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 27 0.03% 61.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 4 0.00% 61.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 358 0.42% 61.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 18 0.02% 61.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 154 0.18% 62.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 9 0.01% 62.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 15 0.02% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 8 0.01% 62.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 31 0.04% 62.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 11 0.01% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 39 0.05% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 15 0.02% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 368 0.43% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 15 0.02% 62.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 165 0.19% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 92 0.11% 63.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 19 0.02% 63.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 2 0.00% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 13 0.02% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 426 0.49% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 8 0.01% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 6 0.01% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 28 0.03% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 19 0.02% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 3 0.00% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 89 0.10% 63.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 63.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 10 0.01% 63.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 2 0.00% 63.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 131 0.15% 63.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 1 0.00% 63.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 15 0.02% 63.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 11 0.01% 64.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 413 0.48% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 1 0.00% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 2 0.00% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 87 0.10% 64.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 4 0.00% 64.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 12 0.01% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 5 0.01% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 145 0.17% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 1 0.00% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 24 0.03% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 8 0.01% 64.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 363 0.42% 65.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 3 0.00% 65.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 9 0.01% 65.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 10 0.01% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 1 0.00% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 98 0.11% 65.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 3 0.00% 65.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 9 0.01% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 82 0.10% 65.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 13 0.02% 65.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8135 1 0.00% 65.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 508 0.59% 66.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 76 0.09% 66.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 89 0.10% 66.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 74 0.09% 66.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 350 0.41% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9351 1 0.00% 66.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 17 0.02% 66.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9543 1 0.00% 66.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9607 3 0.00% 66.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9671 1 0.00% 66.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 138 0.16% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9799 1 0.00% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9863 1 0.00% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 79 0.09% 67.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 6 0.01% 67.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 402 0.47% 67.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 84 0.10% 67.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10567 1 0.00% 67.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 76 0.09% 67.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10951 3 0.00% 67.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 15 0.02% 67.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 1 0.00% 67.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 416 0.48% 68.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11399 1 0.00% 68.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 13 0.02% 68.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11719 2 0.00% 68.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 84 0.10% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 95 0.11% 63.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 2 0.00% 63.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 16 0.02% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 379 0.44% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 10 0.01% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 5 0.01% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 88 0.10% 63.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 21 0.02% 63.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 3 0.00% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 146 0.17% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 2 0.00% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 8 0.01% 64.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 2 0.00% 64.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 64 0.07% 64.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 1 0.00% 64.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 13 0.02% 64.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 11 0.01% 64.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 283 0.33% 64.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 1 0.00% 64.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 2 0.00% 64.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 88 0.10% 64.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 4 0.00% 64.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 11 0.01% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 6 0.01% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 153 0.18% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 1 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 78 0.09% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 9 0.01% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 368 0.43% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 2 0.00% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 11 0.01% 65.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 136 0.16% 65.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 9 0.01% 65.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 1 0.00% 65.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 88 0.10% 65.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 2 0.00% 65.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 9 0.01% 65.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 84 0.10% 65.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 11 0.01% 65.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8135 1 0.00% 65.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 389 0.45% 66.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 2 0.00% 66.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 79 0.09% 66.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 78 0.09% 66.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 130 0.15% 66.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9095 1 0.00% 66.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 355 0.41% 66.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9351 2 0.00% 66.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 73 0.08% 67.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9543 1 0.00% 67.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9607 4 0.00% 67.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9671 1 0.00% 67.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 140 0.16% 67.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9799 2 0.00% 67.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9927 1 0.00% 67.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 79 0.09% 67.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 4 0.00% 67.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 272 0.32% 67.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 15 0.02% 67.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10567 1 0.00% 67.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10631 1 0.00% 67.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 132 0.15% 67.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10951 3 0.00% 67.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 75 0.09% 67.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 373 0.43% 68.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11399 1 0.00% 68.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 86 0.10% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11655 1 0.00% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11719 2 0.00% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 77 0.09% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11911 2 0.00% 68.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 98 0.11% 68.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12167 5 0.01% 68.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 335 0.39% 69.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12423 3 0.00% 69.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 141 0.16% 69.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 79 0.09% 69.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 86 0.10% 69.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13127 1 0.00% 69.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 4 0.00% 69.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 286 0.33% 69.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 76 0.09% 69.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 74 0.09% 69.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13895 1 0.00% 69.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 91 0.11% 70.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 3 0.00% 70.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 284 0.33% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14471 2 0.00% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 139 0.16% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14727 4 0.00% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 146 0.17% 70.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14919 2 0.00% 70.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 13 0.02% 70.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15175 1 0.00% 70.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15303 2 0.00% 70.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 405 0.47% 71.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 17 0.02% 71.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 80 0.09% 71.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16071 1 0.00% 71.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 74 0.09% 71.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16263 11 0.01% 71.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 645 0.75% 72.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 72 0.08% 72.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16711 2 0.00% 72.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16839 1 0.00% 72.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 78 0.09% 72.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17095 1 0.00% 72.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 28 0.03% 72.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17287 5 0.01% 72.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 407 0.47% 72.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17543 2 0.00% 72.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 18 0.02% 72.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17735 2 0.00% 72.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17792-17799 3 0.00% 72.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17856-17863 1 0.00% 72.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 147 0.17% 73.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-17991 1 0.00% 73.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18112-18119 2 0.00% 73.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 144 0.17% 73.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 4 0.00% 73.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 279 0.32% 73.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 89 0.10% 73.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18880-18887 2 0.00% 73.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 73 0.08% 73.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19136-19143 1 0.00% 73.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 77 0.09% 73.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 5 0.01% 73.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 263 0.31% 74.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 82 0.10% 74.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 79 0.09% 74.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20096-20103 1 0.00% 74.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 140 0.16% 74.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20288-20295 1 0.00% 74.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 3 0.00% 74.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 343 0.40% 74.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20672-20679 1 0.00% 74.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 96 0.11% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20864-20871 2 0.00% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 82 0.10% 75.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21120-21127 1 0.00% 75.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 144 0.17% 68.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12103 1 0.00% 68.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12167 4 0.00% 68.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 340 0.39% 69.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12359 1 0.00% 69.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 2 0.00% 69.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 26 0.03% 69.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 18 0.02% 69.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12935 1 0.00% 69.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 2 0.00% 69.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 146 0.17% 69.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13127 1 0.00% 69.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 2 0.00% 69.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 339 0.39% 69.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 74 0.09% 69.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 78 0.09% 69.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13895 1 0.00% 69.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13959 1 0.00% 69.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 87 0.10% 70.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14151 2 0.00% 70.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 4 0.00% 70.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 340 0.39% 70.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 79 0.09% 70.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14727 4 0.00% 70.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 86 0.10% 70.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14919 2 0.00% 70.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 13 0.02% 70.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15303 1 0.00% 70.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 405 0.47% 71.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 83 0.10% 71.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 89 0.10% 71.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16071 1 0.00% 71.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 86 0.10% 71.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 12 0.01% 71.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 642 0.75% 72.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 86 0.10% 72.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16711 2 0.00% 72.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16775 1 0.00% 72.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 84 0.10% 72.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17095 1 0.00% 72.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 92 0.11% 72.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 4 0.00% 72.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17351 1 0.00% 72.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 410 0.48% 72.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17479 2 0.00% 72.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17543 3 0.00% 72.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 15 0.02% 72.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17735 1 0.00% 72.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17799 5 0.01% 72.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17863 1 0.00% 72.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 86 0.10% 73.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-17991 1 0.00% 73.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18048-18055 1 0.00% 73.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18112-18119 2 0.00% 73.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 83 0.10% 73.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 3 0.00% 73.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 331 0.38% 73.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 89 0.10% 73.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18880-18887 2 0.00% 73.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 83 0.10% 73.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19136-19143 1 0.00% 73.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 74 0.09% 73.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 3 0.00% 73.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 326 0.38% 74.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19591 3 0.00% 74.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19648-19655 1 0.00% 74.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 138 0.16% 74.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19840-19847 1 0.00% 74.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 15 0.02% 74.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 23 0.03% 74.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20288-20295 1 0.00% 74.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 3 0.00% 74.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 336 0.39% 74.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20608-20615 1 0.00% 74.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20672-20679 2 0.00% 74.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 143 0.17% 75.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20864-20871 3 0.00% 75.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 73 0.08% 75.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 14 0.02% 75.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 4 0.00% 75.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 401 0.47% 75.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21568-21575 1 0.00% 75.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21632-21639 1 0.00% 75.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 17 0.02% 75.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 2 0.00% 75.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 77 0.09% 75.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22144-22151 1 0.00% 75.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 84 0.10% 75.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 3 0.00% 75.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22464-22471 1 0.00% 75.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 400 0.46% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22656-22663 1 0.00% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22720-22727 2 0.00% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 80 0.09% 76.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22912-22919 1 0.00% 76.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22976-22983 2 0.00% 76.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 136 0.16% 76.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23104-23111 1 0.00% 76.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 21 0.02% 76.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23360-23367 3 0.00% 76.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23424-23431 2 0.00% 76.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 351 0.41% 76.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23687 2 0.00% 76.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 73 0.08% 77.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24007 2 0.00% 77.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 83 0.10% 77.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 83 0.10% 77.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24448-24455 4 0.00% 77.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 387 0.45% 77.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 78 0.09% 77.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24960-24967 1 0.00% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25024-25031 1 0.00% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 89 0.10% 77.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25280-25287 1 0.00% 77.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 72 0.08% 77.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 4 0.00% 77.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 349 0.41% 78.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 19 0.02% 78.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25984-25991 3 0.00% 78.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 133 0.15% 78.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26304-26311 2 0.00% 78.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 78 0.09% 78.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 1 0.00% 78.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 401 0.47% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26752-26759 2 0.00% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 82 0.10% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27008-27015 2 0.00% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 77 0.09% 79.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27200-27207 1 0.00% 79.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 15 0.02% 79.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 403 0.47% 79.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 11 0.01% 79.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27968-27975 2 0.00% 79.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28096-28103 1 0.00% 79.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 83 0.10% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 89 0.10% 75.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 3 0.00% 75.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21440-21447 1 0.00% 75.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 367 0.43% 75.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21568-21575 1 0.00% 75.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21632-21639 1 0.00% 75.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 76 0.09% 75.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21824-21831 1 0.00% 75.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 5 0.01% 75.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 129 0.15% 75.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22144-22151 1 0.00% 75.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 14 0.02% 75.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22336-22343 1 0.00% 75.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 3 0.00% 75.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22464-22471 2 0.00% 75.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 268 0.31% 76.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22720-22727 2 0.00% 76.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 78 0.09% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22912-22919 1 0.00% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22976-22983 2 0.00% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 143 0.17% 76.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23104-23111 1 0.00% 76.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23168-23175 1 0.00% 76.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 77 0.09% 76.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23360-23367 3 0.00% 76.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23424-23431 2 0.00% 76.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 350 0.41% 76.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23680-23687 1 0.00% 76.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 126 0.15% 77.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24007 2 0.00% 77.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 74 0.09% 77.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24192-24199 2 0.00% 77.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 82 0.10% 77.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 3 0.00% 77.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 270 0.31% 77.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 79 0.09% 77.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25024-25031 1 0.00% 77.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 77 0.09% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25216-25223 2 0.00% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25280-25287 1 0.00% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 133 0.15% 77.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 2 0.00% 77.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 355 0.41% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 72 0.08% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25984-25991 2 0.00% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 138 0.16% 78.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26311 2 0.00% 78.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 79 0.09% 78.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 2 0.00% 78.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 269 0.31% 79.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26752-26759 1 0.00% 79.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 14 0.02% 79.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27008-27015 4 0.00% 79.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27072-27079 1 0.00% 79.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 130 0.15% 79.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27200-27207 1 0.00% 79.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 74 0.09% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 367 0.43% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 85 0.10% 79.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-27975 2 0.00% 79.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28032-28039 2 0.00% 79.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28096-28103 1 0.00% 79.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 75 0.09% 79.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::28288-28295 2 0.00% 79.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28352-28359 1 0.00% 79.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 97 0.11% 80.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28480-28487 2 0.00% 80.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 2 0.00% 80.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 341 0.40% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28736-28743 1 0.00% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28800-28807 1 0.00% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28864-28871 2 0.00% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 143 0.17% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29056-29063 1 0.00% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 77 0.09% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29248-29255 2 0.00% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 85 0.10% 80.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29511 3 0.00% 80.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29575 2 0.00% 80.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 268 0.31% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 76 0.09% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 74 0.09% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30336-30343 2 0.00% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 92 0.11% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 4 0.00% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 271 0.31% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30848-30855 2 0.00% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30912-30919 1 0.00% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 145 0.17% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31111 2 0.00% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 148 0.17% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31296-31303 1 0.00% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31367 1 0.00% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 19 0.02% 82.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31552-31559 2 0.00% 82.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31680-31687 4 0.00% 82.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 398 0.46% 82.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31936-31943 1 0.00% 82.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 18 0.02% 82.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 78 0.09% 82.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 83 0.10% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 2 0.00% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 143 0.17% 80.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28480-28487 2 0.00% 80.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 4 0.00% 80.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 337 0.39% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28743 1 0.00% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28864-28871 2 0.00% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 26 0.03% 80.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 17 0.02% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29248-29255 2 0.00% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 139 0.16% 80.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 3 0.00% 80.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 4 0.00% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 329 0.38% 81.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 2 0.00% 81.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 70 0.08% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 79 0.09% 81.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 92 0.11% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 4 0.00% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 327 0.38% 81.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30848-30855 4 0.00% 81.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30919 2 0.00% 81.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 84 0.10% 81.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 89 0.10% 82.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31367 1 0.00% 82.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31424-31431 1 0.00% 82.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 19 0.02% 82.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 2 0.00% 82.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31680-31687 1 0.00% 82.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 406 0.47% 82.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 83 0.10% 82.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32064-32071 1 0.00% 82.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 2 0.00% 82.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 82 0.10% 82.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32448-32455 2 0.00% 82.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 93 0.11% 82.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::32576-32583 1 0.00% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 642 0.75% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 645 0.75% 83.56% # Bytes accessed per row activation system.physmem.bytesPerActivate::32832-32839 2 0.00% 83.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 73 0.08% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33216-33223 2 0.00% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 78 0.09% 83.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 4 0.00% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 27 0.03% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33607 2 0.00% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33735 1 0.00% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 406 0.47% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33920-33927 1 0.00% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 16 0.02% 84.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 144 0.17% 84.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 147 0.17% 84.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 269 0.31% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 87 0.10% 85.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 72 0.08% 85.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35456-35463 2 0.00% 85.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 77 0.09% 85.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35712-35719 1 0.00% 85.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 268 0.31% 85.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 81 0.09% 85.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 77 0.09% 85.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36480-36487 1 0.00% 85.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 144 0.17% 85.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36736-36743 2 0.00% 85.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 338 0.39% 86.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36992-36999 1 0.00% 86.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 91 0.11% 86.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 83 0.10% 86.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32896-32903 1 0.00% 83.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 83 0.10% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33088-33095 1 0.00% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33216-33223 2 0.00% 83.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 82 0.10% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 4 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33472-33479 1 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 95 0.11% 83.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33671 1 0.00% 83.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 411 0.48% 84.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 13 0.02% 84.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34112-34119 1 0.00% 84.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 83 0.10% 84.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 86 0.10% 84.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34688-34695 1 0.00% 84.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 328 0.38% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 86 0.10% 85.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35200-35207 1 0.00% 85.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 76 0.09% 85.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35456-35463 3 0.00% 85.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 72 0.08% 85.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35712-35719 1 0.00% 85.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 328 0.38% 85.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 138 0.16% 85.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 1 0.00% 85.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 15 0.02% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36480-36487 3 0.00% 85.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 25 0.03% 85.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 337 0.39% 86.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36992-36999 2 0.00% 86.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 141 0.16% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37184-37191 1 0.00% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 73 0.08% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 3 0.00% 86.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::37568-37575 1 0.00% 86.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 11 0.01% 86.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 404 0.47% 86.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38016-38023 2 0.00% 86.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 15 0.02% 86.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38272-38279 1 0.00% 86.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38336-38343 1 0.00% 86.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 77 0.09% 87.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 1 0.00% 87.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 84 0.10% 87.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 401 0.47% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39040-39047 2 0.00% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39104-39111 1 0.00% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 77 0.09% 87.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 130 0.15% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 15 0.02% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 348 0.40% 88.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40064-40071 3 0.00% 88.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 71 0.08% 88.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 86 0.10% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 78 0.09% 88.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 387 0.45% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41152-41159 2 0.00% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 78 0.09% 89.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41344-41351 2 0.00% 89.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 83 0.10% 89.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 72 0.08% 89.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41856-41863 3 0.00% 89.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 347 0.40% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 18 0.02% 89.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 133 0.15% 89.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42624-42631 3 0.00% 89.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 79 0.09% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42816-42823 1 0.00% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 399 0.46% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 82 0.10% 90.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 76 0.09% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 2 0.00% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 20 0.02% 90.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 403 0.47% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 10 0.01% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 82 0.10% 86.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 365 0.42% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 2 0.00% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 75 0.09% 87.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38336-38343 1 0.00% 87.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 129 0.15% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38464-38471 1 0.00% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 2 0.00% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 14 0.02% 87.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 267 0.31% 87.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39104-39111 1 0.00% 87.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 77 0.09% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39296-39303 1 0.00% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 140 0.16% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 2 0.00% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 70 0.08% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 351 0.41% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40064-40071 1 0.00% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 129 0.15% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 76 0.09% 88.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 2 0.00% 88.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 80 0.09% 88.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40832-40839 2 0.00% 88.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 269 0.31% 88.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 2 0.00% 88.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 77 0.09% 89.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 75 0.09% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 2 0.00% 89.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 131 0.15% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41856-41863 3 0.00% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 349 0.41% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 70 0.08% 89.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 140 0.16% 89.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 2 0.00% 89.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 77 0.09% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 267 0.31% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43136-43143 3 0.00% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 14 0.02% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 127 0.15% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 1 0.00% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 80 0.09% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 364 0.42% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 1 0.00% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 83 0.10% 91.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 81 0.09% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44679 3 0.00% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 96 0.11% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 341 0.40% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 143 0.17% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 82 0.10% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 5 0.01% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 84 0.10% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45888-45895 1 0.00% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 261 0.30% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 73 0.08% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 68 0.08% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 91 0.11% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 272 0.32% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 142 0.16% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 144 0.17% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 25 0.03% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 395 0.46% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 16 0.02% 93.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 76 0.09% 93.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 71 0.08% 94.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 72 0.08% 94.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5013 5.82% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 73 0.08% 91.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 144 0.17% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44864-44871 2 0.00% 91.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 337 0.39% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 24 0.03% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 3 0.00% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 16 0.02% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 3 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 144 0.17% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 2 0.00% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 327 0.38% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 69 0.08% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 79 0.09% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 89 0.10% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 1 0.00% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 334 0.39% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 78 0.09% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 88 0.10% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 24 0.03% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 398 0.46% 93.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 83 0.10% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 77 0.09% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 72 0.08% 94.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 83 0.10% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 3 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5012 5.82% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation @@ -714,15 +727,15 @@ system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86114 # Bytes accessed per row activation -system.physmem.totQLat 365610387500 # Total ticks spent queuing -system.physmem.totMemAccLat 458189280000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::total 86134 # Bytes accessed per row activation +system.physmem.totQLat 365453646000 # Total ticks spent queuing +system.physmem.totMemAccLat 458164497250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 75292090000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17286802500 # Total ticks spent accessing banks -system.physmem.avgQLat 24279.47 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1147.98 # Average bank access latency per DRAM burst +system.physmem.totBankLat 17418761250 # Total ticks spent accessing banks +system.physmem.avgQLat 24269.06 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1156.75 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30427.45 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30425.81 # Average memory access latency per DRAM burst system.physmem.avgRdBW 381.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.26 # Average system read bandwidth in MiByte/s @@ -732,14 +745,14 @@ system.physmem.busUtil 3.00 # Da system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.84 # Average write queue length when enqueuing -system.physmem.readRowHits 14986740 # Number of row buffer hits during reads -system.physmem.writeRowHits 93410 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.83 # Average write queue length when enqueuing +system.physmem.readRowHits 14986798 # Number of row buffer hits during reads +system.physmem.writeRowHits 93332 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.60 # Row buffer hit rate for writes -system.physmem.avgGap 158714.15 # Average gap between requests +system.physmem.writeRowHitRate 86.53 # Row buffer hit rate for writes +system.physmem.avgGap 158713.50 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.73 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 1.72 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -752,50 +765,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54899945 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149440 # Transaction distribution -system.membus.trans_dist::ReadResp 16149440 # Transaction distribution +system.membus.throughput 54900302 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149434 # Transaction distribution +system.membus.trans_dist::ReadResp 16149434 # Transaction distribution system.membus.trans_dist::WriteReq 763332 # Transaction distribution system.membus.trans_dist::WriteResp 763332 # Transaction distribution -system.membus.trans_dist::Writeback 59125 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution +system.membus.trans_dist::Writeback 59131 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4679 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution -system.membus.trans_dist::ReadExReq 131442 # Transaction distribution -system.membus.trans_dist::ReadExResp 131442 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4682 # Transaction distribution +system.membus.trans_dist::ReadExReq 131448 # Transaction distribution +system.membus.trans_dist::ReadExResp 131448 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885779 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272485 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885801 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272507 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34156901 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34156923 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694552 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092441 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694936 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092825 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138630105 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138630105 # Total data (bytes) +system.membus.tot_pkt_size::total 138630489 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138630489 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486773500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486873500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3686000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3694000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17363455000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17363465500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4733701508 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4733669250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33738367951 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33737503451 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -803,7 +816,7 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48285606 # Throughput (bytes/s) +system.iobus.throughput 48285786 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution system.iobus.trans_dist::WriteReq 8157 # Transaction distribution @@ -913,40 +926,40 @@ system.iobus.reqLayer25.occupancy 14942208000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40921194049 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40921719549 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu.branchPred.lookups 14384905 # Number of BP lookups -system.cpu.branchPred.condPredicted 11471084 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 703956 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9467627 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7657685 # Number of BTB hits +system.cpu.branchPred.lookups 14384927 # Number of BP lookups +system.cpu.branchPred.condPredicted 11469310 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704177 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9471049 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7661571 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.882834 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1397242 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72494 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.894640 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398227 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72610 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51179212 # DTB read hits -system.cpu.dtb.read_misses 64531 # DTB read misses -system.cpu.dtb.write_hits 11698539 # DTB write hits -system.cpu.dtb.write_misses 15837 # DTB write misses +system.cpu.dtb.read_hits 51182106 # DTB read hits +system.cpu.dtb.read_misses 64421 # DTB read misses +system.cpu.dtb.write_hits 11699698 # DTB write hits +system.cpu.dtb.write_misses 15824 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3571 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2411 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3567 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2374 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 404 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1396 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51243743 # DTB read accesses -system.cpu.dtb.write_accesses 11714376 # DTB write accesses +system.cpu.dtb.perms_faults 1314 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51246527 # DTB read accesses +system.cpu.dtb.write_accesses 11715522 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62877751 # DTB hits -system.cpu.dtb.misses 80368 # DTB misses -system.cpu.dtb.accesses 62958119 # DTB accesses -system.cpu.itb.inst_hits 11513998 # ITB inst hits -system.cpu.itb.inst_misses 11344 # ITB inst misses +system.cpu.dtb.hits 62881804 # DTB hits +system.cpu.dtb.misses 80245 # DTB misses +system.cpu.dtb.accesses 62962049 # DTB accesses +system.cpu.itb.inst_hits 11522583 # ITB inst hits +system.cpu.itb.inst_misses 11276 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -955,148 +968,148 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2483 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2480 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2968 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3012 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11525342 # ITB inst accesses -system.cpu.itb.hits 11513998 # DTB hits -system.cpu.itb.misses 11344 # DTB misses -system.cpu.itb.accesses 11525342 # DTB accesses -system.cpu.numCycles 474882944 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11533859 # ITB inst accesses +system.cpu.itb.hits 11522583 # DTB hits +system.cpu.itb.misses 11276 # DTB misses +system.cpu.itb.accesses 11533859 # DTB accesses +system.cpu.numCycles 474898657 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29745457 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90266235 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14384905 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9054927 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20140969 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4652912 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 123687 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96003967 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87891 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2685420 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11510536 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 707949 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5425 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151996950 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.740543 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.094686 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29752889 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90273347 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14384927 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9059798 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20146705 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4653497 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122274 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96010555 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 88482 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2690288 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 446 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11519088 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 708911 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5337 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 152021113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.740504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.094585 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131871277 86.76% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1302073 0.86% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1710886 1.13% 88.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2295409 1.51% 90.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2102442 1.38% 91.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1107607 0.73% 92.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2555872 1.68% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 743971 0.49% 94.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8307413 5.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131890125 86.76% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1304050 0.86% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1713045 1.13% 88.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2295968 1.51% 90.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2102742 1.38% 91.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107769 0.73% 92.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2555355 1.68% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 744146 0.49% 94.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8307913 5.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151996950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 152021113 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.030291 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.190081 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31502209 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 98125273 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18366247 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 966197 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3037024 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1956644 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171990 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107262918 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568386 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3037024 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33252800 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39466554 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52672825 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17523888 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6043859 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102275198 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20557 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4063584 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106014240 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 466907038 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432047963 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10635 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78387438 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27626801 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830029 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736499 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12184256 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19715159 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13304037 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1977063 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2478152 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95106473 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1982467 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122897190 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 166901 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18919534 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47250176 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 500160 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151996950 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.808550 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.527901 # Number of insts issued each cycle +system.cpu.fetch.rate 0.190090 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31508438 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 98138099 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18373215 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 963804 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3037557 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1957081 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171807 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107274658 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 567663 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3037557 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33258738 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39476292 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52673596 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17529662 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6045268 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102285915 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004806 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4066044 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 644 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106018919 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 466959682 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432092489 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10446 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78387358 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27631560 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830464 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736820 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12181979 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19715902 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13307123 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1978281 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2470778 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95109477 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1982753 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122906700 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167286 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18927569 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47237054 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 500451 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 152021113 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.808484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.527863 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108284402 71.24% 71.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13439431 8.84% 80.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6944257 4.57% 84.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5857722 3.85% 88.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12372410 8.14% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2808060 1.85% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1695891 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 467423 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127354 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108300469 71.24% 71.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13447891 8.85% 80.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6945073 4.57% 84.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5857007 3.85% 88.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12370739 8.14% 96.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2808869 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1695394 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 467391 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128280 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151996950 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 152021113 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62444 0.71% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8371933 94.63% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412257 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61937 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 6 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8370529 94.64% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412377 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57615534 46.88% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93100 0.08% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57620183 46.88% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93128 0.08% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued @@ -1109,397 +1122,397 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 33 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 25 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 20 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2115 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 25 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 20 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52504661 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12318028 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52507579 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319960 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122897190 # Type of FU issued -system.cpu.iq.rate 0.258795 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8846641 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071984 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 406861293 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116024937 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85463742 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23592 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12620 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10347 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131367569 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12596 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623590 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122906700 # Type of FU issued +system.cpu.iq.rate 0.258806 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8844849 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071964 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406902990 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116036304 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85470220 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23531 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12536 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10316 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131375312 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12571 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623425 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4061151 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6344 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30249 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1572309 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4061911 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6363 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30197 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1575391 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107765 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 681284 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107753 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 681273 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3037024 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30702730 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434457 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97310809 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 203906 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19715159 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13304037 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1409970 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113496 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3538 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30249 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 349429 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269322 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 618751 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120821579 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51866256 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2075611 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3037557 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30701555 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434229 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97313991 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205819 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19715902 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13307123 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410230 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30197 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350181 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268988 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619169 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120829627 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51869148 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2077073 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221869 # number of nop insts executed -system.cpu.iew.exec_refs 64076774 # number of memory reference insts executed -system.cpu.iew.exec_branches 11475076 # Number of branches executed -system.cpu.iew.exec_stores 12210518 # Number of stores executed -system.cpu.iew.exec_rate 0.254424 # Inst execution rate -system.cpu.iew.wb_sent 119883669 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85474089 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47026181 # num instructions producing a value -system.cpu.iew.wb_consumers 87876552 # num instructions consuming a value +system.cpu.iew.exec_nop 221761 # number of nop insts executed +system.cpu.iew.exec_refs 64080783 # number of memory reference insts executed +system.cpu.iew.exec_branches 11475005 # Number of branches executed +system.cpu.iew.exec_stores 12211635 # Number of stores executed +system.cpu.iew.exec_rate 0.254432 # Inst execution rate +system.cpu.iew.wb_sent 119890224 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85480536 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47031033 # num instructions producing a value +system.cpu.iew.wb_consumers 87879900 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179990 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535139 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179997 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535174 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18658160 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 534513 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 148959926 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.521933 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.510472 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18664214 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482302 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 534875 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 148983556 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521850 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.510275 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121529130 81.59% 81.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13302723 8.93% 90.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3899356 2.62% 93.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2115942 1.42% 94.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1939571 1.30% 95.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 978607 0.66% 96.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1596110 1.07% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 718014 0.48% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2880473 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121547303 81.58% 81.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13306218 8.93% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3902162 2.62% 93.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2119528 1.42% 94.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1937783 1.30% 95.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 976082 0.66% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1595601 1.07% 97.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718241 0.48% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2880638 1.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 148959926 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60456137 # Number of instructions committed -system.cpu.commit.committedOps 77747122 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 148983556 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60456059 # Number of instructions committed +system.cpu.commit.committedOps 77747065 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385736 # Number of memory references committed -system.cpu.commit.loads 15654008 # Number of loads committed -system.cpu.commit.membars 403573 # Number of memory barriers committed -system.cpu.commit.branches 9961077 # Number of branches committed +system.cpu.commit.refs 27385723 # Number of memory references committed +system.cpu.commit.loads 15653991 # Number of loads committed +system.cpu.commit.membars 403571 # Number of memory barriers committed +system.cpu.commit.branches 9961071 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68852562 # Number of committed integer instructions. -system.cpu.commit.function_calls 991208 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2880473 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68852511 # Number of committed integer instructions. +system.cpu.commit.function_calls 991207 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2880638 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 240636318 # The number of ROB reads -system.cpu.rob.rob_writes 195934369 # The number of ROB writes -system.cpu.timesIdled 1776906 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322885994 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575316115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60305756 # Number of Instructions Simulated -system.cpu.committedOps 77596741 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60305756 # Number of Instructions Simulated -system.cpu.cpi 7.874587 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.874587 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126991 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126991 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 547208469 # number of integer regfile reads -system.cpu.int_regfile_writes 87526188 # number of integer regfile writes -system.cpu.fp_regfile_reads 8624 # number of floating regfile reads -system.cpu.fp_regfile_writes 3008 # number of floating regfile writes -system.cpu.misc_regfile_reads 30165107 # number of misc regfile reads +system.cpu.rob.rob_reads 240665808 # The number of ROB reads +system.cpu.rob.rob_writes 195946920 # The number of ROB writes +system.cpu.timesIdled 1776652 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322877544 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575281578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60305678 # Number of Instructions Simulated +system.cpu.committedOps 77596684 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60305678 # Number of Instructions Simulated +system.cpu.cpi 7.874858 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.874858 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126986 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126986 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 547244882 # number of integer regfile reads +system.cpu.int_regfile_writes 87532645 # number of integer regfile writes +system.cpu.fp_regfile_reads 8511 # number of floating regfile reads +system.cpu.fp_regfile_writes 2972 # number of floating regfile writes +system.cpu.misc_regfile_reads 30145050 # number of misc regfile reads system.cpu.misc_regfile_writes 831837 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58889875 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658094 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658093 # Transaction distribution +system.cpu.toL2Bus.throughput 58898886 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658060 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658059 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607699 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2967 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246142 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246142 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961671 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796233 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31091 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128199 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7917194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62737088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85515993 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148510785 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148510785 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 194456 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128799181 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 607897 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2956 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2969 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246128 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246128 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961789 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796637 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30578 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 127052 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7916056 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62740736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85535129 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41644 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 210260 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148527769 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148527769 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 199672 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3129078659 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474440753 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474541718 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2550199081 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2550360089 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20321978 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20171491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74655295 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74593037 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980741 # number of replacements -system.cpu.icache.tags.tagsinuse 511.579116 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10449649 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981253 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.649291 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 980798 # number of replacements +system.cpu.icache.tags.tagsinuse 511.579102 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10457750 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981310 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.656928 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 6918450250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.579116 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.579102 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10449649 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10449649 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10449649 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10449649 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10449649 # number of overall hits -system.cpu.icache.overall_hits::total 10449649 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060761 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060761 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060761 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060761 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060761 # number of overall misses -system.cpu.icache.overall_misses::total 1060761 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14273214680 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14273214680 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14273214680 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14273214680 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14273214680 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14273214680 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11510410 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11510410 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11510410 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11510410 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11510410 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11510410 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092157 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092157 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092157 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092157 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092157 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092157 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13455.636736 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13455.636736 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13455.636736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13455.636736 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6677 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 10457750 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10457750 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10457750 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10457750 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10457750 # number of overall hits +system.cpu.icache.overall_hits::total 10457750 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1061214 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1061214 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1061214 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1061214 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1061214 # number of overall misses +system.cpu.icache.overall_misses::total 1061214 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14272429649 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14272429649 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14272429649 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14272429649 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14272429649 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14272429649 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11518964 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11518964 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11518964 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11518964 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11518964 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11518964 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092128 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092128 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092128 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092128 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092128 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092128 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13449.153186 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13449.153186 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13449.153186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13449.153186 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5990 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 323 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 322 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.671827 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.602484 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79476 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79476 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79476 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79476 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79476 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79476 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981285 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 981285 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 981285 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 981285 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981285 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981285 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587356987 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11587356987 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587356987 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11587356987 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587356987 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11587356987 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79868 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79868 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79868 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79868 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79868 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79868 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981346 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 981346 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 981346 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 981346 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 981346 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 981346 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11584683024 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11584683024 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11584683024 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11584683024 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11584683024 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11584683024 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8658250 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8658250 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8658250 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 8658250 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085252 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085252 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085252 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11808.350262 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11808.350262 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085194 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.085194 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.085194 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11804.891469 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11804.891469 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11804.891469 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11804.891469 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11804.891469 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11804.891469 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 64371 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51366.694603 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1888244 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129769 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.550810 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2490009951000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36925.668640 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 27.934134 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.003945 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8175.587712 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6237.500172 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563441 # Average percentage of cache occupancy +system.cpu.l2cache.tags.tagsinuse 51362.964424 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1886397 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129765 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.537025 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2489982729000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36926.272860 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 27.936805 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000373 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8173.687928 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6235.066458 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.563450 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000426 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124750 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.095177 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.783794 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53605 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10777 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 967799 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387031 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1419212 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607699 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607699 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 40 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 40 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112944 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112944 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 53605 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10777 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 967799 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 499975 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1532156 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 53605 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10777 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 967799 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 499975 # number of overall hits -system.cpu.l2cache.overall_hits::total 1532156 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12350 # number of ReadReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124721 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.095140 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.783737 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52523 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10409 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 967861 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387146 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1417939 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607897 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607897 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 112916 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112916 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 52523 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10409 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 967861 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 500062 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1530855 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 52523 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10409 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 967861 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 500062 # number of overall hits +system.cpu.l2cache.overall_hits::total 1530855 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 42 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12345 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 10721 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23115 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23110 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2915 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2915 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133198 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133198 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12350 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143919 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156313 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12350 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143919 # number of overall misses -system.cpu.l2cache.overall_misses::total 156313 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3352500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 233000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 906466500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 812441248 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1722493248 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 465980 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 465980 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10117185994 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10117185994 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3352500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 233000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 906466500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10929627242 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11839679242 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3352500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 233000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 906466500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10929627242 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11839679242 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53646 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10780 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 980149 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 397752 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1442327 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607699 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607699 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2955 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2955 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246142 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246142 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53646 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10780 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 980149 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 643894 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1688469 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53646 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10780 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 980149 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 643894 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1688469 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000764 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000278 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012600 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026954 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016026 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986464 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986464 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541143 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541143 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000764 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000278 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012600 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223513 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092577 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000764 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000278 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012600 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223513 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092577 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 81768.292683 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77666.666667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73398.097166 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75780.360787 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74518.418689 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 159.855918 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 159.855918 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75955.990285 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75955.990285 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81768.292683 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77666.666667 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73398.097166 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75942.907066 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75743.407407 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81768.292683 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77666.666667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73398.097166 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75942.907066 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75743.407407 # average overall miss latency +system.cpu.l2cache.ReadExReq_misses::cpu.data 133212 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133212 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 42 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12345 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143933 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156322 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 42 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 12345 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143933 # number of overall misses +system.cpu.l2cache.overall_misses::total 156322 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3605250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 158000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 903018500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 812779249 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1719560999 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 510978 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 510978 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10116159486 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10116159486 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3605250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 158000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 903018500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10928938735 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11835720485 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3605250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 158000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 903018500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10928938735 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11835720485 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52565 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10411 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 980206 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 397867 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1441049 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607897 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607897 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2956 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2956 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246128 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246128 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52565 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10411 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 980206 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 643995 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1687177 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52565 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10411 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 980206 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 643995 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1687177 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000799 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000192 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012594 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026946 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016037 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986130 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986130 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.230769 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541231 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541231 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000799 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000192 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012594 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223500 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.092653 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000799 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000192 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012594 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223500 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.092653 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85839.285714 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73148.521669 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75811.887790 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74407.658979 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 175.292624 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 175.292624 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75940.301820 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75940.301820 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85839.285714 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73148.521669 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75930.736766 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75713.722221 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85839.285714 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73148.521669 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75930.736766 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75713.722221 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1508,109 +1521,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59125 # number of writebacks -system.cpu.l2cache.writebacks::total 59125 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 59131 # number of writebacks +system.cpu.l2cache.writebacks::total 59131 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12339 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10656 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23039 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 42 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12334 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10655 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23033 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2915 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2915 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133198 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133198 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12339 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143854 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156237 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12339 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143854 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156237 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2846500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 196000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 750549750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 675500748 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1429092998 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133212 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133212 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 42 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12334 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143867 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156245 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 42 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12334 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143867 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156245 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3085750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 133500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 747187750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 675762749 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1426169749 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29153914 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29153914 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8456317006 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8456317006 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2846500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 196000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 750549750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9131817754 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9885410004 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2846500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 196000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 750549750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9131817754 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9885410004 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8455143514 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8455143514 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3085750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 133500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 747187750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9130906263 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9881313263 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3085750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 133500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 747187750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9130906263 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9881313263 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6187249 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166934965500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941152749 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17442637817 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17442637817 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166935059000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941246249 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17442653817 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17442653817 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6187249 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184377603317 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184383790566 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026791 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015973 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986464 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986464 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541143 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541143 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092532 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092532 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.437394 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63391.586712 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62029.298060 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184377712817 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184383900066 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026780 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015983 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986130 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986130 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541231 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541231 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223398 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092607 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223398 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092607 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60579.515972 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63422.125669 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61918.540746 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342710 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342710 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63486.816664 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63486.816664 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63471.335270 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63471.335270 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60579.515972 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63467.690735 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63242.428641 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73470.238095 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60579.515972 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63467.690735 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63242.428641 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1620,161 +1633,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643382 # number of replacements +system.cpu.dcache.tags.replacements 643483 # number of replacements system.cpu.dcache.tags.tagsinuse 511.993331 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21503755 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 643894 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.396421 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 21507621 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 643995 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.397186 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 42430250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13751955 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13751955 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258296 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258296 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242828 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242828 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21010251 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21010251 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21010251 # number of overall hits -system.cpu.dcache.overall_hits::total 21010251 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737736 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737736 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963735 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963735 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13555 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13555 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3701471 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3701471 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3701471 # number of overall misses -system.cpu.dcache.overall_misses::total 3701471 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10012711310 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10012711310 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 141368125836 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 141368125836 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185715250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 185715250 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 151380837146 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 151380837146 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 151380837146 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 151380837146 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14489691 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14489691 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222031 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222031 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256383 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256383 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24711722 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24711722 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24711722 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24711722 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050915 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050915 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289936 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289936 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052870 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052870 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149786 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149786 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149786 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149786 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13572.214600 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13572.214600 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47699.313817 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47699.313817 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13700.866839 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13700.866839 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40897.480257 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40897.480257 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33174 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 27500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2643 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.551646 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 96.491228 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13755484 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13755484 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258628 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258628 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242811 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242811 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247593 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247593 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21014112 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21014112 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21014112 # number of overall hits +system.cpu.dcache.overall_hits::total 21014112 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737297 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737297 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963410 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2963410 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13576 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13576 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3700707 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3700707 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3700707 # number of overall misses +system.cpu.dcache.overall_misses::total 3700707 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10005137822 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10005137822 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 141347559382 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 141347559382 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185728250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 185728250 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 206503 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 206503 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 151352697204 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 151352697204 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 151352697204 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 151352697204 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14492781 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14492781 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222038 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222038 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256387 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256387 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247606 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247606 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24714819 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24714819 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24714819 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24714819 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050873 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050873 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289904 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289904 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052951 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052951 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000053 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000053 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149736 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149736 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149736 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149736 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13570.023779 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13570.023779 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47697.604915 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47697.604915 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13680.631261 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13680.631261 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15884.846154 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15884.846154 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40898.319484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40898.319484 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32831 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 27415 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2635 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.459583 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 98.261649 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607699 # number of writebacks -system.cpu.dcache.writebacks::total 607699 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 352116 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 352116 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714717 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714717 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3066833 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3066833 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3066833 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3066833 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385620 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385620 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249018 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249018 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4970319128 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4970319128 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11601864538 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11601864538 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572183666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16572183666 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572183666 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16572183666 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328180000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328180000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841518267 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841518267 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169698267 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169698267 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026613 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026613 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024361 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024361 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047628 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047628 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.writebacks::writebacks 607897 # number of writebacks +system.cpu.dcache.writebacks::total 607897 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351582 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351582 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714405 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714405 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1345 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1345 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065987 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065987 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065987 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065987 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385715 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385715 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249005 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249005 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12231 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12231 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634720 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634720 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634720 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634720 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4972029375 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4972029375 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11600619783 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11600619783 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 180497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 180497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572649158 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16572649158 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572649158 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16572649158 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328280000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328280000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841536765 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841536765 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169816765 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169816765 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024360 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024360 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047705 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047705 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000053 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000053 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12889.163238 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12889.163238 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46590.465500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46590.465500 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11957.333552 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.333552 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12890.422657 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12890.422657 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46587.898970 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46587.898970 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11937.821928 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11937.821928 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13884.384615 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13884.384615 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1796,16 +1809,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1499087755049 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1499087755049 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1499067779549 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1499067779549 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83033 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index c314ac71a..745161c28 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -86,6 +94,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -119,6 +128,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -141,18 +151,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -163,6 +176,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -185,14 +199,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -211,18 +228,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=TimingSimpleCPU @@ -234,6 +254,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=Null @@ -255,17 +276,20 @@ workload= [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -284,17 +308,20 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu2] type=DerivO3CPU @@ -325,6 +352,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu2.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -387,6 +416,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -399,12 +429,14 @@ predType=tournament [system.cpu2.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu2.dtb.walker [system.cpu2.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system @@ -412,15 +444,18 @@ sys=system type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 +eventq_index=0 [system.cpu2.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu2.fuPool.FUList0.opList [system.cpu2.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -429,16 +464,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 [system.cpu2.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu2.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -447,22 +485,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 [system.cpu2.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu2.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu2.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -471,22 +513,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 [system.cpu2.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu2.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu2.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -495,10 +541,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList4.opList [system.cpu2.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -507,124 +555,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 [system.cpu2.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu2.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu2.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu2.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu2.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu2.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu2.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu2.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu2.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu2.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu2.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu2.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu2.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu2.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu2.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu2.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu2.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu2.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -633,10 +702,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList6.opList [system.cpu2.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -645,16 +716,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 [system.cpu2.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu2.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -663,16 +737,19 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu2.fuPool.FUList8.opList [system.cpu2.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 [system.cpu2.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -691,30 +768,36 @@ midr=890224640 [system.cpu2.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu2.itb.walker [system.cpu2.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu2.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -727,6 +810,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -749,6 +833,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -758,6 +843,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -780,6 +866,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -787,6 +874,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -798,6 +886,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -824,6 +913,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -835,19 +925,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -857,6 +951,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -866,6 +961,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -894,6 +990,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -903,8 +1000,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -916,6 +1045,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -931,6 +1061,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -945,6 +1077,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -954,6 +1087,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -975,8 +1109,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -985,6 +1121,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -995,6 +1132,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -1005,6 +1143,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -1015,6 +1154,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -1029,6 +1169,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -1042,6 +1183,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -1059,6 +1201,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -1071,6 +1214,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -1082,6 +1226,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -1092,6 +1237,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -1104,6 +1250,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -1117,6 +1264,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -1127,6 +1275,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -1137,6 +1286,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1147,6 +1297,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1159,6 +1310,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -1173,6 +1325,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -1185,6 +1338,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -1199,6 +1353,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1209,6 +1364,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1219,6 +1375,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1229,6 +1386,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1237,6 +1395,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1245,6 +1404,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1254,11 +1414,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 506582551..3eab7d5a6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,166 +1,182 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403658 # Number of seconds simulated -sim_ticks 2403657545000 # Number of ticks simulated -final_tick 2403657545000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403659 # Number of seconds simulated +sim_ticks 2403658742000 # Number of ticks simulated +final_tick 2403658742000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183148 # Simulator instruction rate (inst/s) -host_op_rate 235229 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7297160965 # Simulator tick rate (ticks/s) -host_mem_usage 427808 # Number of bytes of host memory used -host_seconds 329.40 # Real time elapsed on the host -sim_insts 60328152 # Number of instructions simulated -sim_ops 77483430 # Number of ops (including micro ops) simulated +host_inst_rate 141358 # Simulator instruction rate (inst/s) +host_op_rate 181555 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5632122143 # Simulator tick rate (ticks/s) +host_mem_usage 447420 # Number of bytes of host memory used +host_seconds 426.78 # Real time elapsed on the host +sim_insts 60328128 # Number of instructions simulated +sim_ops 77483556 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 512416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7048656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 512480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7049296 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 64128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 675392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 187392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1353632 # Number of bytes read from this memory -system.physmem.bytes_read::total 124661648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 512416 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 674944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 186496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1353888 # Number of bytes read from this memory +system.physmem.bytes_read::total 124661072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 512480 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 64128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 187392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 763936 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3744384 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1298192 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu2.inst 186496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 763104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3743872 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1298256 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 159304 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1558320 # Number of bytes written to this memory -system.physmem.bytes_written::total 6760200 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1558256 # Number of bytes written to this memory +system.physmem.bytes_written::total 6759688 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14209 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14210 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110179 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 1002 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10553 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2928 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 21158 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512418 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58506 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 324548 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 10546 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2914 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 21162 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512409 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58498 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 324564 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 39826 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 389580 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812460 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47768482 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::cpu2.data 389564 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812452 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47768458 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 213182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2932471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2932736 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 26679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 280985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 77961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 563155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51863315 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213182 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 280799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 77588 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 563261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51863049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213208 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 26679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 77961 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317822 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1557786 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 540090 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 77588 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1557572 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 540117 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 66276 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 648312 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2812464 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1557786 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47768482 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 648285 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2812249 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1557572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47768458 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3472561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3472852 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 26679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 347261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 77961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1211467 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54675779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13467317 # Number of read requests accepted -system.physmem.writeReqs 446508 # Number of write requests accepted -system.physmem.readBursts 13467317 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 446508 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 861908288 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu1.data 347074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 186 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 77588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1211546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54675299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13477345 # Number of read requests accepted +system.physmem.writeReqs 446482 # Number of write requests accepted +system.physmem.readBursts 13477345 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 446482 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 862550080 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 2866432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 109734624 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2812152 # Total written bytes from the system interface side +system.physmem.bytesWritten 2865536 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109813728 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2811448 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 401719 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2372 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 837719 # Per bank write bursts -system.physmem.perBankRdBursts::1 837389 # Per bank write bursts -system.physmem.perBankRdBursts::2 837556 # Per bank write bursts -system.physmem.perBankRdBursts::3 837999 # Per bank write bursts -system.physmem.perBankRdBursts::4 838842 # Per bank write bursts -system.physmem.perBankRdBursts::5 838880 # Per bank write bursts -system.physmem.perBankRdBursts::6 838796 # Per bank write bursts -system.physmem.perBankRdBursts::7 839742 # Per bank write bursts -system.physmem.perBankRdBursts::8 840911 # Per bank write bursts -system.physmem.perBankRdBursts::9 843323 # Per bank write bursts -system.physmem.perBankRdBursts::10 844015 # Per bank write bursts -system.physmem.perBankRdBursts::11 845500 # Per bank write bursts -system.physmem.perBankRdBursts::12 847242 # Per bank write bursts -system.physmem.perBankRdBursts::13 846993 # Per bank write bursts -system.physmem.perBankRdBursts::14 845867 # Per bank write bursts -system.physmem.perBankRdBursts::15 846543 # Per bank write bursts -system.physmem.perBankWrBursts::0 2729 # Per bank write bursts -system.physmem.perBankWrBursts::1 2587 # Per bank write bursts -system.physmem.perBankWrBursts::2 2574 # Per bank write bursts -system.physmem.perBankWrBursts::3 3045 # Per bank write bursts -system.physmem.perBankWrBursts::4 3468 # Per bank write bursts -system.physmem.perBankWrBursts::5 3206 # Per bank write bursts -system.physmem.perBankWrBursts::6 2544 # Per bank write bursts -system.physmem.perBankWrBursts::7 2321 # Per bank write bursts -system.physmem.perBankWrBursts::8 2236 # Per bank write bursts -system.physmem.perBankWrBursts::9 2427 # Per bank write bursts -system.physmem.perBankWrBursts::10 2367 # Per bank write bursts -system.physmem.perBankWrBursts::11 2798 # Per bank write bursts -system.physmem.perBankWrBursts::12 3813 # Per bank write bursts -system.physmem.perBankWrBursts::13 3444 # Per bank write bursts -system.physmem.perBankWrBursts::14 2680 # Per bank write bursts -system.physmem.perBankWrBursts::15 2549 # Per bank write bursts +system.physmem.mergedWrBursts 401707 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2370 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 837716 # Per bank write bursts +system.physmem.perBankRdBursts::1 837382 # Per bank write bursts +system.physmem.perBankRdBursts::2 837561 # Per bank write bursts +system.physmem.perBankRdBursts::3 838016 # Per bank write bursts +system.physmem.perBankRdBursts::4 839132 # Per bank write bursts +system.physmem.perBankRdBursts::5 839847 # Per bank write bursts +system.physmem.perBankRdBursts::6 839973 # Per bank write bursts +system.physmem.perBankRdBursts::7 841200 # Per bank write bursts +system.physmem.perBankRdBursts::8 842679 # Per bank write bursts +system.physmem.perBankRdBursts::9 845377 # Per bank write bursts +system.physmem.perBankRdBursts::10 845421 # Per bank write bursts +system.physmem.perBankRdBursts::11 845910 # Per bank write bursts +system.physmem.perBankRdBursts::12 847235 # Per bank write bursts +system.physmem.perBankRdBursts::13 846991 # Per bank write bursts +system.physmem.perBankRdBursts::14 846262 # Per bank write bursts +system.physmem.perBankRdBursts::15 846643 # Per bank write bursts +system.physmem.perBankWrBursts::0 2727 # Per bank write bursts +system.physmem.perBankWrBursts::1 2580 # Per bank write bursts +system.physmem.perBankWrBursts::2 2569 # Per bank write bursts +system.physmem.perBankWrBursts::3 3046 # Per bank write bursts +system.physmem.perBankWrBursts::4 3472 # Per bank write bursts +system.physmem.perBankWrBursts::5 3199 # Per bank write bursts +system.physmem.perBankWrBursts::6 2543 # Per bank write bursts +system.physmem.perBankWrBursts::7 2318 # Per bank write bursts +system.physmem.perBankWrBursts::8 2233 # Per bank write bursts +system.physmem.perBankWrBursts::9 2426 # Per bank write bursts +system.physmem.perBankWrBursts::10 2368 # Per bank write bursts +system.physmem.perBankWrBursts::11 2824 # Per bank write bursts +system.physmem.perBankWrBursts::12 3814 # Per bank write bursts +system.physmem.perBankWrBursts::13 3447 # Per bank write bursts +system.physmem.perBankWrBursts::14 2652 # Per bank write bursts +system.physmem.perBankWrBursts::15 2556 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2402622305000 # Total gap between requests +system.physmem.totGap 2402623562000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 8 # Read request sizes (log2) -system.physmem.readPktSize::3 13431664 # Read request sizes (log2) +system.physmem.readPktSize::3 13441712 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 35645 # Read request sizes (log2) +system.physmem.readPktSize::6 35625 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 429406 # Write request sizes (log2) +system.physmem.writePktSize::2 429390 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 17102 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 965936 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 943404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 937737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3274872 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2367219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2366833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2384991 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 47923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 55146 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17092 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 971418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 948778 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 943230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3279616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2365953 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2365403 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2381873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 45829 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 51923 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 17633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 17621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 17612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 17600 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 17597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 17582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 17632 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 17623 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 17610 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 17603 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 17596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -176,30 +192,30 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2024 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2015 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 2021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 26 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -208,304 +224,298 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48451 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 17848.429795 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 3200.071202 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 18346.519598 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 8608 17.77% 17.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 4824 9.96% 27.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 1006 2.08% 29.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 654 1.35% 31.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 399 0.82% 31.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 406 0.84% 32.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 283 0.58% 33.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 297 0.61% 34.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 176 0.36% 34.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 170 0.35% 34.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 172 0.35% 35.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 155 0.32% 35.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 77 0.16% 35.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 80 0.17% 35.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 48 0.10% 35.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 416 0.86% 36.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 18 0.04% 36.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 23 0.05% 36.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 23 0.05% 36.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 108 0.22% 37.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 17 0.04% 37.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 165 0.34% 37.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 12 0.02% 37.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 112 0.23% 37.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 15 0.03% 37.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 32 0.07% 37.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 7 0.01% 37.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 140 0.29% 38.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 6 0.01% 38.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 13 0.03% 38.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 8 0.02% 38.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 455 0.94% 39.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 3 0.01% 39.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 12 0.02% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 2 0.00% 39.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 72 0.15% 39.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 6 0.01% 39.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 4 0.01% 39.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 2 0.00% 39.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 5 0.01% 39.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 6 0.01% 39.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 3 0.01% 39.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 5 0.01% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 10 0.02% 39.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 5 0.01% 39.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 8 0.02% 39.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 2 0.00% 39.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 505 1.04% 40.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 5 0.01% 40.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 5 0.01% 40.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 5 0.01% 40.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 65 0.13% 40.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 6 0.01% 40.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 5 0.01% 40.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 9 0.02% 40.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 15 0.03% 40.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 3 0.01% 40.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 4 0.01% 40.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 6 0.01% 40.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 66 0.14% 40.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 4 0.01% 40.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 6 0.01% 40.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 3 0.01% 40.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 327 0.67% 41.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 5 0.01% 41.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 8 0.02% 41.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 2 0.00% 41.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 130 0.27% 41.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 6 0.01% 41.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 4 0.01% 41.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 3 0.01% 41.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 68 0.14% 41.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 3 0.01% 41.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 2 0.00% 41.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 5 0.01% 41.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 4 0.01% 42.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 4 0.01% 42.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 4 0.01% 42.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 7 0.01% 42.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 258 0.53% 42.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 5 0.01% 42.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 4 0.01% 42.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 3 0.01% 42.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 88 0.18% 42.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 3 0.01% 42.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 8 0.02% 42.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 3 0.01% 42.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 92 0.19% 42.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 4 0.01% 43.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 7 0.01% 43.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 2 0.00% 43.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 102 0.21% 43.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 2 0.00% 43.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 3 0.01% 43.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 10 0.02% 43.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 481 0.99% 44.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 2 0.00% 44.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 3 0.01% 44.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 1 0.00% 44.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 1 0.00% 44.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 3 0.01% 44.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 2 0.00% 44.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 67 0.14% 44.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 5 0.01% 44.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 6 0.01% 44.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 131 0.27% 44.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 1 0.00% 44.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 1 0.00% 44.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 3 0.01% 44.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 72 0.15% 44.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 1 0.00% 44.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 2 0.00% 44.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 13 0.03% 44.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 133 0.27% 45.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 66 0.14% 45.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 64 0.13% 45.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 385 0.79% 46.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 65 0.13% 46.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 65 0.13% 46.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 128 0.26% 46.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 73 0.15% 46.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 128 0.26% 47.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 64 0.13% 47.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 1 0.00% 47.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 478 0.99% 48.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 63 0.13% 48.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10631 1 0.00% 48.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 89 0.18% 48.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 86 0.18% 48.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 257 0.53% 49.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 1 0.00% 49.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 65 0.13% 49.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 128 0.26% 49.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 320 0.66% 50.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 64 0.13% 50.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 14 0.03% 50.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12999 1 0.00% 50.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 64 0.13% 50.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 499 1.03% 51.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 64 0.13% 51.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 442 0.91% 52.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 128 0.26% 53.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 66 0.14% 53.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 72 0.15% 53.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 362 0.75% 54.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 2 0.00% 54.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 6 0.01% 54.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 781 1.61% 55.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 7 0.01% 55.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 1 0.00% 55.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17031 1 0.00% 55.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 1 0.00% 55.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 362 0.75% 56.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 72 0.15% 56.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 64 0.13% 56.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 128 0.26% 56.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 1 0.00% 57.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 1 0.00% 57.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 442 0.91% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 64 0.13% 58.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 1 0.00% 58.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 499 1.03% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 64 0.13% 59.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 12 0.02% 59.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 66 0.14% 59.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 320 0.66% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 128 0.26% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 64 0.13% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 256 0.53% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 85 0.18% 61.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 1 0.00% 61.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 87 0.18% 61.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 64 0.13% 61.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 478 0.99% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 67 0.14% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 128 0.26% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 71 0.15% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 129 0.27% 63.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 64 0.13% 63.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 64 0.13% 63.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 384 0.79% 64.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 64 0.13% 64.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 64 0.13% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 129 0.27% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 70 0.14% 64.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 128 0.26% 65.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26048-26055 1 0.00% 65.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 66 0.14% 65.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 480 0.99% 66.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 64 0.13% 66.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 89 0.18% 66.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 86 0.18% 66.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 256 0.53% 67.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 1 0.00% 67.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 65 0.13% 67.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28288-28295 1 0.00% 67.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 127 0.26% 67.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 320 0.66% 68.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 65 0.13% 68.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 13 0.03% 68.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 64 0.13% 68.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 497 1.03% 69.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 1 0.00% 69.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 64 0.13% 69.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 442 0.91% 70.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30912-30919 1 0.00% 70.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 129 0.27% 71.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 65 0.13% 71.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 72 0.15% 71.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 362 0.75% 72.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 1 0.00% 72.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32320-32327 1 0.00% 72.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 6 0.01% 72.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 778 1.61% 73.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 5 0.01% 73.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33216-33223 1 0.00% 73.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 2 0.00% 73.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 362 0.75% 74.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 72 0.15% 74.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 66 0.14% 74.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 128 0.26% 75.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34688-34695 1 0.00% 75.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 443 0.91% 75.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 64 0.13% 76.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35712-35719 1 0.00% 76.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 499 1.03% 77.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 64 0.13% 77.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 13 0.03% 77.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 65 0.13% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 321 0.66% 78.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 127 0.26% 78.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37248-37255 1 0.00% 78.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 64 0.13% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 1 0.00% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 257 0.53% 79.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38016-38023 1 0.00% 79.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 86 0.18% 79.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 89 0.18% 79.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 65 0.13% 79.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 479 0.99% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 65 0.13% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39488-39495 1 0.00% 80.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 128 0.26% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 71 0.15% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 128 0.26% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 64 0.13% 81.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 64 0.13% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 384 0.79% 82.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 64 0.13% 82.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 64 0.13% 82.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 129 0.27% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 71 0.15% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 128 0.26% 83.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 67 0.14% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 477 0.98% 84.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 64 0.13% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 87 0.18% 84.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 1 0.00% 84.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 84 0.17% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 256 0.53% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 1 0.00% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 64 0.13% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 128 0.26% 85.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 320 0.66% 86.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 65 0.13% 86.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 12 0.02% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 64 0.13% 86.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 498 1.03% 87.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 1 0.00% 87.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 64 0.13% 87.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 443 0.91% 88.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 128 0.26% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 66 0.14% 89.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 72 0.15% 89.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 362 0.75% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 2 0.00% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48512-48519 2 0.00% 90.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 1 0.00% 90.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 7 0.01% 90.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 1 0.00% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 1 0.00% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 4749 9.80% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 48451 # Bytes accessed per row activation -system.physmem.totQLat 326245474250 # Total ticks spent queuing -system.physmem.totMemAccLat 407559786750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 67336585000 # Total ticks spent in databus transfers -system.physmem.totBankLat 13977727500 # Total ticks spent accessing banks -system.physmem.avgQLat 24224.98 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1037.90 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 48550 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 17825.239135 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 3190.498487 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 18342.849091 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 8610 17.73% 17.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 4856 10.00% 27.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 981 2.02% 29.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 733 1.51% 31.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 427 0.88% 32.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 370 0.76% 32.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 272 0.56% 33.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 308 0.63% 34.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 164 0.34% 34.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 164 0.34% 34.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 166 0.34% 35.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 231 0.48% 35.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 82 0.17% 35.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 88 0.18% 35.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 37 0.08% 36.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 306 0.63% 36.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 22 0.05% 36.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 33 0.07% 36.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 21 0.04% 36.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 99 0.20% 37.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 20 0.04% 37.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 170 0.35% 37.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 13 0.03% 37.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 137 0.28% 37.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 12 0.02% 37.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 29 0.06% 37.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 10 0.02% 37.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 139 0.29% 38.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 7 0.01% 38.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 11 0.02% 38.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 8 0.02% 38.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 378 0.78% 38.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 6 0.01% 38.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 7 0.01% 38.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 7 0.01% 38.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 70 0.14% 39.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 6 0.01% 39.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 4 0.01% 39.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 3 0.01% 39.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 71 0.15% 39.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 5 0.01% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 4 0.01% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 4 0.01% 39.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 9 0.02% 39.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 7 0.01% 39.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 7 0.01% 39.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 5 0.01% 39.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 411 0.85% 40.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 5 0.01% 40.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 4 0.01% 40.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 1 0.00% 40.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 132 0.27% 40.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 3 0.01% 40.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 6 0.01% 40.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 7 0.01% 40.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 67 0.14% 40.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 5 0.01% 40.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 5 0.01% 40.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 3 0.01% 40.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 73 0.15% 40.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 4 0.01% 40.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 6 0.01% 40.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 384 0.79% 41.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 7 0.01% 41.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 7 0.01% 41.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 3 0.01% 41.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 131 0.27% 41.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 8 0.02% 42.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 2 0.00% 42.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 2 0.00% 42.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 68 0.14% 42.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 2 0.00% 42.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 2 0.00% 42.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 5 0.01% 42.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 34 0.07% 42.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 2 0.00% 42.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 6 0.01% 42.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 4 0.01% 42.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 263 0.54% 42.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 1 0.00% 42.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 3 0.01% 42.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 5 0.01% 42.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 131 0.27% 43.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 4 0.01% 43.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 9 0.02% 43.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 3 0.01% 43.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 70 0.14% 43.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 3 0.01% 43.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 4 0.01% 43.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 5 0.01% 43.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 103 0.21% 43.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 1 0.00% 43.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 4 0.01% 43.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 9 0.02% 43.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 323 0.67% 44.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 3 0.01% 44.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 1 0.00% 44.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 4 0.01% 44.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 7 0.01% 44.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 82 0.17% 44.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 1 0.00% 44.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 8 0.02% 44.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 4 0.01% 44.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 3 0.01% 44.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 4 0.01% 44.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 2 0.00% 44.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 292 0.60% 45.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 2 0.00% 45.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 14 0.03% 45.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 4 0.01% 45.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 128 0.26% 45.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 65 0.13% 45.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 1 0.00% 45.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 415 0.85% 46.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 65 0.13% 46.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 128 0.26% 46.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 291 0.60% 47.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 1 0.00% 47.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 81 0.17% 47.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 3 0.01% 47.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 320 0.66% 48.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 64 0.13% 48.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 64 0.13% 48.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 128 0.26% 48.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 256 0.53% 49.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 32 0.07% 49.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 64 0.13% 49.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 128 0.26% 49.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 375 0.77% 50.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 68 0.14% 50.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12615 1 0.00% 50.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 65 0.13% 50.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 125 0.26% 50.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13127 1 0.00% 51.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 408 0.84% 51.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 1 0.00% 51.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 64 0.13% 51.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 64 0.13% 52.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 364 0.75% 52.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14407 1 0.00% 52.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 128 0.26% 53.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 98 0.20% 53.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 70 0.14% 53.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 256 0.53% 53.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 65 0.13% 54.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 71 0.15% 54.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 644 1.33% 55.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 73 0.15% 55.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16839 1 0.00% 55.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 65 0.13% 55.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 256 0.53% 56.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 68 0.14% 56.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 96 0.20% 56.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 128 0.26% 57.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 364 0.75% 57.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 64 0.13% 57.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 64 0.13% 58.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19008-19015 1 0.00% 58.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 1 0.00% 58.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 407 0.84% 58.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 125 0.26% 59.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 65 0.13% 59.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 70 0.14% 59.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20288-20295 1 0.00% 59.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 376 0.77% 60.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 127 0.26% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 64 0.13% 60.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 29 0.06% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 256 0.53% 61.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 128 0.26% 61.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 64 0.13% 61.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 65 0.13% 61.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 320 0.66% 62.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 3 0.01% 62.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 82 0.17% 62.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 292 0.60% 63.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 129 0.27% 63.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 64 0.13% 63.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 414 0.85% 64.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 65 0.13% 64.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 129 0.27% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 291 0.60% 65.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25735 1 0.00% 65.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 80 0.16% 65.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 4 0.01% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 320 0.66% 66.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 65 0.13% 66.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 64 0.13% 66.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 128 0.26% 66.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 256 0.53% 67.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 32 0.07% 67.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 65 0.13% 67.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 128 0.26% 67.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 377 0.78% 68.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 68 0.14% 68.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 1 0.00% 68.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 65 0.13% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 125 0.26% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 410 0.84% 69.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 1 0.00% 69.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 64 0.13% 70.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 65 0.13% 70.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 363 0.75% 70.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 129 0.27% 71.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 96 0.20% 71.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 68 0.14% 71.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 256 0.53% 72.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 64 0.13% 72.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 1 0.00% 72.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 72 0.15% 72.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 642 1.32% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 72 0.15% 73.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 1 0.00% 73.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 63 0.13% 73.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 256 0.53% 74.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 68 0.14% 74.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 96 0.20% 74.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 128 0.26% 75.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 363 0.75% 75.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 64 0.13% 75.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 64 0.13% 76.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 1 0.00% 76.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 410 0.84% 76.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 125 0.26% 77.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 65 0.13% 77.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 68 0.14% 77.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 376 0.77% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 128 0.26% 78.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 65 0.13% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 32 0.07% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 256 0.53% 79.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 128 0.26% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 64 0.13% 79.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 65 0.13% 79.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 320 0.66% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 4 0.01% 80.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 80 0.16% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 1 0.00% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 292 0.60% 81.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 129 0.27% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 65 0.13% 81.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 413 0.85% 82.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 64 0.13% 82.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 129 0.27% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 292 0.60% 83.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 82 0.17% 83.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 3 0.01% 83.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 320 0.66% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 65 0.13% 84.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 65 0.13% 84.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 128 0.26% 84.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 256 0.53% 85.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 1 0.00% 85.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 29 0.06% 85.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 64 0.13% 85.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 127 0.26% 85.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 375 0.77% 86.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 70 0.14% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45376-45383 1 0.00% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 64 0.13% 86.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 125 0.26% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 406 0.84% 87.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46528-46535 1 0.00% 87.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 64 0.13% 88.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 64 0.13% 88.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 364 0.75% 88.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 128 0.26% 89.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 96 0.20% 89.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 69 0.14% 89.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 258 0.53% 90.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 67 0.14% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 71 0.15% 90.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 1 0.00% 90.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 2 0.00% 90.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 4686 9.65% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 48550 # Bytes accessed per row activation +system.physmem.totQLat 326412969750 # Total ticks spent queuing +system.physmem.totMemAccLat 407861489750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67386725000 # Total ticks spent in databus transfers +system.physmem.totBankLat 14061795000 # Total ticks spent accessing banks +system.physmem.avgQLat 24219.38 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1043.37 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30262.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 358.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30262.75 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 358.85 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.19 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 45.65 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 45.69 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.81 # Data bus utilization in percentage @@ -513,328 +523,330 @@ system.physmem.busUtilRead 2.80 # Da system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.37 # Average write queue length when enqueuing -system.physmem.readRowHits 13424164 # Number of row buffer hits during reads -system.physmem.writeRowHits 39490 # Number of row buffer hits during writes +system.physmem.readRowHits 13434104 # Number of row buffer hits during reads +system.physmem.writeRowHits 39465 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 88.17 # Row buffer hit rate for writes -system.physmem.avgGap 172678.78 # Average gap between requests +system.physmem.writeRowHitRate 88.14 # Row buffer hit rate for writes +system.physmem.avgGap 172554.83 # Average gap between requests system.physmem.pageHitRate 99.64 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.76 # Percentage of time for which DRAM has all the banks in precharge state -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55673060 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13803640 # Transaction distribution -system.membus.trans_dist::ReadResp 13803640 # Transaction distribution -system.membus.trans_dist::WriteReq 432247 # Transaction distribution -system.membus.trans_dist::WriteResp 432247 # Transaction distribution -system.membus.trans_dist::Writeback 17102 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2372 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2372 # Transaction distribution -system.membus.trans_dist::ReadExReq 28053 # Transaction distribution -system.membus.trans_dist::ReadExResp 28053 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 734214 # Packet count per connected master and slave (bytes) +system.physmem.prechargeAllPercent 0.75 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 55672581 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13813538 # Transaction distribution +system.membus.trans_dist::ReadResp 13813538 # Transaction distribution +system.membus.trans_dist::WriteReq 432230 # Transaction distribution +system.membus.trans_dist::WriteResp 432230 # Transaction distribution +system.membus.trans_dist::Writeback 17092 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2370 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2370 # Transaction distribution +system.membus.trans_dist::ReadExReq 28046 # Transaction distribution +system.membus.trans_dist::ReadExResp 28046 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 733938 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 220 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951964 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1686398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26863328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26863328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28549726 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 738102 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951878 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1686036 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26883424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26883424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28569460 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 737821 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5093464 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5832006 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107453312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107453312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113285318 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133818970 # Total data (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5091480 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5829741 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107533696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107533696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113363437 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133817886 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 417653000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 418359500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 209500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 204500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14595653500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 14607428500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1597948868 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1598779620 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 30334798000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 30355600750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 63262 # number of replacements -system.l2c.tags.tagsinuse 50391.923695 # Cycle average of tags in use -system.l2c.tags.total_refs 1749292 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128659 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.596344 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375568862000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36846.357046 # Average occupied blocks per requestor +system.l2c.tags.replacements 63253 # number of replacements +system.l2c.tags.tagsinuse 50392.264505 # Cycle average of tags in use +system.l2c.tags.total_refs 1749443 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128649 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.598574 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375574111000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36861.205107 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5224.016956 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3834.498559 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5227.235315 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3840.097341 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993317 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 503.830830 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 691.484420 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.832714 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1696.766805 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1584.142905 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562231 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 502.876093 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 689.542033 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.851035 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.974650 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1682.063126 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1580.426346 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562457 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079712 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058510 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079761 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.058595 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007688 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010551 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000150 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.025891 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.024172 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768920 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 8708 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3160 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 467622 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 176862 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2604 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1190 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 130139 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 64269 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18599 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4205 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 281217 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 132179 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1290754 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597747 # number of Writeback hits -system.l2c.Writeback_hits::total 597747 # number of Writeback hits +system.l2c.tags.occ_percent::cpu1.inst 0.007673 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010522 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000105 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.025666 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.024115 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768925 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 8706 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3165 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 467858 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 176725 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2609 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1184 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 130025 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 64311 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18749 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4292 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 281381 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 132168 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1291173 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597611 # number of Writeback hits +system.l2c.Writeback_hits::total 597611 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 14 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 32 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 61947 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 18483 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33173 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113603 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8708 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3160 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 467622 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 238809 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2604 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1190 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 130139 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 82752 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 18599 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 4205 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 281217 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 165352 # number of demand (read+write) hits -system.l2c.demand_hits::total 1404357 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8708 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3160 # number of overall hits -system.l2c.overall_hits::cpu0.inst 467622 # number of overall hits -system.l2c.overall_hits::cpu0.data 238809 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 2604 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1190 # number of overall hits -system.l2c.overall_hits::cpu1.inst 130139 # number of overall hits -system.l2c.overall_hits::cpu1.data 82752 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 18599 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 4205 # number of overall hits -system.l2c.overall_hits::cpu2.inst 281217 # number of overall hits -system.l2c.overall_hits::cpu2.data 165352 # number of overall hits -system.l2c.overall_hits::total 1404357 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 61949 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 18453 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 33219 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113621 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 8706 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3165 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 467858 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 238674 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 2609 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1184 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 130025 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 82764 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 18749 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 4292 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 281381 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 165387 # number of demand (read+write) hits +system.l2c.demand_hits::total 1404794 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 8706 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3165 # number of overall hits +system.l2c.overall_hits::cpu0.inst 467858 # number of overall hits +system.l2c.overall_hits::cpu0.data 238674 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 2609 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1184 # number of overall hits +system.l2c.overall_hits::cpu1.inst 130025 # number of overall hits +system.l2c.overall_hits::cpu1.data 82764 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 18749 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 4292 # number of overall hits +system.l2c.overall_hits::cpu2.inst 281381 # number of overall hits +system.l2c.overall_hits::cpu2.data 165387 # number of overall hits +system.l2c.overall_hits::total 1404794 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7593 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6471 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7594 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6477 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 1002 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1122 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 2929 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 2540 # number of ReadReq misses -system.l2c.ReadReq_misses::total 21672 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1412 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu1.data 1121 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 2915 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 2544 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21665 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1413 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 467 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu2.data 1028 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2907 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2908 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 104452 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9703 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 19227 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133382 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9697 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 19224 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133373 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7593 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 110923 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7594 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 110929 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 1002 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10825 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 11 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 2929 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 21767 # number of demand (read+write) misses -system.l2c.demand_misses::total 155054 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10818 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 7 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 2915 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 21768 # number of demand (read+write) misses +system.l2c.demand_misses::total 155038 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7593 # number of overall misses -system.l2c.overall_misses::cpu0.data 110923 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7594 # number of overall misses +system.l2c.overall_misses::cpu0.data 110929 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu1.inst 1002 # number of overall misses -system.l2c.overall_misses::cpu1.data 10825 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 11 # number of overall misses -system.l2c.overall_misses::cpu2.inst 2929 # number of overall misses -system.l2c.overall_misses::cpu2.data 21767 # number of overall misses -system.l2c.overall_misses::total 155054 # number of overall misses +system.l2c.overall_misses::cpu1.data 10818 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 7 # number of overall misses +system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu2.inst 2915 # number of overall misses +system.l2c.overall_misses::cpu2.data 21768 # number of overall misses +system.l2c.overall_misses::total 155038 # number of overall misses system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 71455000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 85190000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 823000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 219607750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 196366750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 573517000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 72874750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 86399250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 538750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.itb.walker 75000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 221844500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 200958749 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 582765499 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 93996 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 92996 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 186992 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 728546978 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1457919895 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2186466873 # number of ReadExReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 162493 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 256489 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 729445478 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1446208147 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2175653625 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 74500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 71455000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 813736978 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 823000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 219607750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1654286645 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2759983873 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 72874750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 815844728 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 538750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.itb.walker 75000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 221844500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1647166896 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2758419124 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 74500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 71455000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 813736978 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 823000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 219607750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1654286645 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2759983873 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 8709 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3162 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 475215 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 183333 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 2605 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1190 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 131141 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 65391 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 18610 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 4205 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 284146 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 134719 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1312426 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 597747 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 597747 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1426 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu1.inst 72874750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 815844728 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 538750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.itb.walker 75000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 221844500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1647166896 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2758419124 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 8707 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3167 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 475452 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 183202 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 2610 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1184 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 131027 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 65432 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 18756 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 4293 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 284296 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 134712 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1312838 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 597611 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 597611 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1427 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 471 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 1042 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 1041 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2939 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu2.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 166399 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 28186 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 52400 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246985 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8709 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3162 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 475215 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 349732 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 2605 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1190 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 131141 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 93577 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 18610 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 4205 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 284146 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 187119 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1559411 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8709 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3162 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 475215 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 349732 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 2605 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1190 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 131141 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 93577 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 18610 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 4205 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 284146 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 187119 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1559411 # number of overall (read+write) accesses +system.l2c.ReadExReq_accesses::cpu0.data 166401 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 28150 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 52443 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246994 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8707 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3167 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 475452 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 349603 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 2610 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1184 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 131027 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 93582 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 18756 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 4293 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 284296 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 187155 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1559832 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8707 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3167 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 475452 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 349603 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 2610 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1184 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 131027 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 93582 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 18756 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 4293 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 284296 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 187155 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1559832 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000115 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000633 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015978 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.035296 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000384 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.007641 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.017158 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000591 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.010308 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.018854 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016513 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990182 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000632 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015972 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.035354 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000383 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.007647 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.017132 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000373 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000233 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.010253 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.018885 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016502 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990189 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991507 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.986564 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.989112 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.627720 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.344249 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.366927 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.540041 # miss rate for ReadExReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.987512 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.989452 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.627713 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.344476 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.366569 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.539985 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000115 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000633 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015978 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.317166 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000384 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.007641 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.115680 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000591 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.010308 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.116327 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.099431 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000632 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015972 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.317300 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000383 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.007647 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.115599 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000373 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.itb.walker 0.000233 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.010253 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.116310 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.099394 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000115 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000633 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015978 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.317166 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000384 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.007641 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.115680 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000591 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.010308 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.116327 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.099431 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000632 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015972 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.317300 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000383 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.007647 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.115599 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000373 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.itb.walker 0.000233 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.010253 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.116310 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.099394 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71312.375250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 75926.916221 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 74818.181818 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 74977.039945 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 77309.744094 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 26463.501292 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72729.291417 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 77073.371989 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 76964.285714 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 75000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 76104.459691 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 78993.218947 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 26898.938334 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 201.276231 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 90.463035 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 64.324733 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75084.713800 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 75826.696573 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 16392.518278 # average ReadExReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 158.067121 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 88.201169 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75223.829844 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 75229.304359 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 16312.549204 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 71312.375250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 75172.007206 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 74818.181818 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 74977.039945 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 75999.753985 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 17800.146226 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 72729.291417 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 75415.486042 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 76964.285714 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.itb.walker 75000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 76104.459691 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 75669.188534 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 17791.890530 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 71312.375250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 75172.007206 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 74818.181818 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 74977.039945 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 75999.753985 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 17800.146226 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 72729.291417 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 75415.486042 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 76964.285714 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.itb.walker 75000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 76104.459691 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 75669.188534 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 17791.890530 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -843,134 +855,146 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 58506 # number of writebacks -system.l2c.writebacks::total 58506 # number of writebacks +system.l2c.writebacks::writebacks 58498 # number of writebacks +system.l2c.writebacks::total 58498 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu2.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.data 12 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.data 11 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu2.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.data 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.data 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu2.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.data 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 13 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.data 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.inst 1002 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1122 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 11 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 2928 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 2528 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 7592 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1121 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 7 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 2914 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 2533 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 7579 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1.data 467 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu2.data 1028 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 1495 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 9703 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 19227 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 28930 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 9697 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 19224 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 28921 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 1002 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 10825 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 11 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 2928 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 21755 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 36522 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 10818 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 7 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 2914 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 21757 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 36500 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 1002 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 10825 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 11 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 2928 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 21755 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 36522 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 10818 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 7 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 2914 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 21757 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 36500 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 58877500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 71259000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 687500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 182826500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 164184000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 477897000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 60159250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 72443750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 451250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 185254250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 168538249 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 486971749 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4670967 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10281528 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 14952495 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 606681022 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1218059105 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1824740127 # number of ReadExReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10281028 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 14951995 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 606663522 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1206372353 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1813035875 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 58877500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 677940022 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 687500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 182826500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 1382243105 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 2302637127 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 60159250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 679107272 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 451250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 185254250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1374910602 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2300007624 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 58877500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 677940022 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 687500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 182826500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 1382243105 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 2302637127 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25057289000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26363515500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 51420804500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 935323010 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 8517824000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 9453147010 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25992612010 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34881339500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 60873951510 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007641 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017158 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000591 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010305 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018765 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.005785 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_miss_latency::cpu1.inst 60159250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 679107272 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 451250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 62500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 185254250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1374910602 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2300007624 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25039931500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26362168250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 51402099750 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 935202510 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 8516244000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 9451446510 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25975134010 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34878412250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60853546260 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000383 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007647 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017132 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000373 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000233 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010250 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018803 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.005773 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991507 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.986564 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.987512 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.508676 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.344249 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.366927 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.117133 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007641 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.115680 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000591 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010305 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.116263 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.023420 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007641 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.115680 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000591 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010305 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.116263 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.023420 # mshr miss rate for overall accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.344476 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.366569 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.117092 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000383 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007647 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.115599 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000373 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000233 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010250 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.116251 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.023400 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000383 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007647 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.115599 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000373 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000233 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010250 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.116251 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.023400 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58759.980040 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63510.695187 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 62440.744536 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64946.202532 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 62947.444679 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60039.171657 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64624.219447 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 64464.285714 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63573.867536 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 66537.011054 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 64252.770682 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.070664 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001.486381 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.668896 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62525.097599 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 63351.490352 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63074.321708 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.334448 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62561.980200 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62753.451571 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62689.252619 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58759.980040 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62627.253764 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 62440.744536 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63536.800965 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 63047.947183 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60039.171657 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62775.676835 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64464.285714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63573.867536 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63193.942271 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 63013.907507 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58759.980040 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62627.253764 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 62440.744536 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63536.800965 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 63047.947183 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60039.171657 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62775.676835 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64464.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63573.867536 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63193.942271 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63013.907507 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -987,52 +1011,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58815755 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1021426 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1021425 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 432247 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 432247 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 265552 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1513 # Transaction distribution +system.toL2Bus.throughput 58816500 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1021450 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1021449 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 432230 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 432230 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 265546 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1512 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1515 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80586 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80586 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831264 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2423236 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15497 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52067 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3322064 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26578304 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37416070 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21580 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 84860 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 64100814 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141271334 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 101600 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2179143758 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::UpgradeResp 1514 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80593 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80593 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831311 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2423002 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15637 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52276 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3322226 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26580608 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37417965 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21908 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 85464 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 64105945 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141275262 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 99532 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2179112263 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1872769954 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1872836168 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1848854181 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1848885181 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10116966 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10174967 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30973250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 31036489 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48762849 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13795996 # Transaction distribution -system.iobus.trans_dist::ReadResp 13795996 # Transaction distribution -system.iobus.trans_dist::WriteReq 2775 # Transaction distribution -system.iobus.trans_dist::WriteResp 2775 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11418 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3030 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48762826 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13805907 # Transaction distribution +system.iobus.trans_dist::ReadResp 13805907 # Transaction distribution +system.iobus.trans_dist::WriteReq 2774 # Transaction distribution +system.iobus.trans_dist::WriteResp 2774 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11404 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3028 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 256 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 719202 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 718942 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -1048,18 +1072,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 734214 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26863328 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26863328 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27597542 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15382 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 733938 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26883424 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26883424 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27617362 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6056 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 715532 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 715269 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1075,14 +1099,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 738102 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107453312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107453312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108191414 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 117209190 # Total data (bytes) -system.iobus.reqLayer0.occupancy 7974000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 737821 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107533696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107533696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108271517 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 117209194 # Total data (bytes) +system.iobus.reqLayer0.occupancy 7964000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1515000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1514000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1094,7 +1118,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 360101000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 359973000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -1126,35 +1150,35 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13431664000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13441712000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 731439000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 731164000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 36823110000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 36852557250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7991455 # DTB read hits -system.cpu0.dtb.read_misses 6184 # DTB read misses -system.cpu0.dtb.write_hits 6591541 # DTB write hits +system.cpu0.dtb.read_hits 7990938 # DTB read hits +system.cpu0.dtb.read_misses 6181 # DTB read misses +system.cpu0.dtb.write_hits 6591681 # DTB write hits system.cpu0.dtb.write_misses 1989 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 674 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5669 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5665 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 118 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 119 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 208 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7997639 # DTB read accesses -system.cpu0.dtb.write_accesses 6593530 # DTB write accesses +system.cpu0.dtb.read_accesses 7997119 # DTB read accesses +system.cpu0.dtb.write_accesses 6593670 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14582996 # DTB hits -system.cpu0.dtb.misses 8173 # DTB misses -system.cpu0.dtb.accesses 14591169 # DTB accesses -system.cpu0.itb.inst_hits 32325256 # ITB inst hits -system.cpu0.itb.inst_misses 3454 # ITB inst misses +system.cpu0.dtb.hits 14582619 # DTB hits +system.cpu0.dtb.misses 8170 # DTB misses +system.cpu0.dtb.accesses 14590789 # DTB accesses +system.cpu0.itb.inst_hits 32323173 # ITB inst hits +system.cpu0.itb.inst_misses 3455 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1170,400 +1194,400 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32328710 # ITB inst accesses -system.cpu0.itb.hits 32325256 # DTB hits -system.cpu0.itb.misses 3454 # DTB misses -system.cpu0.itb.accesses 32328710 # DTB accesses -system.cpu0.numCycles 113673861 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32326628 # ITB inst accesses +system.cpu0.itb.hits 32323173 # DTB hits +system.cpu0.itb.misses 3455 # DTB misses +system.cpu0.itb.accesses 32326628 # DTB accesses +system.cpu0.numCycles 113706934 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31847112 # Number of instructions committed -system.cpu0.committedOps 42008964 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37152656 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5018 # Number of float alu accesses -system.cpu0.num_func_calls 1198427 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4245737 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37152656 # number of integer instructions -system.cpu0.num_fp_insts 5018 # number of float instructions -system.cpu0.num_int_register_reads 189368889 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39264582 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3589 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1430 # number of times the floating registers were written -system.cpu0.num_mem_refs 15250074 # number of memory refs -system.cpu0.num_load_insts 8359762 # Number of load instructions -system.cpu0.num_store_insts 6890312 # Number of store instructions -system.cpu0.num_idle_cycles 110868175.114613 # Number of idle cycles -system.cpu0.num_busy_cycles 2805685.885387 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024682 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975318 # Percentage of idle cycles +system.cpu0.committedInsts 31845607 # Number of instructions committed +system.cpu0.committedOps 42007795 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37151613 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4937 # Number of float alu accesses +system.cpu0.num_func_calls 1198507 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4245528 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37151613 # number of integer instructions +system.cpu0.num_fp_insts 4937 # number of float instructions +system.cpu0.num_int_register_reads 189362798 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39261274 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3572 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1366 # number of times the floating registers were written +system.cpu0.num_mem_refs 15249830 # number of memory refs +system.cpu0.num_load_insts 8359344 # Number of load instructions +system.cpu0.num_store_insts 6890486 # Number of store instructions +system.cpu0.num_idle_cycles 110900908.371908 # Number of idle cycles +system.cpu0.num_busy_cycles 2806025.628092 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024678 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975322 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 891412 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.602619 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43641790 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 891924 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 48.929942 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8178595250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 492.265032 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.623785 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 11.713802 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.961455 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014890 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.022879 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999224 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 31851952 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8051251 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3738587 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43641790 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31851952 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8051251 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3738587 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43641790 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31851952 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8051251 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3738587 # number of overall hits -system.cpu0.icache.overall_hits::total 43641790 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 475959 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 131403 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 308483 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 915845 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 475959 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 131403 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 308483 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 915845 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 475959 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 131403 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 308483 # number of overall misses -system.cpu0.icache.overall_misses::total 915845 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1773590500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4162650116 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5936240616 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1773590500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4162650116 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5936240616 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1773590500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4162650116 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5936240616 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32327911 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 8182654 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 4047070 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 44557635 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32327911 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 8182654 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 4047070 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 44557635 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32327911 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 8182654 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 4047070 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 44557635 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014723 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016059 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076224 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.020554 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014723 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016059 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076224 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.020554 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014723 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016059 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076224 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.020554 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13497.336438 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13493.936833 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6481.708822 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13497.336438 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13493.936833 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6481.708822 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13497.336438 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13493.936833 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6481.708822 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3646 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 891661 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.603832 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 43642559 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 892173 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 48.917148 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 8180434250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 493.710568 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.685506 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.207759 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.964278 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.015011 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.019937 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999226 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 31849634 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 8050768 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3742157 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 43642559 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 31849634 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 8050768 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3742157 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 43642559 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 31849634 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 8050768 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3742157 # number of overall hits +system.cpu0.icache.overall_hits::total 43642559 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 476194 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 131290 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 308690 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 916174 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 476194 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 131290 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 308690 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 916174 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 476194 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 131290 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 308690 # number of overall misses +system.cpu0.icache.overall_misses::total 916174 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1773545250 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4166299335 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5939844585 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1773545250 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4166299335 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5939844585 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1773545250 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4166299335 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5939844585 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32325828 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 8182058 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 4050847 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 44558733 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 32325828 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 8182058 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 4050847 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 44558733 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32325828 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 8182058 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 4050847 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 44558733 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014731 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016046 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076204 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.020561 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014731 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016046 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076204 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.020561 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014731 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016046 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076204 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.020561 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13508.608805 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13496.709757 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6483.314943 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13508.608805 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13496.709757 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6483.314943 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13508.608805 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13496.709757 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6483.314943 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4376 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 241 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 225 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.128631 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.448889 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23908 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 23908 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 23908 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 23908 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 23908 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 23908 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 131403 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 284575 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 415978 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 131403 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 284575 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 415978 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 131403 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 284575 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 415978 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1510394500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3385597029 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4895991529 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1510394500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3385597029 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4895991529 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1510394500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3385597029 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4895991529 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016059 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070316 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23991 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 23991 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 23991 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 23991 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 23991 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 23991 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 131290 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 284699 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 415989 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 131290 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 284699 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 415989 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 131290 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 284699 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 415989 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1510573750 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3389684570 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4900258320 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1510573750 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3389684570 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4900258320 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1510573750 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3389684570 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4900258320 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016046 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070281 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009336 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016059 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070316 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016046 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070281 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.009336 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016059 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070316 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016046 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070281 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.009336 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11494.368470 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11897.029005 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11769.832849 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11494.368470 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11897.029005 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11769.832849 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11494.368470 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11897.029005 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11769.832849 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11505.626857 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11906.204693 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11779.778600 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11505.626857 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11906.204693 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11779.778600 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11505.626857 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11906.204693 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11779.778600 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 629916 # number of replacements +system.cpu0.dcache.tags.replacements 629828 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997119 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23219265 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 630428 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 36.830955 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 23220836 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 630340 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 36.838589 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.028749 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.124022 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.844348 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970759 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015867 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013368 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.025505 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.136631 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.834983 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970753 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015892 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013350 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6862135 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1819979 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4638838 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13320952 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5960420 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1315170 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2133916 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9409506 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131682 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 33066 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73671 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 238419 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 138143 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34804 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74442 # number of StoreCondReq hits +system.cpu0.dcache.ReadReq_hits::cpu0.data 6861592 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1819766 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4641843 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13323201 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5960512 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1314083 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2134390 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9408985 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131699 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 33044 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73537 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 238280 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 138171 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34778 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74440 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 247389 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12822555 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 3135149 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6772754 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 22730458 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12822555 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 3135149 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6772754 # number of overall hits -system.cpu0.dcache.overall_hits::total 22730458 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 176872 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 63653 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 271744 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 512269 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 167825 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 28657 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 610336 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 806818 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6461 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1738 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3756 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11955 # number of LoadLockedReq misses +system.cpu0.dcache.demand_hits::cpu0.data 12822104 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 3133849 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6776233 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 22732186 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12822104 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 3133849 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6776233 # number of overall hits +system.cpu0.dcache.overall_hits::total 22732186 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 176730 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 63698 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 271377 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 511805 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 167828 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 28621 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 610894 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 807343 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6472 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1734 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3738 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11944 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu2.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 344697 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 92310 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 882080 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1319087 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 344697 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 92310 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 882080 # number of overall misses -system.cpu0.dcache.overall_misses::total 1319087 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 905796750 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3920290585 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4826087335 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1012897489 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 23468295787 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 24481193276 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22815750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 50223749 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 73039499 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 344558 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 92319 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 882271 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1319148 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 344558 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 92319 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 882271 # number of overall misses +system.cpu0.dcache.overall_misses::total 1319148 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 907621250 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3911808086 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4819429336 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1013384989 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 23348414230 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24361799219 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22749500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 49835999 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 72585499 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 26000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 1918694239 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 27388586372 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 29307280611 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1918694239 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 27388586372 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 29307280611 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7039007 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1883632 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4910582 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13833221 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6128245 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1343827 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2744252 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10216324 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138143 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34804 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77427 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250374 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 138143 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34804 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74444 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu1.data 1921006239 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 27260222316 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 29181228555 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 1921006239 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 27260222316 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 29181228555 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7038322 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1883464 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4913220 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13835006 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6128340 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1342704 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2745284 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10216328 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138171 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34778 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77275 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 250224 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 138171 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34778 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74442 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247391 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13167252 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3227459 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7654834 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24049545 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13167252 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3227459 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7654834 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24049545 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025127 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033793 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.055338 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037032 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027385 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021325 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.222405 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.078973 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046770 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049937 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.048510 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047749 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 13166662 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 3226168 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7658504 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24051334 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13166662 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 3226168 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7658504 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24051334 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025110 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033820 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.055234 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036993 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027386 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021316 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.222525 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.079025 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046841 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049859 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.048373 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047733 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000027 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026178 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028601 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115232 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.054849 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026178 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028601 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.115232 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.054849 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14230.228740 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14426.410832 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9421.002120 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35345.552186 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 38451.436237 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 30342.894279 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13127.589183 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13371.605165 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6109.535675 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026169 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028616 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115201 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.054847 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026169 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028616 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.115201 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.054847 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14248.818644 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14414.663313 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9416.534297 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35407.043395 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 38220.074563 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30175.277694 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13119.665513 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13332.262975 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6077.151624 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20785.334622 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 31050.002689 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 22217.852659 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20785.334622 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 31050.002689 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 22217.852659 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8471 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2566 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 892 # number of cycles access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20808.351899 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30897.787999 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22121.269604 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20808.351899 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30897.787999 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22121.269604 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 7683 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3605 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 878 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 49 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.496637 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 52.367347 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.750569 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 73.571429 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597747 # number of writebacks -system.cpu0.dcache.writebacks::total 597747 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 140335 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 140335 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 556925 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 556925 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 415 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 415 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 697260 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 697260 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 697260 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 697260 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63653 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 131409 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 195062 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28657 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53411 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 82068 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1738 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3341 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5079 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 597611 # number of writebacks +system.cpu0.dcache.writebacks::total 597611 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 139954 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 139954 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 557446 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 557446 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 413 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 413 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 697400 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 697400 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 697400 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 697400 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63698 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 131423 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 195121 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28621 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53448 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 82069 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1734 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3325 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5059 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 92310 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 184820 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 277130 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 92310 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 184820 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 277130 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 778293250 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1698666084 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2476959334 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 952956511 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1898218478 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2851174989 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19339250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38699751 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 58039001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_misses::cpu1.data 92319 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 184871 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 277190 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 92319 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 184871 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 277190 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 780025750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1703190327 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2483216077 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 953521011 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1887250485 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2840771496 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19281500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38325501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57607001 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1731249761 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3596884562 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5328134323 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1731249761 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3596884562 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5328134323 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27375287500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28782575500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56157863000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1442314990 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13341314242 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14783629232 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28817602490 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42123889742 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70941492232 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033793 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026760 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014101 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021325 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019463 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1733546761 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3590440812 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5323987573 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1733546761 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3590440812 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5323987573 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27356277500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28781091750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56137369250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1442174490 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13339751582 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14781926072 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28798451990 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42120843332 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70919295322 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033820 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026749 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014103 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021316 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019469 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008033 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049937 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043150 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020286 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049859 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043028 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020218 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028601 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024144 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011523 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028601 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024144 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011523 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12227.125980 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12926.558181 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12698.318145 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33253.882507 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35539.841568 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34741.616574 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11127.301496 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11583.283747 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11427.249655 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028616 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024139 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011525 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028616 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024139 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011525 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12245.686678 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12959.606210 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12726.544437 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33315.433109 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35310.030029 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34614.428054 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11119.665513 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11526.466466 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11387.033208 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18754.736876 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19461.554821 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19226.118872 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18754.736876 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19461.554821 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19226.118872 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18777.789632 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19421.330614 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19206.997269 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18777.789632 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19421.330614 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19206.997269 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1576,27 +1600,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2096740 # DTB read hits -system.cpu1.dtb.read_misses 2075 # DTB read misses -system.cpu1.dtb.write_hits 1419315 # DTB write hits +system.cpu1.dtb.read_hits 2096419 # DTB read hits +system.cpu1.dtb.read_misses 2083 # DTB read misses +system.cpu1.dtb.write_hits 1418166 # DTB write hits system.cpu1.dtb.write_misses 373 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 234 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1735 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1734 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2098815 # DTB read accesses -system.cpu1.dtb.write_accesses 1419688 # DTB write accesses +system.cpu1.dtb.read_accesses 2098502 # DTB read accesses +system.cpu1.dtb.write_accesses 1418539 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3516055 # DTB hits -system.cpu1.dtb.misses 2448 # DTB misses -system.cpu1.dtb.accesses 3518503 # DTB accesses -system.cpu1.itb.inst_hits 8182654 # ITB inst hits -system.cpu1.itb.inst_misses 1200 # ITB inst misses +system.cpu1.dtb.hits 3514585 # DTB hits +system.cpu1.dtb.misses 2456 # DTB misses +system.cpu1.dtb.accesses 3517041 # DTB accesses +system.cpu1.itb.inst_hits 8182058 # ITB inst hits +system.cpu1.itb.inst_misses 1201 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1605,73 +1629,73 @@ system.cpu1.itb.flush_tlb 277 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 234 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 888 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 889 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8183854 # ITB inst accesses -system.cpu1.itb.hits 8182654 # DTB hits -system.cpu1.itb.misses 1200 # DTB misses -system.cpu1.itb.accesses 8183854 # DTB accesses -system.cpu1.numCycles 581318737 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8183259 # ITB inst accesses +system.cpu1.itb.hits 8182058 # DTB hits +system.cpu1.itb.misses 1201 # DTB misses +system.cpu1.itb.accesses 8183259 # DTB accesses +system.cpu1.numCycles 581387993 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7974693 # Number of instructions committed -system.cpu1.committedOps 10126531 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9058549 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1938 # Number of float alu accesses -system.cpu1.num_func_calls 304877 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1114107 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9058549 # number of integer instructions -system.cpu1.num_fp_insts 1938 # number of float instructions -system.cpu1.num_int_register_reads 52214198 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9844324 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1424 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_mem_refs 3684398 # number of memory refs -system.cpu1.num_load_insts 2190368 # Number of load instructions -system.cpu1.num_store_insts 1494030 # Number of store instructions -system.cpu1.num_idle_cycles 546218260.044225 # Number of idle cycles -system.cpu1.num_busy_cycles 35100476.955774 # Number of busy cycles -system.cpu1.not_idle_fraction 0.060381 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.939619 # Percentage of idle cycles +system.cpu1.committedInsts 7973391 # Number of instructions committed +system.cpu1.committedOps 10123180 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9055145 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2019 # Number of float alu accesses +system.cpu1.num_func_calls 304839 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1113920 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9055145 # number of integer instructions +system.cpu1.num_fp_insts 2019 # number of float instructions +system.cpu1.num_int_register_reads 52196104 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9841677 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1441 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 580 # number of times the floating registers were written +system.cpu1.num_mem_refs 3682729 # number of memory refs +system.cpu1.num_load_insts 2189938 # Number of load instructions +system.cpu1.num_store_insts 1492791 # Number of store instructions +system.cpu1.num_idle_cycles 546287151.729317 # Number of idle cycles +system.cpu1.num_busy_cycles 35100841.270683 # Number of busy cycles +system.cpu1.not_idle_fraction 0.060374 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.939626 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4723221 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3843292 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 222521 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3120017 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2528037 # Number of BTB hits +system.cpu2.branchPred.lookups 4728615 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3846891 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 223365 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3153803 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2531568 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 81.026385 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 412365 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21211 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 80.270328 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 413323 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21760 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10969613 # DTB read hits -system.cpu2.dtb.read_misses 23045 # DTB read misses -system.cpu2.dtb.write_hits 3352330 # DTB write hits +system.cpu2.dtb.read_hits 10972958 # DTB read hits +system.cpu2.dtb.read_misses 22884 # DTB read misses +system.cpu2.dtb.write_hits 3353841 # DTB write hits system.cpu2.dtb.write_misses 6440 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 531 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2328 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 714 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 159 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2329 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 684 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 147 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 478 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10992658 # DTB read accesses -system.cpu2.dtb.write_accesses 3358770 # DTB write accesses +system.cpu2.dtb.perms_faults 471 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10995842 # DTB read accesses +system.cpu2.dtb.write_accesses 3360281 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14321943 # DTB hits -system.cpu2.dtb.misses 29485 # DTB misses -system.cpu2.dtb.accesses 14351428 # DTB accesses -system.cpu2.itb.inst_hits 4048520 # ITB inst hits -system.cpu2.itb.inst_misses 4581 # ITB inst misses +system.cpu2.dtb.hits 14326799 # DTB hits +system.cpu2.dtb.misses 29324 # DTB misses +system.cpu2.dtb.accesses 14356123 # DTB accesses +system.cpu2.itb.inst_hits 4052293 # ITB inst hits +system.cpu2.itb.inst_misses 4591 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits @@ -1684,110 +1708,110 @@ system.cpu2.itb.flush_entries 1671 # Nu system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1028 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1020 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4053101 # ITB inst accesses -system.cpu2.itb.hits 4048520 # DTB hits -system.cpu2.itb.misses 4581 # DTB misses -system.cpu2.itb.accesses 4053101 # DTB accesses -system.cpu2.numCycles 88363580 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4056884 # ITB inst accesses +system.cpu2.itb.hits 4052293 # DTB hits +system.cpu2.itb.misses 4591 # DTB misses +system.cpu2.itb.accesses 4056884 # DTB accesses +system.cpu2.numCycles 88364936 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9342746 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32497136 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4723221 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2940402 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6855397 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1756636 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 50446 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 18848050 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 334 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 925 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 34178 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 721824 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 449 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4047074 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 289511 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1970 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37061318 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.053700 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.440521 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9352566 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32517206 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4728615 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2944891 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6861610 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1759869 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 50868 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 18844594 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 335 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 866 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 32744 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 721068 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 448 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4050852 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 289827 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1989 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37074469 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.054164 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.440934 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30210914 81.52% 81.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 385385 1.04% 82.56% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 515477 1.39% 83.95% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 820134 2.21% 86.16% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 628486 1.70% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 342820 0.93% 88.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1044433 2.82% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 229207 0.62% 92.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2884462 7.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30218075 81.51% 81.51% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 386681 1.04% 82.55% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 516163 1.39% 83.94% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 819367 2.21% 86.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 628808 1.70% 87.85% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 344228 0.93% 88.78% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1045241 2.82% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 229591 0.62% 92.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2886315 7.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37061318 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053452 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.367766 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9926500 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19460558 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6238388 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 279816 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1155131 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 608208 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53066 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36958585 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 178391 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1155131 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10476553 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6920166 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11076723 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5947862 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1483966 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34870863 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2458 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 328650 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 889849 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 96 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37358262 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 159586833 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 148423376 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 3369 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26507725 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10850536 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 232822 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 209087 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3256835 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6623705 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3904787 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 530493 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 775113 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32195808 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 505146 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34809127 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 54913 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7172484 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19086467 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 147942 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37061318 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.939231 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.598560 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37074469 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053512 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.367988 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9932859 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19459354 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6244628 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 279238 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1157490 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 609849 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53110 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36985250 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 179754 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1157490 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10483306 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6921288 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11074515 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5953553 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1483425 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34895792 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2444 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 326661 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 892066 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 111 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37386016 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 159700078 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 148525933 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 3408 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26513636 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10872379 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 232480 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 208815 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3253838 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6628841 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3905916 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 536820 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 771052 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32212739 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 505163 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34823222 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 55040 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7182108 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19097970 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 148083 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37074469 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.939278 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.598547 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24455957 65.99% 65.99% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3833682 10.34% 76.33% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2322342 6.27% 82.60% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2005181 5.41% 88.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2795966 7.54% 95.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 971107 2.62% 98.17% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 498292 1.34% 99.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 144261 0.39% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34530 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24463826 65.99% 65.99% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3833492 10.34% 76.33% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2324654 6.27% 82.60% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2008652 5.42% 88.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2796278 7.54% 95.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 971248 2.62% 98.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 496274 1.34% 99.51% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 144890 0.39% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 35155 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37061318 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37074469 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19660 1.28% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19545 1.28% 1.28% # attempts to use FU when none available system.cpu2.iq.fu_full::IntMult 1 0.00% 1.28% # attempts to use FU when none available system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.28% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.28% # attempts to use FU when none available @@ -1816,13 +1840,13 @@ system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.28% # at system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.28% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.28% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1402550 91.51% 92.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 110445 7.21% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1401661 91.55% 92.82% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 109897 7.18% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61175 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19747110 56.73% 56.91% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 27980 0.08% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61115 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19755783 56.73% 56.91% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 28013 0.08% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.99% # Type of FU issued @@ -1838,7 +1862,7 @@ system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.99% # Ty system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.99% # Type of FU issued @@ -1850,114 +1874,114 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc 388 0.00% 56.99% # Ty system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11452276 32.90% 89.89% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3520179 10.11% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11456328 32.90% 89.89% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3521577 10.11% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34809127 # Type of FU issued -system.cpu2.iq.rate 0.393931 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1532656 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044030 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108288948 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39878610 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28070823 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7546 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3965 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3367 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36276582 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 4026 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 205280 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34823222 # Type of FU issued +system.cpu2.iq.rate 0.394084 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1531104 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.043968 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108328678 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39905127 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28084625 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7572 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 4019 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3368 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36289170 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 4041 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206363 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1528845 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1875 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9489 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 562920 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1533130 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 2013 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9465 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 562980 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5328051 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 344229 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5327720 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 344503 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1155131 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5244365 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 89322 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32783919 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 60352 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6623705 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3904787 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 362611 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 30261 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2481 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9489 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 106879 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 89021 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 195900 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33894861 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11182187 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 914266 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1157490 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5247900 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 88519 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32800222 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 60619 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6628841 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3905916 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 362644 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 29757 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2395 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9465 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 107959 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 89408 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 197367 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33908136 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11185478 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 915086 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 82965 # number of nop insts executed -system.cpu2.iew.exec_refs 14668868 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3706634 # Number of branches executed -system.cpu2.iew.exec_stores 3486681 # Number of stores executed -system.cpu2.iew.exec_rate 0.383584 # Inst execution rate -system.cpu2.iew.wb_sent 33494578 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28074190 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16115456 # num instructions producing a value -system.cpu2.iew.wb_consumers 29164308 # num instructions consuming a value +system.cpu2.iew.exec_nop 82320 # number of nop insts executed +system.cpu2.iew.exec_refs 14673656 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3709694 # Number of branches executed +system.cpu2.iew.exec_stores 3488178 # Number of stores executed +system.cpu2.iew.exec_rate 0.383728 # Inst execution rate +system.cpu2.iew.wb_sent 33508440 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28087993 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16121354 # num instructions producing a value +system.cpu2.iew.wb_consumers 29172590 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.317712 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.552575 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.317864 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.552620 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7126752 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 357204 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 170224 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35906001 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.707499 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.751012 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7137877 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 357080 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 171034 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35916785 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.707415 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.751354 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27147368 75.61% 75.61% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4230684 11.78% 87.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1251387 3.49% 90.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 639812 1.78% 92.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 559957 1.56% 94.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 318640 0.89% 95.10% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 417979 1.16% 96.27% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 311730 0.87% 97.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1028444 2.86% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27161260 75.62% 75.62% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4227698 11.77% 87.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1252285 3.49% 90.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 635084 1.77% 92.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 561790 1.56% 94.21% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 319405 0.89% 95.10% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 418201 1.16% 96.27% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 311340 0.87% 97.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1029722 2.87% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35906001 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20561870 # Number of instructions committed -system.cpu2.commit.committedOps 25403458 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35916785 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20564616 # Number of instructions committed +system.cpu2.commit.committedOps 25408067 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8436727 # Number of memory references committed -system.cpu2.commit.loads 5094860 # Number of loads committed -system.cpu2.commit.membars 94449 # Number of memory barriers committed -system.cpu2.commit.branches 3185060 # Number of branches committed +system.cpu2.commit.refs 8438647 # Number of memory references committed +system.cpu2.commit.loads 5095711 # Number of loads committed +system.cpu2.commit.membars 94423 # Number of memory barriers committed +system.cpu2.commit.branches 3185422 # Number of branches committed system.cpu2.commit.fp_insts 3299 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22606405 # Number of committed integer instructions. -system.cpu2.commit.function_calls 295605 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 1028444 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 22610745 # Number of committed integer instructions. +system.cpu2.commit.function_calls 295586 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 1029722 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66885510 # The number of ROB reads -system.cpu2.rob.rob_writes 66259648 # The number of ROB writes -system.cpu2.timesIdled 359925 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51302262 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3553994827 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20506347 # Number of Instructions Simulated -system.cpu2.committedOps 25347935 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 20506347 # Number of Instructions Simulated -system.cpu2.cpi 4.309084 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.309084 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.232068 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.232068 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 157055367 # number of integer regfile reads -system.cpu2.int_regfile_writes 29889640 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22622 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20830 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9269321 # number of misc regfile reads -system.cpu2.misc_regfile_writes 242794 # number of misc regfile writes +system.cpu2.rob.rob_reads 66910934 # The number of ROB reads +system.cpu2.rob.rob_writes 66293514 # The number of ROB writes +system.cpu2.timesIdled 359960 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51290467 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3553935024 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20509130 # Number of Instructions Simulated +system.cpu2.committedOps 25352581 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 20509130 # Number of Instructions Simulated +system.cpu2.cpi 4.308566 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.308566 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.232096 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.232096 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 157121826 # number of integer regfile reads +system.cpu2.int_regfile_writes 29906145 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22616 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20826 # number of floating regfile writes +system.cpu2.misc_regfile_reads 9261107 # number of misc regfile reads +system.cpu2.misc_regfile_writes 242774 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1972,10 +1996,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1346583006000 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1346583006000 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1346583006000 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1346583006000 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1347589582250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1347589582250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1347589582250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1347589582250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 0865afb47..bd21d2c8f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -105,6 +113,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -169,6 +179,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -184,6 +195,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -206,18 +218,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -226,15 +241,18 @@ port=system.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 +eventq_index=0 [system.cpu0.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu0.fuPool.FUList0.opList [system.cpu0.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -243,16 +261,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 [system.cpu0.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu0.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -261,22 +282,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 [system.cpu0.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu0.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu0.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -285,22 +310,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 [system.cpu0.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu0.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu0.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -309,10 +338,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList4.opList [system.cpu0.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -321,124 +352,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 [system.cpu0.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu0.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu0.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu0.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu0.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu0.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu0.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu0.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu0.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu0.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu0.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu0.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu0.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu0.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu0.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu0.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu0.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu0.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -447,10 +499,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList6.opList [system.cpu0.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -459,16 +513,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 [system.cpu0.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu0.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -477,10 +534,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu0.fuPool.FUList8.opList [system.cpu0.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -491,6 +550,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -513,14 +573,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -539,18 +602,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=DerivO3CPU @@ -581,6 +647,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -643,6 +711,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -655,12 +724,14 @@ predType=tournament [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system @@ -668,15 +739,18 @@ sys=system type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 +eventq_index=0 [system.cpu1.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu1.fuPool.FUList0.opList [system.cpu1.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -685,16 +759,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 [system.cpu1.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu1.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -703,22 +780,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 [system.cpu1.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu1.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu1.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -727,22 +808,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 [system.cpu1.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu1.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu1.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -751,10 +836,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList4.opList [system.cpu1.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -763,124 +850,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 [system.cpu1.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu1.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu1.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu1.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu1.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu1.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu1.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu1.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu1.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu1.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu1.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu1.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu1.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu1.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu1.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu1.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu1.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu1.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -889,10 +997,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList6.opList [system.cpu1.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -901,16 +1011,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 [system.cpu1.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu1.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -919,16 +1032,19 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu1.fuPool.FUList8.opList [system.cpu1.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -947,30 +1063,36 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -983,6 +1105,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -1005,6 +1128,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -1014,6 +1138,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -1036,6 +1161,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -1043,6 +1169,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1054,6 +1181,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1080,6 +1208,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -1091,19 +1220,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -1113,6 +1246,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -1122,6 +1256,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -1150,6 +1285,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -1159,8 +1295,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -1172,6 +1340,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -1187,6 +1356,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -1201,6 +1372,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -1210,6 +1382,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -1231,8 +1404,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -1241,6 +1416,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -1251,6 +1427,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -1261,6 +1438,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -1271,6 +1449,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -1285,6 +1464,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -1298,6 +1478,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -1315,6 +1496,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -1327,6 +1509,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -1338,6 +1521,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -1348,6 +1532,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -1360,6 +1545,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -1373,6 +1559,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -1383,6 +1570,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -1393,6 +1581,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1403,6 +1592,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1415,6 +1605,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -1429,6 +1620,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -1441,6 +1633,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -1455,6 +1648,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1465,6 +1659,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1475,6 +1670,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1485,6 +1681,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1493,6 +1690,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1501,6 +1699,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1510,11 +1709,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index cc97b6f9f..5fef90c5a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,166 +1,154 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.549325 # Number of seconds simulated -sim_ticks 2549325180000 # Number of ticks simulated -final_tick 2549325180000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.549345 # Number of seconds simulated +sim_ticks 2549345168000 # Number of ticks simulated +final_tick 2549345168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61075 # Simulator instruction rate (inst/s) -host_op_rate 78588 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2581455626 # Simulator tick rate (ticks/s) -host_mem_usage 428832 # Number of bytes of host memory used -host_seconds 987.55 # Real time elapsed on the host -sim_insts 60314884 # Number of instructions simulated -sim_ops 77609482 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 48945 # Simulator instruction rate (inst/s) +host_op_rate 62980 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2068782078 # Simulator tick rate (ticks/s) +host_mem_usage 448444 # Number of bytes of host memory used +host_seconds 1232.29 # Real time elapsed on the host +sim_insts 60314699 # Number of instructions simulated +sim_ops 77609228 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 507840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4720464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 291712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4372184 # Number of bytes read from this memory -system.physmem.bytes_read::total 131005480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 507840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 291712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785664 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1521520 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1494580 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801764 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 498624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4680272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 301248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4410392 # Number of bytes read from this memory +system.physmem.bytes_read::total 131004072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 498624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 301248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784640 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1521380 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1494720 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800740 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7935 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73791 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4558 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 68321 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293464 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59151 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380380 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373645 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813176 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47506897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 678 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7791 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4707 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 68918 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293442 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59135 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380345 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373680 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813160 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47506524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 728 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 199206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1851652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 114427 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1715036 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51388297 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 199206 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 114427 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313633 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 596832 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 586265 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2668064 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47506897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 195589 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1835872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 118167 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1730010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51387342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 195589 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 118167 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313756 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484554 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 596773 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 586315 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2667642 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47506524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 728 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 199206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2448485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 114427 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2301301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54056362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293464 # Number of read requests accepted -system.physmem.writeReqs 813176 # Number of write requests accepted -system.physmem.readBursts 15293464 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813176 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 978217536 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 564160 # Total number of bytes read from write queue -system.physmem.bytesWritten 6910272 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131005480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6801764 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 8815 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 705189 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4711 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955865 # Per bank write bursts -system.physmem.perBankRdBursts::1 955523 # Per bank write bursts -system.physmem.perBankRdBursts::2 954611 # Per bank write bursts -system.physmem.perBankRdBursts::3 954852 # Per bank write bursts -system.physmem.perBankRdBursts::4 955764 # Per bank write bursts -system.physmem.perBankRdBursts::5 955945 # Per bank write bursts -system.physmem.perBankRdBursts::6 954843 # Per bank write bursts -system.physmem.perBankRdBursts::7 954680 # Per bank write bursts -system.physmem.perBankRdBursts::8 956251 # Per bank write bursts -system.physmem.perBankRdBursts::9 955822 # Per bank write bursts -system.physmem.perBankRdBursts::10 954302 # Per bank write bursts -system.physmem.perBankRdBursts::11 954022 # Per bank write bursts -system.physmem.perBankRdBursts::12 956218 # Per bank write bursts -system.physmem.perBankRdBursts::13 955977 # Per bank write bursts -system.physmem.perBankRdBursts::14 955052 # Per bank write bursts -system.physmem.perBankRdBursts::15 954922 # Per bank write bursts -system.physmem.perBankWrBursts::0 6685 # Per bank write bursts -system.physmem.perBankWrBursts::1 6462 # Per bank write bursts -system.physmem.perBankWrBursts::2 6616 # Per bank write bursts -system.physmem.perBankWrBursts::3 6625 # Per bank write bursts -system.physmem.perBankWrBursts::4 6578 # Per bank write bursts -system.physmem.perBankWrBursts::5 6834 # Per bank write bursts -system.physmem.perBankWrBursts::6 6825 # Per bank write bursts -system.physmem.perBankWrBursts::7 6778 # Per bank write bursts -system.physmem.perBankWrBursts::8 7112 # Per bank write bursts -system.physmem.perBankWrBursts::9 6876 # Per bank write bursts -system.physmem.perBankWrBursts::10 6540 # Per bank write bursts -system.physmem.perBankWrBursts::11 6189 # Per bank write bursts -system.physmem.perBankWrBursts::12 7142 # Per bank write bursts -system.physmem.perBankWrBursts::13 6759 # Per bank write bursts -system.physmem.perBankWrBursts::14 7042 # Per bank write bursts -system.physmem.perBankWrBursts::15 6910 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 195589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2432645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 118167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2316325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54054984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293442 # Number of read requests accepted +system.physmem.writeReqs 813160 # Number of write requests accepted +system.physmem.readBursts 15293442 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813160 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 978220224 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 560064 # Total number of bytes read from write queue +system.physmem.bytesWritten 6909248 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131004072 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6800740 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 8751 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705188 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4685 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955866 # Per bank write bursts +system.physmem.perBankRdBursts::1 955512 # Per bank write bursts +system.physmem.perBankRdBursts::2 954595 # Per bank write bursts +system.physmem.perBankRdBursts::3 954812 # Per bank write bursts +system.physmem.perBankRdBursts::4 955762 # Per bank write bursts +system.physmem.perBankRdBursts::5 955910 # Per bank write bursts +system.physmem.perBankRdBursts::6 954892 # Per bank write bursts +system.physmem.perBankRdBursts::7 954654 # Per bank write bursts +system.physmem.perBankRdBursts::8 956247 # Per bank write bursts +system.physmem.perBankRdBursts::9 955899 # Per bank write bursts +system.physmem.perBankRdBursts::10 954311 # Per bank write bursts +system.physmem.perBankRdBursts::11 954068 # Per bank write bursts +system.physmem.perBankRdBursts::12 956211 # Per bank write bursts +system.physmem.perBankRdBursts::13 955980 # Per bank write bursts +system.physmem.perBankRdBursts::14 955097 # Per bank write bursts +system.physmem.perBankRdBursts::15 954875 # Per bank write bursts +system.physmem.perBankWrBursts::0 6687 # Per bank write bursts +system.physmem.perBankWrBursts::1 6461 # Per bank write bursts +system.physmem.perBankWrBursts::2 6610 # Per bank write bursts +system.physmem.perBankWrBursts::3 6631 # Per bank write bursts +system.physmem.perBankWrBursts::4 6571 # Per bank write bursts +system.physmem.perBankWrBursts::5 6830 # Per bank write bursts +system.physmem.perBankWrBursts::6 6820 # Per bank write bursts +system.physmem.perBankWrBursts::7 6764 # Per bank write bursts +system.physmem.perBankWrBursts::8 7113 # Per bank write bursts +system.physmem.perBankWrBursts::9 6879 # Per bank write bursts +system.physmem.perBankWrBursts::10 6545 # Per bank write bursts +system.physmem.perBankWrBursts::11 6197 # Per bank write bursts +system.physmem.perBankWrBursts::12 7141 # Per bank write bursts +system.physmem.perBankWrBursts::13 6760 # Per bank write bursts +system.physmem.perBankWrBursts::14 7037 # Per bank write bursts +system.physmem.perBankWrBursts::15 6911 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2549324058500 # Total gap between requests +system.physmem.totGap 2549344036000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 42 # Read request sizes (log2) system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154606 # Read request sizes (log2) +system.physmem.readPktSize::6 154584 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754025 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59151 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1187642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1126920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1081304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3687011 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2647213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2642028 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2655762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 54010 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 60825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20224 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59135 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1194358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1134175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1088302 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3688965 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2641659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2636525 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2648641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 52098 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 58013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20372 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20270 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -171,418 +159,411 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86834 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11344.953359 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1015.074534 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16830.192081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23626 27.21% 27.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14089 16.23% 43.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2724 3.14% 46.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2126 2.45% 49.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1310 1.51% 50.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1204 1.39% 51.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 811 0.93% 52.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1018 1.17% 54.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 572 0.66% 54.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 583 0.67% 55.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 533 0.61% 55.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 603 0.69% 56.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 284 0.33% 56.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 265 0.31% 57.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 147 0.17% 57.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 578 0.67% 58.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 113 0.13% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 129 0.15% 58.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 72 0.08% 58.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 237 0.27% 58.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 56 0.06% 58.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 502 0.58% 59.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 39 0.04% 59.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 171 0.20% 59.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 11 0.01% 59.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 115 0.13% 59.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 15 0.02% 59.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 109 0.13% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 18 0.02% 59.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 54 0.06% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 24 0.03% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 490 0.56% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 17 0.02% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 36 0.04% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 7 0.01% 60.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 154 0.18% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 14 0.02% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 32 0.04% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 7 0.01% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 95 0.11% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 10 0.01% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 14 0.02% 61.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 9 0.01% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 155 0.18% 61.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 16 0.02% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 17 0.02% 61.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 10 0.01% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 408 0.47% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 10 0.01% 61.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 18 0.02% 61.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 7 0.01% 61.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 96 0.11% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 10 0.01% 61.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 20 0.02% 61.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 9 0.01% 61.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 86 0.10% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 6 0.01% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 21 0.02% 62.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 12 0.01% 62.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 58 0.07% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 7 0.01% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 1 0.00% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 407 0.47% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 10 0.01% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 18 0.02% 62.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 3 0.00% 62.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 75 0.09% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 12 0.01% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 7 0.01% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 139 0.16% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 8 0.01% 62.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 15 0.02% 63.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 9 0.01% 63.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 72 0.08% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 6 0.01% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 13 0.01% 63.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 6 0.01% 63.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 409 0.47% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 7 0.01% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 17 0.02% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 14 0.02% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 76 0.09% 63.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 9 0.01% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 13 0.01% 63.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 8 0.01% 63.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 144 0.17% 63.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 2 0.00% 63.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 9 0.01% 63.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 13 0.01% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 142 0.16% 64.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 12 0.01% 64.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 6 0.01% 64.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 262 0.30% 64.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 6 0.01% 64.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 5 0.01% 64.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 6 0.01% 64.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 136 0.16% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 3 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 8 0.01% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 8 0.01% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 6 0.01% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 21 0.02% 64.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 74 0.09% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 5 0.01% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 8 0.01% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 452 0.52% 65.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 4 0.00% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 13 0.01% 65.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 11 0.01% 65.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 23 0.03% 65.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 4 0.00% 65.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 73 0.08% 65.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 1 0.00% 65.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 2 0.00% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 3 0.00% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 132 0.15% 65.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 4 0.00% 65.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 8 0.01% 65.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 243 0.28% 66.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 128 0.15% 66.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 66 0.08% 66.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 67 0.08% 66.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 450 0.52% 66.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 67 0.08% 66.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 2 0.00% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9799 1 0.00% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9927 1 0.00% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 133 0.15% 67.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 1 0.00% 67.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 251 0.29% 67.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 68 0.08% 67.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10695 1 0.00% 67.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 128 0.15% 67.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 66 0.08% 67.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 387 0.45% 68.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 67 0.08% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11719 1 0.00% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 121 0.14% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 66 0.08% 68.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12103 1 0.00% 68.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 380 0.44% 68.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 37 0.04% 68.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 69 0.08% 68.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 65 0.07% 69.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13255 1 0.00% 69.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 389 0.45% 69.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 129 0.15% 69.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13703 1 0.00% 69.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 66 0.08% 69.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 120 0.14% 69.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 443 0.51% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14407 1 0.00% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14535 1 0.00% 70.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 57 0.07% 70.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 13 0.01% 70.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 119 0.14% 70.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 388 0.45% 71.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 123 0.14% 71.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15751 1 0.00% 71.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 64 0.07% 71.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 66 0.08% 71.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16327 1 0.00% 71.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 526 0.61% 71.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 68 0.08% 72.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 64 0.07% 72.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 122 0.14% 72.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 391 0.45% 72.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 120 0.14% 72.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17735 1 0.00% 72.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 15 0.02% 72.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 57 0.07% 72.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 1 0.00% 72.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 1 0.00% 72.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 444 0.51% 73.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 119 0.14% 73.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 66 0.08% 73.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 129 0.15% 73.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 384 0.44% 74.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 64 0.07% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 70 0.08% 74.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20096-20103 1 0.00% 74.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 37 0.04% 74.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 1 0.00% 74.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 382 0.44% 74.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 65 0.07% 74.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 119 0.14% 75.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 66 0.08% 75.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 385 0.44% 75.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 68 0.08% 75.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21952-21959 1 0.00% 75.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 128 0.15% 75.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 69 0.08% 75.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 1 0.00% 75.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 253 0.29% 76.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22592-22599 1 0.00% 76.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22720-22727 1 0.00% 76.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 132 0.15% 76.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22976-22983 1 0.00% 76.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 67 0.08% 76.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 450 0.52% 76.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 68 0.08% 77.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24007 1 0.00% 77.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 67 0.08% 77.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 129 0.15% 77.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 137 0.16% 77.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24704-24711 1 0.00% 77.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 129 0.15% 77.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 67 0.08% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25152-25159 1 0.00% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25216-25223 1 0.00% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 67 0.08% 77.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 448 0.52% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25664-25671 1 0.00% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 66 0.08% 78.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 134 0.15% 78.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 253 0.29% 78.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 68 0.08% 78.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 129 0.15% 78.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27264-27271 1 0.00% 78.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 68 0.08% 79.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27463 1 0.00% 79.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 384 0.44% 79.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 66 0.08% 79.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 119 0.14% 79.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 64 0.07% 79.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 380 0.44% 80.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28864-28871 1 0.00% 80.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 37 0.04% 80.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 72 0.08% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 65 0.07% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 385 0.44% 80.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 1 0.00% 80.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 129 0.15% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30144-30151 1 0.00% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 64 0.07% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 119 0.14% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 443 0.51% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 56 0.06% 81.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 13 0.01% 81.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 119 0.14% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31552-31559 2 0.00% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 1 0.00% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 389 0.45% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31808-31815 1 0.00% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 124 0.14% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32064-32071 1 0.00% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 66 0.08% 82.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 66 0.08% 82.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 526 0.61% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32832-32839 1 0.00% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 65 0.07% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 65 0.07% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33344-33351 1 0.00% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 1 0.00% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 125 0.14% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33671 1 0.00% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 390 0.45% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 119 0.14% 84.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 13 0.01% 84.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 56 0.06% 84.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 441 0.51% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 119 0.14% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 64 0.07% 84.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 129 0.15% 85.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 385 0.44% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 64 0.07% 85.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 72 0.08% 85.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36416-36423 1 0.00% 85.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 37 0.04% 85.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 380 0.44% 86.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 64 0.07% 86.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 119 0.14% 86.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 66 0.08% 86.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 384 0.44% 86.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38080-38087 1 0.00% 86.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 67 0.08% 87.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 128 0.15% 87.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 68 0.08% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 253 0.29% 87.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 134 0.15% 87.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 66 0.08% 87.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 448 0.52% 88.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 68 0.08% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40320-40327 1 0.00% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 66 0.08% 88.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 129 0.15% 88.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 137 0.16% 88.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 129 0.15% 88.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 67 0.08% 88.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 68 0.08% 89.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 449 0.52% 89.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42176-42183 1 0.00% 89.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 67 0.08% 89.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42432-42439 1 0.00% 89.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 2 0.00% 89.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 132 0.15% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42944-42951 1 0.00% 89.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 251 0.29% 90.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 67 0.08% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43392-43399 2 0.00% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 128 0.15% 90.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 67 0.08% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 384 0.44% 90.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44160-44167 1 0.00% 90.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 68 0.08% 90.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44352-44359 1 0.00% 90.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44480-44487 1 0.00% 90.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 119 0.14% 91.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44736-44743 1 0.00% 91.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 66 0.08% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 383 0.44% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 41 0.05% 91.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 70 0.08% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45632-45639 1 0.00% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 65 0.07% 91.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45952-45959 1 0.00% 91.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 385 0.44% 92.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 129 0.15% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 64 0.07% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 119 0.14% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 440 0.51% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47239 1 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 58 0.07% 93.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 14 0.02% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 120 0.14% 93.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 388 0.45% 93.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 122 0.14% 93.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 64 0.07% 93.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 65 0.07% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 1 0.00% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 2 0.00% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5147 5.93% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 86636 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11370.889515 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1019.409545 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16839.040635 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23447 27.06% 27.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14187 16.38% 43.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2756 3.18% 46.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2051 2.37% 48.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1336 1.54% 50.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1207 1.39% 51.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 834 0.96% 52.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1069 1.23% 54.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 542 0.63% 54.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 595 0.69% 55.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 544 0.63% 56.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 497 0.57% 56.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 259 0.30% 56.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 256 0.30% 57.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 151 0.17% 57.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 457 0.53% 57.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 109 0.13% 58.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 146 0.17% 58.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 72 0.08% 58.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 245 0.28% 58.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 63 0.07% 58.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 509 0.59% 59.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 238 0.27% 59.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 21 0.02% 59.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 111 0.13% 59.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 24 0.03% 59.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 197 0.23% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 24 0.03% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 41 0.05% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 375 0.43% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 14 0.02% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 36 0.04% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 11 0.01% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 279 0.32% 60.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 8 0.01% 60.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 26 0.03% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 6 0.01% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 24 0.03% 60.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 10 0.01% 60.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 21 0.02% 60.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 7 0.01% 61.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 158 0.18% 61.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 8 0.01% 61.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 20 0.02% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 12 0.01% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 221 0.26% 61.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 10 0.01% 61.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 16 0.02% 61.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 7 0.01% 61.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 86 0.10% 61.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 7 0.01% 61.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 12 0.01% 61.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 13 0.02% 61.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 93 0.11% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 7 0.01% 61.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 17 0.02% 61.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 7 0.01% 61.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 145 0.17% 61.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 10 0.01% 61.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 20 0.02% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 16 0.02% 62.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 418 0.48% 62.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 6 0.01% 62.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 13 0.02% 62.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 5 0.01% 62.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 16 0.02% 62.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 22 0.03% 62.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 16 0.02% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 10 0.01% 62.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 214 0.25% 62.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 6 0.01% 62.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 10 0.01% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 2 0.00% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 11 0.01% 62.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 11 0.01% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 9 0.01% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 5 0.01% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 326 0.38% 63.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 6 0.01% 63.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 11 0.01% 63.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 8 0.01% 63.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 81 0.09% 63.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 14 0.02% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 6 0.01% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 112 0.13% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 3 0.00% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 16 0.02% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 7 0.01% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 131 0.15% 63.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 3 0.00% 63.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 12 0.01% 63.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 12 0.01% 63.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 585 0.68% 64.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 5 0.01% 64.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 9 0.01% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 3 0.00% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 63 0.07% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 2 0.00% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 10 0.01% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 4 0.00% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 9 0.01% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 6 0.01% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 18 0.02% 64.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 6 0.01% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 188 0.22% 64.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 4 0.00% 64.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 8 0.01% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 12 0.01% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 264 0.30% 65.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 3 0.00% 65.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 8 0.01% 65.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 14 0.02% 65.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 15 0.02% 65.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 4 0.00% 65.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 8 0.01% 65.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 3 0.00% 65.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 139 0.16% 65.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7751 1 0.00% 65.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 8 0.01% 65.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 78 0.09% 65.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 7 0.01% 65.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 491 0.57% 66.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 73 0.08% 66.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 137 0.16% 66.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 1 0.00% 66.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 257 0.30% 66.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 183 0.21% 66.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 1 0.00% 66.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 57 0.07% 66.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 569 0.66% 67.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 64 0.07% 67.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 98 0.11% 67.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 68 0.08% 67.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 311 0.36% 68.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 1 0.00% 68.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11655 1 0.00% 68.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 192 0.22% 68.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11911 1 0.00% 68.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12231 1 0.00% 68.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 384 0.44% 68.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12359 1 0.00% 68.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 130 0.15% 69.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 71 0.08% 69.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12935 1 0.00% 69.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 66 0.08% 69.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 202 0.23% 69.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 137 0.16% 69.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 4 0.00% 69.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 238 0.27% 69.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14279 1 0.00% 69.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 326 0.38% 70.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14535 1 0.00% 70.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 131 0.15% 70.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 64 0.07% 70.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15047 1 0.00% 70.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 130 0.15% 70.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 263 0.30% 70.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15431 1 0.00% 70.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 128 0.15% 71.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16007 1 0.00% 71.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 62 0.07% 71.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16327 1 0.00% 71.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 773 0.89% 72.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 60 0.07% 72.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16711 1 0.00% 72.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 129 0.15% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 261 0.30% 72.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 130 0.15% 72.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 64 0.07% 72.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 130 0.15% 72.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 328 0.38% 73.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 242 0.28% 73.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18816-18823 1 0.00% 73.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 2 0.00% 73.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 137 0.16% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19264-19271 1 0.00% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 198 0.23% 73.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19520-19527 2 0.00% 73.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19591 2 0.00% 73.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19648-19655 1 0.00% 73.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 63 0.07% 74.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 69 0.08% 74.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 129 0.15% 74.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 386 0.45% 74.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20608-20615 1 0.00% 74.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20864-20871 1 0.00% 74.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20928-20935 1 0.00% 74.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 194 0.22% 74.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 1 0.00% 74.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 312 0.36% 75.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 67 0.08% 75.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 97 0.11% 75.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 65 0.08% 75.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 568 0.66% 76.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 55 0.06% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22912-22919 2 0.00% 76.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 2 0.00% 76.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 183 0.21% 76.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 257 0.30% 76.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 1 0.00% 76.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 135 0.16% 76.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 73 0.08% 77.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 1 0.00% 77.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 388 0.45% 77.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24640-24647 1 0.00% 77.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 72 0.08% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24896-24903 2 0.00% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 137 0.16% 77.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25152-25159 1 0.00% 77.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25216-25223 1 0.00% 77.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 1 0.00% 77.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 257 0.30% 78.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 182 0.21% 78.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25984-25991 1 0.00% 78.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26048-26055 2 0.00% 78.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 1 0.00% 78.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 55 0.06% 78.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 568 0.66% 78.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 64 0.07% 79.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 98 0.11% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 69 0.08% 79.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 312 0.36% 79.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-27975 1 0.00% 79.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 192 0.22% 79.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28224-28231 1 0.00% 79.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 2 0.00% 79.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 2 0.00% 79.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 387 0.45% 80.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 1 0.00% 80.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 130 0.15% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29056-29063 1 0.00% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 70 0.08% 80.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29376-29383 1 0.00% 80.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 64 0.07% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 199 0.23% 80.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 1 0.00% 80.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 1 0.00% 80.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 138 0.16% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 2 0.00% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 236 0.27% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 324 0.37% 81.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30919 1 0.00% 81.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 131 0.15% 81.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31040-31047 1 0.00% 81.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 65 0.08% 81.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 131 0.15% 81.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 1 0.00% 81.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 262 0.30% 82.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32192-32199 1 0.00% 82.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 128 0.15% 82.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 61 0.07% 82.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 772 0.89% 83.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32832-32839 1 0.00% 83.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32896-32903 1 0.00% 83.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 61 0.07% 83.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 129 0.15% 83.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 2 0.00% 83.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 1 0.00% 83.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33671 2 0.00% 83.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 262 0.30% 83.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 131 0.15% 84.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 64 0.07% 84.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 131 0.15% 84.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 325 0.38% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 236 0.27% 84.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 2 0.00% 84.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 137 0.16% 85.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 198 0.23% 85.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 64 0.07% 85.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36160-36167 1 0.00% 85.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 70 0.08% 85.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 129 0.15% 85.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 384 0.44% 86.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 1 0.00% 86.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 192 0.22% 86.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 312 0.36% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 70 0.08% 86.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 98 0.11% 86.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 64 0.07% 86.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 568 0.66% 87.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 55 0.06% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 1 0.00% 87.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39488-39495 1 0.00% 87.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 182 0.21% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 257 0.30% 88.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 1 0.00% 88.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 136 0.16% 88.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 72 0.08% 88.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 387 0.45% 88.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41024-41031 1 0.00% 88.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 1 0.00% 88.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 73 0.08% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 135 0.16% 89.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 1 0.00% 89.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 257 0.30% 89.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 183 0.21% 89.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 55 0.06% 89.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 569 0.66% 90.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 66 0.08% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 97 0.11% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 68 0.08% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 314 0.36% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 2 0.00% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 1 0.00% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 196 0.23% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 1 0.00% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44992-44999 1 0.00% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 386 0.45% 91.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 132 0.15% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 70 0.08% 91.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 65 0.08% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 1 0.00% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46016-46023 3 0.00% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 199 0.23% 92.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 135 0.16% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46528-46535 1 0.00% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 1 0.00% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 239 0.28% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47040-47047 1 0.00% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 324 0.37% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 131 0.15% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 64 0.07% 93.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 131 0.15% 93.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 260 0.30% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 128 0.15% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48832-48839 1 0.00% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 61 0.07% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 3 0.00% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5274 6.09% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::49344-49351 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49472-49479 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50432-50439 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50695 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50816-50823 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49536-49543 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50183 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50304-50311 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::51072-51079 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51136-51143 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51463 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86834 # Bytes accessed per row activation -system.physmem.totQLat 369633946000 # Total ticks spent queuing -system.physmem.totMemAccLat 463601929750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76423245000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17544738750 # Total ticks spent accessing banks -system.physmem.avgQLat 24183.35 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1147.87 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::51200-51207 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51968-51975 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86636 # Bytes accessed per row activation +system.physmem.totQLat 369559391250 # Total ticks spent queuing +system.physmem.totMemAccLat 463610140000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76423455000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17627293750 # Total ticks spent accessing banks +system.physmem.avgQLat 24178.40 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1153.26 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30331.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 383.72 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30331.67 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 383.71 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.39 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s @@ -592,24 +573,35 @@ system.physmem.busUtilRead 3.00 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 1.05 # Average write queue length when enqueuing -system.physmem.readRowHits 15212610 # Number of row buffer hits during reads -system.physmem.writeRowHits 93178 # Number of row buffer hits during writes +system.physmem.readRowHits 15212838 # Number of row buffer hits during reads +system.physmem.writeRowHits 93174 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads system.physmem.writeRowHitRate 86.29 # Row buffer hit rate for writes -system.physmem.avgGap 158277.83 # Average gap between requests +system.physmem.avgGap 158279.45 # Average gap between requests system.physmem.pageHitRate 99.44 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 1.88 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 54996997 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346113 # Transaction distribution -system.membus.trans_dist::ReadResp 16346116 # Transaction distribution +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54995612 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346068 # Transaction distribution +system.membus.trans_dist::ReadResp 16346071 # Transaction distribution system.membus.trans_dist::WriteReq 763348 # Transaction distribution system.membus.trans_dist::WriteResp 763348 # Transaction distribution -system.membus.trans_dist::Writeback 59151 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4708 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4711 # Transaction distribution -system.membus.trans_dist::ReadExReq 131399 # Transaction distribution -system.membus.trans_dist::ReadExResp 131399 # Transaction distribution +system.membus.trans_dist::Writeback 59135 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4685 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4685 # Transaction distribution +system.membus.trans_dist::ReadExReq 131422 # Transaction distribution +system.membus.trans_dist::ReadExResp 131422 # Transaction distribution system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution system.membus.trans_dist::StoreCondReq 3 # Transaction distribution system.membus.trans_dist::StoreCondResp 3 # Transaction distribution @@ -617,261 +609,255 @@ system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382960 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885919 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885807 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272561 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550305 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34550193 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390337 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16696716 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19094701 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16694284 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19092269 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140205229 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140205229 # Total data (bytes) +system.membus.tot_pkt_size::total 140202797 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140202797 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487741000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487346000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3601000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3636500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17567405000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17566569000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4737923280 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4736419263 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34188515482 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34186627978 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 64379 # number of replacements -system.l2c.tags.tagsinuse 51427.622498 # Cycle average of tags in use -system.l2c.tags.total_refs 1904241 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129768 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.674195 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2512188924000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36951.825179 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.926736 # Average occupied blocks per requestor +system.l2c.tags.replacements 64357 # number of replacements +system.l2c.tags.tagsinuse 51453.251473 # Cycle average of tags in use +system.l2c.tags.total_refs 1905423 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129744 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.686020 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2512210729500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36987.198092 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 19.713113 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4986.850446 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3336.949611 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.947160 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3226.583152 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2894.539843 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.563840 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000289 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 4872.243485 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3313.752357 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 13.584037 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3345.363294 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2901.396724 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.564380 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000301 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.076093 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.050918 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000182 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.049234 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044167 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.784723 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 32603 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 7139 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 505956 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 182118 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30730 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6661 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 464492 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 205502 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1435201 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608382 # number of Writeback hits -system.l2c.Writeback_hits::total 608382 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 22 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 40 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 10 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 15 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 58173 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 54780 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112953 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 32603 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 7139 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 505956 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 240291 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30730 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 464492 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 260282 # number of demand (read+write) hits -system.l2c.demand_hits::total 1548154 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 32603 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 7139 # number of overall hits -system.l2c.overall_hits::cpu0.inst 505956 # number of overall hits -system.l2c.overall_hits::cpu0.data 240291 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30730 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6661 # number of overall hits -system.l2c.overall_hits::cpu1.inst 464492 # number of overall hits -system.l2c.overall_hits::cpu1.data 260282 # number of overall hits -system.l2c.overall_hits::total 1548154 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 27 # number of ReadReq misses +system.l2c.tags.occ_percent::cpu0.inst 0.074345 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.050564 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000207 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.051046 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.044272 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.785114 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 32950 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 7107 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 506567 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 181823 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30566 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6814 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 464544 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 205967 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1436338 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608494 # number of Writeback hits +system.l2c.Writeback_hits::total 608494 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 34 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 4 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 58298 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 54682 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112980 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 32950 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 7107 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 506567 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 240121 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30566 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6814 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 464544 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 260649 # number of demand (read+write) hits +system.l2c.demand_hits::total 1549318 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 32950 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 7107 # number of overall hits +system.l2c.overall_hits::cpu0.inst 506567 # number of overall hits +system.l2c.overall_hits::cpu0.data 240121 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30566 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6814 # number of overall hits +system.l2c.overall_hits::cpu1.inst 464544 # number of overall hits +system.l2c.overall_hits::cpu1.data 260649 # number of overall hits +system.l2c.overall_hits::total 1549318 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 29 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7825 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6187 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 14 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4565 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4551 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23171 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1285 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1631 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2916 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 68474 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 64717 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133191 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 7681 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6151 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 16 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 4714 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4533 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23126 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1282 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1636 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2918 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 67869 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 65320 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133189 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 29 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7825 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 74661 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 14 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4565 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 69268 # number of demand (read+write) misses -system.l2c.demand_misses::total 156362 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 27 # number of overall misses +system.l2c.demand_misses::cpu0.inst 7681 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 74020 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 4714 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 69853 # number of demand (read+write) misses +system.l2c.demand_misses::total 156315 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 29 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7825 # number of overall misses -system.l2c.overall_misses::cpu0.data 74661 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 14 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4565 # number of overall misses -system.l2c.overall_misses::cpu1.data 69268 # number of overall misses -system.l2c.overall_misses::total 156362 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2234250 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu0.inst 7681 # number of overall misses +system.l2c.overall_misses::cpu0.data 74020 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses +system.l2c.overall_misses::cpu1.inst 4714 # number of overall misses +system.l2c.overall_misses::cpu1.data 69853 # number of overall misses +system.l2c.overall_misses::total 156315 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2207500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 158000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 566532750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 458261500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1111500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 342566000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 354437999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1725301999 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 254989 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 187492 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 442481 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5097311886 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4928859322 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10026171208 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 2234250 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 559087000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 461077500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1541500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 349988250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 349614499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1723674249 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 255989 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 162493 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 418482 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5047283901 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4980536832 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10027820733 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 2207500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 158000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 566532750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 5555573386 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1111500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 342566000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 5283297321 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 11751473207 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 2234250 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 559087000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 5508361401 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1541500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 349988250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 5330151331 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 11751494982 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 2207500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 158000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 566532750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 5555573386 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1111500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 342566000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 5283297321 # number of overall miss cycles -system.l2c.overall_miss_latency::total 11751473207 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 32630 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 7141 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 513781 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 188305 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 30744 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6661 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 469057 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 210053 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1458372 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 608382 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 608382 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1307 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1649 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2956 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 6 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 12 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 18 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 126647 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 119497 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246144 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 32630 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 7141 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 513781 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 314952 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 30744 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6661 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 469057 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 329550 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1704516 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 32630 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7141 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 513781 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 314952 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 30744 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6661 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 469057 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 329550 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1704516 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000827 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000280 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015230 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.032856 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000455 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009732 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.021666 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015888 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.983168 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989084 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.986468 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.166667 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.166667 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.166667 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.540668 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.541578 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541110 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000827 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000280 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015230 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.237055 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000455 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009732 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.210190 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.091734 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000827 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000280 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015230 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.237055 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000455 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009732 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.210190 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.091734 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 82750 # average ReadReq miss latency +system.l2c.overall_miss_latency::cpu0.inst 559087000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 5508361401 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1541500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 349988250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 5330151331 # number of overall miss cycles +system.l2c.overall_miss_latency::total 11751494982 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 32979 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 7109 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 514248 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 187974 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 30582 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6814 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 469258 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 210500 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1459464 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 608494 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 608494 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1300 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1652 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2952 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 4 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 6 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 126167 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 120002 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246169 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 32979 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 7109 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 514248 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 314141 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 30582 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6814 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 469258 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 330502 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1705633 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 32979 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 7109 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 514248 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 314141 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 30582 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6814 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 469258 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 330502 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1705633 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000879 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000281 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014936 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.032723 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000523 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010046 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.021534 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015846 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.986154 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990315 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.988482 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.537930 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.544324 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541047 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000879 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000281 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014936 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.235627 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000523 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010046 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.211354 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.091646 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000879 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000281 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014936 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.235627 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000523 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010046 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.211354 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.091646 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 76120.689655 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 79000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72400.351438 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 74068.449976 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79392.857143 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75041.840088 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 77881.344540 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 74459.539899 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 198.435019 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 114.955242 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 151.742455 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74441.567398 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76160.194725 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 75276.641875 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 82750 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72788.308814 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 74959.762640 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 96343.750000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74244.431481 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 77126.516435 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 74534.041728 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 199.679407 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 99.323350 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 143.413982 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74368.031075 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76248.267483 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 75290.157093 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 76120.689655 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 79000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 72400.351438 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 74410.647942 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79392.857143 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 75041.840088 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 76273.276563 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 75155.557022 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 82750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 72788.308814 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 74417.203472 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 96343.750000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 74244.431481 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 76305.260060 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 75178.293715 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 76120.689655 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 79000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 72400.351438 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 74410.647942 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79392.857143 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 75041.840088 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 76273.276563 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 75155.557022 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 72788.308814 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 74417.203472 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 96343.750000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 74244.431481 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 76305.260060 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 75178.293715 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -880,170 +866,158 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 59151 # number of writebacks -system.l2c.writebacks::total 59151 # number of writebacks +system.l2c.writebacks::writebacks 59135 # number of writebacks +system.l2c.writebacks::total 59135 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 42 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 44 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 25 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 23 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 42 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 44 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 25 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 23 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 42 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 44 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 25 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 23 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 79 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 27 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 29 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 7820 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6145 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 14 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 4558 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4526 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23092 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1285 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1631 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2916 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 2 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 68474 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 64717 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133191 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 27 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 7676 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6107 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 16 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 4707 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4510 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23047 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1282 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1636 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2918 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 67869 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 65320 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133189 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 29 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 7820 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 74619 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 14 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 4558 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 69243 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 156283 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 27 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 7676 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 73976 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 16 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 4707 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 69830 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 156236 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 29 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 7820 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 74619 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 14 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 4558 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 69243 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 156283 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1902250 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu0.inst 7676 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 73976 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 16 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 4707 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 69830 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 156236 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1848500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 133500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 467782250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 379156500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 939000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 284899750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 296279749 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1431092999 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 12851285 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 16316631 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 29167916 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 10001 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20002 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4242388114 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4120773678 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8363161792 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1902250 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 462156500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 381785750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1343500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 290452750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 292088999 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1429809499 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 12821282 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 16367635 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 29188917 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4199900099 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4165909168 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8365809267 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1848500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 133500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 467782250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 4621544614 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 939000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 284899750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 4417053427 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 9794254791 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1902250 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 462156500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 4581685849 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1343500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 290452750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 4457998167 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 9795618766 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1848500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 133500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 467782250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 4621544614 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 939000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 284899750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 4417053427 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 9794254791 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 462156500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 4581685849 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1343500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 290452750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4457998167 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9795618766 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6012999 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84576136750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82361165750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166943315499 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8951295259 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8415675500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 17366970759 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84589545750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82347341250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166942899999 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8959860803 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8414119000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17373979803 # number of WriteReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 116250 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 116250 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 60000 # number of StoreCondReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::total 60000 # number of StoreCondReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6012999 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 93527432009 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 90776841250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 184310286258 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000827 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000280 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015220 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.032633 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009717 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.021547 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015834 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.983168 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989084 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.986468 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.166667 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.166667 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.166667 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540668 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.541578 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541110 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000827 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000280 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015220 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.236922 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009717 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.210114 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.091688 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000827 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000280 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015220 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.236922 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009717 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.210114 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091688 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 70453.703704 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 93549406553 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 90761460250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184316879802 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000879 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000281 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014927 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.032489 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000523 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010031 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.021425 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015791 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.986154 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.990315 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.988482 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.537930 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.544324 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541047 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000879 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000281 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014927 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.235487 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000523 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010031 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.211285 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091600 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000879 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000281 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014927 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.235487 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000523 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010031 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.211285 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091600 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 63741.379310 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59818.702046 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61701.627339 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67071.428571 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65461.720946 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61973.540577 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60207.985930 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62516.088096 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 83968.750000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61706.554068 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64764.744789 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62038.855339 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.065604 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.714678 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61956.189415 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63673.743808 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 62790.742558 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70453.703704 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.666870 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10003.055860 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61882.451473 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63776.931537 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62811.563019 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63741.379310 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59818.702046 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61935.225800 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67071.428571 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63790.613159 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 62669.994760 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70453.703704 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60207.985930 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61934.760585 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 83968.750000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61706.554068 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63840.729873 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62697.577805 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63741.379310 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59818.702046 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61935.225800 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67071.428571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62505.430013 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63790.613159 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 62669.994760 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60207.985930 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61934.760585 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 83968.750000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61706.554068 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63840.729873 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62697.577805 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -1066,43 +1040,43 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58456334 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2676393 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2676395 # Transaction distribution +system.toL2Bus.throughput 58478558 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2677542 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2677544 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 608382 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2956 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2974 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246144 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246144 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 608494 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2952 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2958 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246169 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246169 # Transaction distribution system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967115 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798220 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37803 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149157 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7952295 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62908992 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85598765 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55208 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253496 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148816461 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148816461 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 207744 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4964319701 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1968408 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798582 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 38031 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149645 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7954666 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62951744 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85614957 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55692 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 254244 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148876637 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148876637 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 205392 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4965399712 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4431802148 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4434611165 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4486267320 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4486677044 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24046904 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24152407 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86228845 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86557036 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48444532 # Throughput (bytes/s) +system.iobus.throughput 48444152 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16322136 # Transaction distribution system.iobus.trans_dist::ReadResp 16322136 # Transaction distribution system.iobus.trans_dist::WriteReq 8160 # Transaction distribution @@ -1212,40 +1186,40 @@ system.iobus.reqLayer25.occupancy 15138816000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41492591518 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41494630022 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu0.branchPred.lookups 7178846 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5689563 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 376334 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4735029 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3823898 # Number of BTB hits +system.cpu0.branchPred.lookups 7183590 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5694303 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 377290 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4721847 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3824688 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 80.757647 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 708733 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39412 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 80.999829 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 708757 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39349 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25686724 # DTB read hits -system.cpu0.dtb.read_misses 37672 # DTB read misses -system.cpu0.dtb.write_hits 5882199 # DTB write hits -system.cpu0.dtb.write_misses 9157 # DTB write misses +system.cpu0.dtb.read_hits 25676392 # DTB read hits +system.cpu0.dtb.read_misses 38073 # DTB read misses +system.cpu0.dtb.write_hits 5871403 # DTB write hits +system.cpu0.dtb.write_misses 9193 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5402 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1359 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 227 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5420 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1344 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 238 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 602 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25724396 # DTB read accesses -system.cpu0.dtb.write_accesses 5891356 # DTB write accesses +system.cpu0.dtb.perms_faults 585 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25714465 # DTB read accesses +system.cpu0.dtb.write_accesses 5880596 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31568923 # DTB hits -system.cpu0.dtb.misses 46829 # DTB misses -system.cpu0.dtb.accesses 31615752 # DTB accesses -system.cpu0.itb.inst_hits 5794960 # ITB inst hits -system.cpu0.itb.inst_misses 6979 # ITB inst misses +system.cpu0.dtb.hits 31547795 # DTB hits +system.cpu0.dtb.misses 47266 # DTB misses +system.cpu0.dtb.accesses 31595061 # DTB accesses +system.cpu0.itb.inst_hits 5793609 # ITB inst hits +system.cpu0.itb.inst_misses 6965 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1254,114 +1228,114 @@ system.cpu0.itb.flush_tlb 257 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2537 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2542 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1462 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1475 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5801939 # ITB inst accesses -system.cpu0.itb.hits 5794960 # DTB hits -system.cpu0.itb.misses 6979 # DTB misses -system.cpu0.itb.accesses 5801939 # DTB accesses -system.cpu0.numCycles 241329954 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5800574 # ITB inst accesses +system.cpu0.itb.hits 5793609 # DTB hits +system.cpu0.itb.misses 6965 # DTB misses +system.cpu0.itb.accesses 5800574 # DTB accesses +system.cpu0.numCycles 241355643 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15402359 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 44612176 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7178846 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4532631 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10046821 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2409329 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 81802 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 48777724 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1779 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1966 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 42894 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1416575 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 470 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5793020 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 368373 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3163 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77432013 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.722773 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.070911 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15408312 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 44581736 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7183590 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4533445 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10042154 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2412494 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 81949 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 48815807 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1726 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1993 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 42608 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1411972 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 385 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5791670 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 368874 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3149 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77468964 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.722040 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.069743 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67393349 87.04% 87.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 663167 0.86% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 850708 1.10% 88.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1161944 1.50% 90.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1070979 1.38% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 538004 0.69% 92.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1258402 1.63% 94.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 372673 0.48% 94.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4122787 5.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67434698 87.05% 87.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 662922 0.86% 87.90% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 849826 1.10% 89.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1158615 1.50% 90.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1071303 1.38% 91.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 540404 0.70% 92.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1264103 1.63% 94.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 371341 0.48% 94.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4115752 5.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77432013 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.029747 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.184860 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16324291 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49901037 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9152885 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 482910 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1568783 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 985989 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 93507 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 53239353 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 312067 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1568783 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17193647 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 20516369 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 26371209 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8691714 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3088262 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 50703360 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7236 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 484563 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2089605 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 237 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 52223867 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 231534090 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 214067803 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5431 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 38086867 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14136999 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 416413 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 366902 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6391113 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9801074 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6698586 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1023553 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1394670 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 47085778 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 981191 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 61028996 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 87181 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9766291 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24255892 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256976 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77432013 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.788162 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.509612 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77468964 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.029764 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.184714 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16332862 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49931887 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9147459 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 483482 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1571127 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 985970 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 93586 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 53203424 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 313882 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1571127 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17204608 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 20551297 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 26349401 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8685161 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3105311 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 50667470 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7242 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 502803 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2087731 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 194 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 52194379 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 231353972 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 213903823 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5361 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 38031727 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14162651 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 415813 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 366209 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6409920 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9794680 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6688167 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1031152 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1299354 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 47050561 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 979447 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 60972564 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 88288 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9787230 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24359943 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256705 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77468964 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.787058 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.508592 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 55649099 71.87% 71.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6737778 8.70% 80.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3435441 4.44% 85.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2925983 3.78% 88.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6185685 7.99% 96.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1437832 1.86% 98.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 773159 1.00% 99.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 224755 0.29% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 62281 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 55694568 71.89% 71.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6744950 8.71% 80.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3431902 4.43% 85.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2928703 3.78% 88.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6175861 7.97% 96.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1433177 1.85% 98.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 773017 1.00% 99.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 224018 0.29% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 62768 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77432013 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77468964 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 29912 0.67% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 30016 0.67% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 1 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available @@ -1390,504 +1364,504 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4221653 94.70% 95.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 206360 4.63% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4221900 94.67% 95.34% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 207684 4.66% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 165947 0.27% 0.27% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 28282024 46.34% 46.61% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46844 0.08% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1271 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26348641 43.17% 89.87% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6184237 10.13% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 165809 0.27% 0.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 28246973 46.33% 46.60% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46806 0.08% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1267 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26338371 43.20% 89.88% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6173305 10.12% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 61028996 # Type of FU issued -system.cpu0.iq.rate 0.252886 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4457926 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.073046 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 204069737 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 57841875 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 42095336 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12029 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6474 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5396 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 65314591 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6384 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 305188 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 60972564 # Type of FU issued +system.cpu0.iq.rate 0.252625 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4459601 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.073141 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 203996977 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 57825737 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 42036875 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12074 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6420 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5360 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 65259915 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6441 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 303470 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2103037 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3902 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15671 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 837358 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2107176 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3913 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15490 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 838182 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17232684 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 348213 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17232343 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 348683 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1568783 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15829049 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 237688 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 48167223 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 105126 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9801074 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6698586 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 691561 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 54422 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4242 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15671 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 182031 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 143561 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 325592 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 59970791 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26024613 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1058205 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1571127 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15861030 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 237452 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 48130825 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 105592 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9794680 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6688167 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 690516 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 54721 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4205 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15490 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 181987 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 144371 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 326358 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 59914186 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26012956 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1058378 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 100254 # number of nop insts executed -system.cpu0.iew.exec_refs 32151728 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5674244 # Number of branches executed -system.cpu0.iew.exec_stores 6127115 # Number of stores executed -system.cpu0.iew.exec_rate 0.248501 # Inst execution rate -system.cpu0.iew.wb_sent 59482820 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 42100732 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 22797313 # num instructions producing a value -system.cpu0.iew.wb_consumers 41683102 # num instructions consuming a value +system.cpu0.iew.exec_nop 100817 # number of nop insts executed +system.cpu0.iew.exec_refs 32128938 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5674429 # Number of branches executed +system.cpu0.iew.exec_stores 6115982 # Number of stores executed +system.cpu0.iew.exec_rate 0.248240 # Inst execution rate +system.cpu0.iew.wb_sent 59424173 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 42042235 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 22754717 # num instructions producing a value +system.cpu0.iew.wb_consumers 41618983 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.174453 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.546920 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.174192 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.546739 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 9635326 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 724215 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 284304 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75863230 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.501725 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.477269 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9657152 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 722742 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 285161 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75897837 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.500741 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.473402 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 62300247 82.12% 82.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6632163 8.74% 90.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1905948 2.51% 93.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1063803 1.40% 94.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 963459 1.27% 96.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 539688 0.71% 96.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 720050 0.95% 97.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 348558 0.46% 98.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1389314 1.83% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 62326931 82.12% 82.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6623929 8.73% 90.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1927651 2.54% 93.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1062809 1.40% 94.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 977806 1.29% 96.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 537572 0.71% 96.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 721191 0.95% 97.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 348340 0.46% 98.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1371608 1.81% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75863230 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 29321704 # Number of instructions committed -system.cpu0.commit.committedOps 38062462 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75897837 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 29270698 # Number of instructions committed +system.cpu0.commit.committedOps 38005132 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13559265 # Number of memory references committed -system.cpu0.commit.loads 7698037 # Number of loads committed -system.cpu0.commit.membars 204059 # Number of memory barriers committed -system.cpu0.commit.branches 4889328 # Number of branches committed -system.cpu0.commit.fp_insts 5354 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 33742241 # Number of committed integer instructions. -system.cpu0.commit.function_calls 497179 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1389314 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13537489 # Number of memory references committed +system.cpu0.commit.loads 7687504 # Number of loads committed +system.cpu0.commit.membars 203418 # Number of memory barriers committed +system.cpu0.commit.branches 4891612 # Number of branches committed +system.cpu0.commit.fp_insts 5306 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 33685063 # Number of committed integer instructions. +system.cpu0.commit.function_calls 497791 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1371608 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 121250209 # The number of ROB reads -system.cpu0.rob.rob_writes 97007351 # The number of ROB writes -system.cpu0.timesIdled 906901 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 163897941 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2251401803 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 29254206 # Number of Instructions Simulated -system.cpu0.committedOps 37994964 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 29254206 # Number of Instructions Simulated -system.cpu0.cpi 8.249410 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.249410 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.121221 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.121221 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 271506841 # number of integer regfile reads -system.cpu0.int_regfile_writes 42814380 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22646 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19918 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15055897 # number of misc regfile reads -system.cpu0.misc_regfile_writes 404161 # number of misc regfile writes -system.cpu0.icache.tags.replacements 983492 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.574238 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10516196 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 984004 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.687148 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6986136250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 318.901478 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 192.672760 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.622854 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.376314 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999168 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5235281 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5280915 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10516196 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5235281 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5280915 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10516196 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5235281 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5280915 # number of overall hits -system.cpu0.icache.overall_hits::total 10516196 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 557620 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 507749 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065369 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 557620 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 507749 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065369 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 557620 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 507749 # number of overall misses -system.cpu0.icache.overall_misses::total 1065369 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7715888650 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6834076460 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14549965110 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7715888650 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6834076460 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14549965110 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7715888650 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6834076460 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14549965110 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5792901 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5788664 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11581565 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5792901 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5788664 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11581565 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5792901 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5788664 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11581565 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.096259 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087714 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.091988 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.096259 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087714 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.091988 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.096259 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087714 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.091988 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13837.180607 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13459.556710 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13657.207137 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13837.180607 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13459.556710 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13657.207137 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13837.180607 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13459.556710 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13657.207137 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6518 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 829 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 410 # number of cycles access was blocked +system.cpu0.rob.rob_reads 121269057 # The number of ROB reads +system.cpu0.rob.rob_writes 96938789 # The number of ROB writes +system.cpu0.timesIdled 907351 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 163886679 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2251360755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 29203197 # Number of Instructions Simulated +system.cpu0.committedOps 37937631 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 29203197 # Number of Instructions Simulated +system.cpu0.cpi 8.264699 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.264699 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.120997 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.120997 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 271224247 # number of integer regfile reads +system.cpu0.int_regfile_writes 42758050 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22657 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19930 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15040337 # number of misc regfile reads +system.cpu0.misc_regfile_writes 403311 # number of misc regfile writes +system.cpu0.icache.tags.replacements 984140 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.573239 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 10515740 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 984652 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.679651 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7012159250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 319.827324 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 191.745915 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.624663 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.374504 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999166 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5233615 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5282125 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 10515740 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5233615 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5282125 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 10515740 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5233615 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5282125 # number of overall hits +system.cpu0.icache.overall_hits::total 10515740 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 557933 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 508279 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1066212 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 557933 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 508279 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1066212 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 557933 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 508279 # number of overall misses +system.cpu0.icache.overall_misses::total 1066212 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7711361387 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6850959748 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14562321135 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7711361387 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6850959748 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14562321135 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7711361387 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6850959748 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14562321135 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5791548 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5790404 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 11581952 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5791548 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5790404 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11581952 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5791548 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5790404 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 11581952 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.096336 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087780 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.092058 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.096336 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087780 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.092058 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.096336 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087780 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.092058 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13821.303610 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13478.738543 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13657.997786 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13821.303610 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13478.738543 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13657.997786 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13821.303610 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13478.738543 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13657.997786 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6730 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 450 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 431 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.897561 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 829 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.614849 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 450 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43249 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 38074 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 81323 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 43249 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 38074 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 81323 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 43249 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 38074 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 81323 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 514371 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 469675 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 984046 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 514371 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 469675 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 984046 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 514371 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 469675 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 984046 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6258994404 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5567069659 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11826064063 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6258994404 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5567069659 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11826064063 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6258994404 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5567069659 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11826064063 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43117 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 38424 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 81541 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 43117 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 38424 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 81541 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 43117 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 38424 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 81541 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 514816 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 469855 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 984671 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 514816 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 469855 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 984671 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 514816 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 469855 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 984671 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6258274414 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5575421883 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11833696297 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6258274414 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5575421883 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11833696297 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6258274414 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5575421883 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11833696297 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8426500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8426500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8426500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 8426500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.088793 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081137 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084967 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.088793 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.081137 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.084967 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.088793 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.081137 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.084967 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12017.795980 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12017.795980 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12168.248995 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11853.025303 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12017.795980 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.088891 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081144 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085018 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.088891 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.081144 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.085018 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.088891 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.081144 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.085018 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12156.332387 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11866.260619 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12017.918977 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12156.332387 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11866.260619 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12017.918977 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12156.332387 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11866.260619 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12017.918977 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 643990 # number of replacements +system.cpu0.dcache.tags.replacements 644131 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.993324 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21534082 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 644502 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.411971 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 21534637 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 644643 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.405524 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 43026250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 255.795317 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 256.198007 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.499600 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.500387 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.706394 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 257.286930 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497473 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.502514 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6836118 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6942659 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13778777 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3601868 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3659456 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7261324 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114429 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 128738 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243167 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 116989 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 130670 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247659 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10437986 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10602115 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21040101 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10437986 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10602115 # number of overall hits -system.cpu0.dcache.overall_hits::total 21040101 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 327145 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 421730 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 748875 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1520256 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1442024 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2962280 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7436 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6109 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13545 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 12 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1847401 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1863754 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3711155 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1847401 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1863754 # number of overall misses -system.cpu0.dcache.overall_misses::total 3711155 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5258794781 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6175311803 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11434106584 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76116558084 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 73496602051 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 149613160135 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 106253499 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 82007996 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 188261495 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 90501 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 181002 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 271503 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 81375352865 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 79671913854 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 161047266719 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 81375352865 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 79671913854 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 161047266719 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7163263 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 7364389 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14527652 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5122124 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5101480 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10223604 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 121865 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 134847 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 256712 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 116995 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 130682 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247677 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12285387 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12465869 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24751256 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12285387 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12465869 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24751256 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.045670 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057266 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051548 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.296802 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.282668 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289749 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061018 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045303 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052763 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000051 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000092 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000073 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.150374 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.149509 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149938 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.150374 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.149509 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149938 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16074.813251 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14642.808913 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15268.378012 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50068.250403 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 50967.669089 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50506.083198 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14289.066568 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13424.127680 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13898.966039 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15083.500000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15083.500000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15083.500000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 44048.559498 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 42748.084701 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 43395.456864 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 44048.559498 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 42748.084701 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 43395.456864 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 38322 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 25151 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3482 # number of cycles access was blocked +system.cpu0.dcache.ReadReq_hits::cpu0.data 6830201 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6949651 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13779852 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3598843 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3661860 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7260703 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114028 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 129247 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243275 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 116593 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 131076 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247669 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10429044 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10611511 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 21040555 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10429044 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10611511 # number of overall hits +system.cpu0.dcache.overall_hits::total 21040555 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 324834 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 424795 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 749629 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1512773 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1450071 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2962844 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7425 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6132 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13557 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 4 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1837607 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1874866 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3712473 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1837607 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1874866 # number of overall misses +system.cpu0.dcache.overall_misses::total 3712473 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5222562191 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6193158591 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11415720782 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 75296679857 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 74371858974 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 149668538831 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 106104748 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 82161747 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 188266495 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 26000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 52000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 78000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 80519242048 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 80565017565 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 161084259613 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 80519242048 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 80565017565 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 161084259613 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7155035 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 7374446 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 14529481 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5111616 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5111931 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10223547 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 121453 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 135379 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 256832 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 116595 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 131080 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247675 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12266651 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 12486377 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24753028 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12266651 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 12486377 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24753028 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.045399 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057604 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.051594 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.295948 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.283664 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.289806 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061135 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045295 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052785 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000017 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000031 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000024 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.149805 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.150153 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.149981 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.149805 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.150153 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.149981 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16077.634087 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14579.170167 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15228.494071 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49773.944840 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 51288.425859 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50515.160039 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14290.201751 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13398.849804 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13887.032161 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43817.444126 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 42971.080368 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 43390.015123 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43817.444126 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 42971.080368 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 43390.015123 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 36582 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 25832 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3477 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 293 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11.005744 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 85.839590 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.521139 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 88.163823 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 608382 # number of writebacks -system.cpu0.dcache.writebacks::total 608382 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 145500 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 217105 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 362605 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1392355 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1320933 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2713288 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 723 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 626 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1349 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1537855 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1538038 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3075893 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1537855 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1538038 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3075893 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 181645 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 204625 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 386270 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 127901 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 121091 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 248992 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6713 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5483 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12196 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 12 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 18 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 309546 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 325716 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 635262 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 309546 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 325716 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 635262 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2539210775 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2715181297 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5254392072 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5938244941 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5721716845 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11659961786 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 84451251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63563504 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148014755 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 78499 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 156998 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 235497 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8477455716 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8436898142 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16914353858 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8477455716 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 8436898142 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16914353858 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 92366768250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 89963955251 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182330723501 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13704367995 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13062365000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26766732995 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.writebacks::writebacks 608494 # number of writebacks +system.cpu0.dcache.writebacks::total 608494 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 143520 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 219714 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 363234 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1385356 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1328479 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2713835 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 715 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 651 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1366 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1528876 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1548193 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3077069 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1528876 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1548193 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3077069 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 181314 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 205081 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 386395 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 127417 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 121592 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249009 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6710 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5481 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12191 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 4 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 308731 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 326673 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 635404 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 308731 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 326673 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 635404 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2537114094 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2716244009 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5253358103 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5888392200 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5776496365 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11664888565 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 84437751 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63633003 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148070754 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 66000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8425506294 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8492740374 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16918246668 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8425506294 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 8492740374 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16918246668 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 92381073251 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 89949254752 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182330328003 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13713085264 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13059234413 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26772319677 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 155750 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 155750 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106071136245 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103026320251 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209097456496 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025358 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027786 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026589 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024970 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023736 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055086 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040661 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047508 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000051 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000092 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000073 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025196 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025666 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025196 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025666 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13978.974235 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13269.059484 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13602.899713 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46428.448104 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47251.379913 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46828.660302 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12580.254879 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11592.833121 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12136.336094 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13083.166667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 13083.166667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13083.166667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27386.739664 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25902.621124 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26625.791969 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27386.739664 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25902.621124 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26625.791969 # average overall mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106094158515 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103008489165 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209102647680 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025341 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027810 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026594 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024927 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023786 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024356 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055248 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040486 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047467 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000017 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000031 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000024 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025168 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026162 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025670 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025168 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026162 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025670 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13992.929912 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13244.737489 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13595.823194 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46213.552352 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47507.207423 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46845.248826 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12583.867511 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11609.743295 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12145.907145 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27290.768643 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25997.680782 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26625.968153 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27290.768643 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25997.680782 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26625.968153 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1902,38 +1876,38 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7299586 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5849815 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 347289 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4589899 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3862662 # Number of BTB hits +system.cpu1.branchPred.lookups 7296861 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5846678 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 347662 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4742078 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3857406 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 84.155708 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 691728 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34987 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 81.344212 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 691724 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 35172 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25535708 # DTB read hits -system.cpu1.dtb.read_misses 37819 # DTB read misses -system.cpu1.dtb.write_hits 5832824 # DTB write hits -system.cpu1.dtb.write_misses 9748 # DTB write misses +system.cpu1.dtb.read_hits 25545961 # DTB read hits +system.cpu1.dtb.read_misses 37652 # DTB read misses +system.cpu1.dtb.write_hits 5843070 # DTB write hits +system.cpu1.dtb.write_misses 9833 # DTB write misses system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5631 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2100 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 278 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5607 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2149 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 268 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 694 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25573527 # DTB read accesses -system.cpu1.dtb.write_accesses 5842572 # DTB write accesses +system.cpu1.dtb.perms_faults 680 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25583613 # DTB read accesses +system.cpu1.dtb.write_accesses 5852903 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31368532 # DTB hits -system.cpu1.dtb.misses 47567 # DTB misses -system.cpu1.dtb.accesses 31416099 # DTB accesses -system.cpu1.itb.inst_hits 5790816 # ITB inst hits -system.cpu1.itb.inst_misses 7158 # ITB inst misses +system.cpu1.dtb.hits 31389031 # DTB hits +system.cpu1.dtb.misses 47485 # DTB misses +system.cpu1.dtb.accesses 31436516 # DTB accesses +system.cpu1.itb.inst_hits 5792513 # ITB inst hits +system.cpu1.itb.inst_misses 7242 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1942,284 +1916,284 @@ system.cpu1.itb.flush_tlb 255 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2684 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2667 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1580 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1547 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5797974 # ITB inst accesses -system.cpu1.itb.hits 5790816 # DTB hits -system.cpu1.itb.misses 7158 # DTB misses -system.cpu1.itb.accesses 5797974 # DTB accesses -system.cpu1.numCycles 235384601 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5799755 # ITB inst accesses +system.cpu1.itb.hits 5792513 # DTB hits +system.cpu1.itb.misses 7242 # DTB misses +system.cpu1.itb.accesses 5799755 # DTB accesses +system.cpu1.numCycles 235437063 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14589178 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46084175 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7299586 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4554390 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10179964 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2322435 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 82610 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 48394674 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1151 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1760 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 51069 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1300436 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5788667 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 351586 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2955 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 76205210 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.749083 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.107109 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14594322 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46143705 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7296861 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4549130 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10187153 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2325105 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 84075 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 48390355 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1006 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1773 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 50802 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1299927 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 134 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5790405 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 352119 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3045 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76215873 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.749895 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.108619 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66032287 86.65% 86.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 647062 0.85% 87.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 866139 1.14% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1142625 1.50% 90.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1039142 1.36% 91.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 573208 0.75% 92.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1303078 1.71% 93.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 377648 0.50% 94.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4224021 5.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66035998 86.64% 86.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 646269 0.85% 87.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 866115 1.14% 88.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1144603 1.50% 90.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1038380 1.36% 91.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 570616 0.75% 92.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1298592 1.70% 93.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 378941 0.50% 94.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4236359 5.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 76205210 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.031011 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.195782 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15588837 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 49317422 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9252055 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 521656 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1523167 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 986244 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 83403 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54452083 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 278013 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1523167 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16469267 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19674049 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 26510190 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8818021 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3208448 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51956781 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 13421 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 604219 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2079670 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 451 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 54191440 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 237039699 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 219510796 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 4998 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 40313487 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13877953 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 415796 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 370913 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6599828 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9995387 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6641278 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 924791 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1180275 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 48354458 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1004264 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 62036555 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 93414 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9463744 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 23885542 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 245582 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 76205210 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.814072 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.522064 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76215873 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030993 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.195992 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15595502 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 49311936 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9258524 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 522439 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1525385 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 986467 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 83299 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54522655 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 277301 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1525385 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16476975 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19655955 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 26515105 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8823591 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3216801 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 52024243 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 13429 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 607553 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2083322 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 488 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 54254654 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 237368382 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 219812592 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5012 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 40368418 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13886236 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 416636 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 371803 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6618695 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 10010762 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6654363 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 928897 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1221940 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 48420965 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1005597 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 62096685 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94311 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9477685 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 23931706 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 245448 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76215873 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.814747 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.522121 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53886192 70.71% 70.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6968313 9.14% 79.86% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3603419 4.73% 84.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3067011 4.02% 88.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6180907 8.11% 96.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1416351 1.86% 98.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 790440 1.04% 99.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 228268 0.30% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 64309 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53862159 70.67% 70.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6987914 9.17% 79.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3609115 4.74% 84.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3073312 4.03% 88.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6185840 8.12% 96.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1415029 1.86% 98.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 789705 1.04% 99.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 228522 0.30% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 64277 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 76205210 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76215873 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29954 0.68% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 6 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4154847 94.70% 95.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 202692 4.62% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 30122 0.69% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 4 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4155854 94.74% 95.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 200598 4.57% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 197719 0.32% 0.32% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 29431617 47.44% 47.76% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46723 0.08% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 843 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.84% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26206761 42.24% 90.08% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6152865 9.92% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 197857 0.32% 0.32% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 29468242 47.46% 47.77% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46687 0.08% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 846 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.85% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26218549 42.22% 90.07% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6164475 9.93% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 62036555 # Type of FU issued -system.cpu1.iq.rate 0.263554 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4387499 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.070724 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 204795562 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 58831312 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 43493604 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11047 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6062 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4926 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 66220464 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5871 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 319800 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 62096685 # Type of FU issued +system.cpu1.iq.rate 0.263751 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4386578 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.070641 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 204926211 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 58913069 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 43552448 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11222 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6050 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4957 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 66279422 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5984 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 320383 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2036379 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2915 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15518 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 769053 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2041284 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2958 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 15466 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 770955 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16877667 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 333288 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16877302 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 331906 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1523167 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14985510 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 225691 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 49480647 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 96107 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9995387 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6641278 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 719443 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 50947 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6143 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15518 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 171517 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 135143 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 306660 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 61000330 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25886068 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1036225 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1525385 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14957873 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 224833 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 49549209 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 95185 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 10010762 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6654363 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 720304 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 50705 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4281 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 15466 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 171203 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 135670 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 306873 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 61058870 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25897367 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1037815 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 121925 # number of nop insts executed -system.cpu1.iew.exec_refs 31986182 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5823905 # Number of branches executed -system.cpu1.iew.exec_stores 6100114 # Number of stores executed -system.cpu1.iew.exec_rate 0.259152 # Inst execution rate -system.cpu1.iew.wb_sent 60530443 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 43498530 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 24164344 # num instructions producing a value -system.cpu1.iew.wb_consumers 44485345 # num instructions consuming a value +system.cpu1.iew.exec_nop 122647 # number of nop insts executed +system.cpu1.iew.exec_refs 32008147 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5821795 # Number of branches executed +system.cpu1.iew.exec_stores 6110780 # Number of stores executed +system.cpu1.iew.exec_rate 0.259343 # Inst execution rate +system.cpu1.iew.wb_sent 60589807 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 43557405 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 24211075 # num instructions producing a value +system.cpu1.iew.wb_consumers 44594441 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.184798 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.543198 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.185007 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.542917 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9351616 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 758682 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 265186 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 74682043 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.531552 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.520144 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9363446 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 760149 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 265641 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 74690488 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.532256 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.520816 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60574973 81.11% 81.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6925092 9.27% 90.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1956264 2.62% 93.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1088628 1.46% 94.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1022152 1.37% 95.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 532797 0.71% 96.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 718663 0.96% 97.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 378466 0.51% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1485008 1.99% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60561931 81.08% 81.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6932594 9.28% 90.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1961063 2.63% 92.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1092193 1.46% 94.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1024970 1.37% 95.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 536622 0.72% 96.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 713910 0.96% 97.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 380912 0.51% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1486293 1.99% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 74682043 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 31143561 # Number of instructions committed -system.cpu1.commit.committedOps 39697401 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 74690488 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 31194382 # Number of instructions committed +system.cpu1.commit.committedOps 39754477 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13831233 # Number of memory references committed -system.cpu1.commit.loads 7959008 # Number of loads committed -system.cpu1.commit.membars 199700 # Number of memory barriers committed -system.cpu1.commit.branches 5073252 # Number of branches committed -system.cpu1.commit.fp_insts 4858 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 35121772 # Number of committed integer instructions. -system.cpu1.commit.function_calls 494294 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1485008 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13852886 # Number of memory references committed +system.cpu1.commit.loads 7969478 # Number of loads committed +system.cpu1.commit.membars 200339 # Number of memory barriers committed +system.cpu1.commit.branches 5070949 # Number of branches committed +system.cpu1.commit.fp_insts 4906 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 35178713 # Number of committed integer instructions. +system.cpu1.commit.function_calls 493679 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1486293 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 121317994 # The number of ROB reads -system.cpu1.rob.rob_writes 99664484 # The number of ROB writes -system.cpu1.timesIdled 865516 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159179391 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2318646728 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 31060678 # Number of Instructions Simulated -system.cpu1.committedOps 39614518 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 31060678 # Number of Instructions Simulated -system.cpu1.cpi 7.578218 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.578218 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.131957 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.131957 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 276434717 # number of integer regfile reads -system.cpu1.int_regfile_writes 44854574 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22375 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19728 # number of floating regfile writes -system.cpu1.misc_regfile_reads 15285924 # number of misc regfile reads -system.cpu1.misc_regfile_writes 428613 # number of misc regfile writes +system.cpu1.rob.rob_reads 121392021 # The number of ROB reads +system.cpu1.rob.rob_writes 99804752 # The number of ROB writes +system.cpu1.timesIdled 864703 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159221190 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2318646914 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 31111502 # Number of Instructions Simulated +system.cpu1.committedOps 39671597 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 31111502 # Number of Instructions Simulated +system.cpu1.cpi 7.567525 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.567525 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.132144 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.132144 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 276724007 # number of integer regfile reads +system.cpu1.int_regfile_writes 44911737 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22398 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19708 # number of floating regfile writes +system.cpu1.misc_regfile_reads 15283998 # number of misc regfile reads +system.cpu1.misc_regfile_writes 429459 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2234,10 +2208,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518441783518 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1518441783518 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518441783518 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1518441783518 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518454987022 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1518454987022 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518454987022 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1518454987022 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini index 78712e3a3..927b487de 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,22 +12,23 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 panic_on_oops=true @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -86,6 +94,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts @@ -112,6 +121,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -134,18 +144,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -156,6 +169,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -178,14 +192,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -204,18 +221,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=TimingSimpleCPU @@ -227,6 +247,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=Null @@ -248,17 +269,20 @@ workload= [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -277,30 +301,36 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -313,6 +343,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -335,6 +366,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -344,6 +376,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -366,6 +399,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -373,6 +407,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -384,6 +419,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -410,6 +446,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -421,19 +458,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -443,6 +484,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -452,6 +494,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -480,6 +523,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -489,8 +533,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -502,6 +578,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -517,6 +594,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -531,6 +610,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -540,6 +620,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -561,8 +642,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -571,6 +654,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -581,6 +665,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -591,6 +676,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -601,6 +687,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -615,6 +702,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -628,6 +716,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -645,6 +734,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -657,6 +747,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -668,6 +759,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -678,6 +770,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -690,6 +783,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -703,6 +797,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -713,6 +808,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -723,6 +819,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -733,6 +830,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -745,6 +843,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -759,6 +858,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -771,6 +871,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -785,6 +886,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -795,6 +897,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -805,6 +908,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -815,6 +919,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -823,6 +928,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -831,6 +937,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -840,11 +947,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 87a0dc109..98143dc12 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,145 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.631415 # Number of seconds simulated -sim_ticks 2631415171500 # Number of ticks simulated -final_tick 2631415171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.629717 # Number of seconds simulated +sim_ticks 2629717216500 # Number of ticks simulated +final_tick 2629717216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 471038 # Simulator instruction rate (inst/s) -host_op_rate 599389 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20585916294 # Simulator tick rate (ticks/s) -host_mem_usage 424736 # Number of bytes of host memory used -host_seconds 127.83 # Real time elapsed on the host -sim_insts 60210883 # Number of instructions simulated -sim_ops 76617506 # Number of ops (including micro ops) simulated +host_inst_rate 340896 # Simulator instruction rate (inst/s) +host_op_rate 433786 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14888327014 # Simulator tick rate (ticks/s) +host_mem_usage 445372 # Number of bytes of host memory used +host_seconds 176.63 # Real time elapsed on the host +sim_insts 60212334 # Number of instructions simulated +sim_ops 76619433 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 278752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4724944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 298016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4661584 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 425732 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4336188 # Number of bytes read from this memory -system.physmem.bytes_read::total 134022064 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 278752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 425732 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704484 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3690496 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1530592 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1485560 # Number of bytes written to this memory -system.physmem.bytes_written::total 6706648 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 406404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4399060 # Number of bytes read from this memory +system.physmem.bytes_read::total 134021512 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 298016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 406404 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704420 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3689984 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1527272 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1489008 # Number of bytes written to this memory +system.physmem.bytes_written::total 6706264 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10558 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73861 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10859 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 72871 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6668 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 67782 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690904 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57664 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 382648 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 371390 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811702 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47220316 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6366 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 68770 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690901 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57656 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 381818 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 372252 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811726 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47250805 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 105932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1795590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 113326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1772656 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 161788 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1647854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50931554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 105932 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 161788 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267721 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1402476 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 581661 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 564548 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2548685 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1402476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47220316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 154543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1672826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50964230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 113326 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 154543 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267869 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1403187 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 580774 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 566224 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2550184 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1403187 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47250805 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 105932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2377252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 113326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2353430 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 161788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2212402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53480239 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690904 # Number of read requests accepted -system.physmem.writeReqs 811702 # Number of write requests accepted -system.physmem.readBursts 15690904 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811702 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1004216000 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu1.inst 154543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2239050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53514414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690901 # Number of read requests accepted +system.physmem.writeReqs 811726 # Number of write requests accepted +system.physmem.readBursts 15690901 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811726 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1004215808 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 1856 # Total number of bytes read from write queue -system.physmem.bytesWritten 6838848 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134022064 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6706648 # Total written bytes from the system interface side +system.physmem.bytesWritten 6837952 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134021512 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6706264 # Total written bytes from the system interface side system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 704845 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4517 # Number of requests that are neither read nor write +system.physmem.mergedWrBursts 704883 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4518 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 980392 # Per bank write bursts system.physmem.perBankRdBursts::1 980205 # Per bank write bursts system.physmem.perBankRdBursts::2 980222 # Per bank write bursts -system.physmem.perBankRdBursts::3 980428 # Per bank write bursts +system.physmem.perBankRdBursts::3 980431 # Per bank write bursts system.physmem.perBankRdBursts::4 986950 # Per bank write bursts -system.physmem.perBankRdBursts::5 980709 # Per bank write bursts -system.physmem.perBankRdBursts::6 980611 # Per bank write bursts -system.physmem.perBankRdBursts::7 980420 # Per bank write bursts +system.physmem.perBankRdBursts::5 980708 # Per bank write bursts +system.physmem.perBankRdBursts::6 980610 # Per bank write bursts +system.physmem.perBankRdBursts::7 980424 # Per bank write bursts system.physmem.perBankRdBursts::8 980615 # Per bank write bursts system.physmem.perBankRdBursts::9 980431 # Per bank write bursts system.physmem.perBankRdBursts::10 979815 # Per bank write bursts -system.physmem.perBankRdBursts::11 979555 # Per bank write bursts -system.physmem.perBankRdBursts::12 980153 # Per bank write bursts -system.physmem.perBankRdBursts::13 980095 # Per bank write bursts -system.physmem.perBankRdBursts::14 980165 # Per bank write bursts +system.physmem.perBankRdBursts::11 979558 # Per bank write bursts +system.physmem.perBankRdBursts::12 980154 # Per bank write bursts +system.physmem.perBankRdBursts::13 980093 # Per bank write bursts +system.physmem.perBankRdBursts::14 980155 # Per bank write bursts system.physmem.perBankRdBursts::15 980109 # Per bank write bursts -system.physmem.perBankWrBursts::0 6734 # Per bank write bursts -system.physmem.perBankWrBursts::1 6600 # Per bank write bursts -system.physmem.perBankWrBursts::2 6608 # Per bank write bursts -system.physmem.perBankWrBursts::3 6671 # Per bank write bursts -system.physmem.perBankWrBursts::4 6747 # Per bank write bursts -system.physmem.perBankWrBursts::5 7057 # Per bank write bursts -system.physmem.perBankWrBursts::6 7034 # Per bank write bursts -system.physmem.perBankWrBursts::7 6884 # Per bank write bursts -system.physmem.perBankWrBursts::8 7000 # Per bank write bursts -system.physmem.perBankWrBursts::9 6825 # Per bank write bursts +system.physmem.perBankWrBursts::0 6731 # Per bank write bursts +system.physmem.perBankWrBursts::1 6599 # Per bank write bursts +system.physmem.perBankWrBursts::2 6610 # Per bank write bursts +system.physmem.perBankWrBursts::3 6672 # Per bank write bursts +system.physmem.perBankWrBursts::4 6746 # Per bank write bursts +system.physmem.perBankWrBursts::5 7052 # Per bank write bursts +system.physmem.perBankWrBursts::6 7033 # Per bank write bursts +system.physmem.perBankWrBursts::7 6881 # Per bank write bursts +system.physmem.perBankWrBursts::8 7002 # Per bank write bursts +system.physmem.perBankWrBursts::9 6827 # Per bank write bursts system.physmem.perBankWrBursts::10 6323 # Per bank write bursts -system.physmem.perBankWrBursts::11 6129 # Per bank write bursts +system.physmem.perBankWrBursts::11 6122 # Per bank write bursts system.physmem.perBankWrBursts::12 6612 # Per bank write bursts -system.physmem.perBankWrBursts::13 6395 # Per bank write bursts -system.physmem.perBankWrBursts::14 6622 # Per bank write bursts +system.physmem.perBankWrBursts::13 6399 # Per bank write bursts +system.physmem.perBankWrBursts::14 6618 # Per bank write bursts system.physmem.perBankWrBursts::15 6616 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2631410752000 # Total gap between requests +system.physmem.totGap 2629712785000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6700 # Read request sizes (log2) +system.physmem.readPktSize::2 6706 # Read request sizes (log2) system.physmem.readPktSize::3 15532032 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152172 # Read request sizes (log2) +system.physmem.readPktSize::6 152163 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 754038 # Write request sizes (log2) +system.physmem.writePktSize::2 754070 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57664 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1280991 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1124435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1124568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3790382 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2700913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2699740 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2717442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 51875 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 57733 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20335 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 37 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57656 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1290849 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1134741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1135188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3791353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2690884 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2690157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2706986 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 51561 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 56279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20472 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20341 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 45 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -155,28 +167,28 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5010 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 4995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4689 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see @@ -187,301 +199,302 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90271 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11200.204894 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1031.239605 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16762.903946 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23441 25.97% 25.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14726 16.31% 42.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2829 3.13% 45.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2153 2.39% 47.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1359 1.51% 49.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1176 1.30% 50.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 955 1.06% 51.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1145 1.27% 52.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 612 0.68% 53.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 559 0.62% 54.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 621 0.69% 54.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 534 0.59% 55.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 322 0.36% 55.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 268 0.30% 56.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 218 0.24% 56.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 586 0.65% 57.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 164 0.18% 57.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 127 0.14% 57.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 130 0.14% 57.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 257 0.28% 57.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 105 0.12% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2231 2.47% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 89 0.10% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 142 0.16% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 48 0.05% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 45 0.05% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 41 0.05% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 166 0.18% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 19 0.02% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 18 0.02% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 150 0.17% 61.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 341 0.38% 61.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 18 0.02% 61.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 19 0.02% 61.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 17 0.02% 61.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 76 0.08% 61.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 15 0.02% 61.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 8 0.01% 61.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 16 0.02% 61.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 76 0.08% 61.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 11 0.01% 61.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 6 0.01% 61.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 7 0.01% 61.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 22 0.02% 61.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 8 0.01% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 3 0.00% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 6 0.01% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 382 0.42% 62.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 7 0.01% 62.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 8 0.01% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 6 0.01% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 146 0.16% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 2 0.00% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 137 0.15% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 6 0.01% 62.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 197 0.22% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 7 0.01% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 7 0.01% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 32 0.04% 62.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 137 0.15% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 6 0.01% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 2 0.00% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 6 0.01% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 337 0.37% 63.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 1 0.00% 63.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 1 0.00% 63.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 2 0.00% 63.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 130 0.14% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 2 0.00% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 1 0.00% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 71 0.08% 63.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 129 0.14% 63.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 3 0.00% 63.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 75 0.08% 63.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 4 0.00% 63.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 261 0.29% 64.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 1 0.00% 64.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 1 0.00% 64.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 62 0.07% 64.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 15 0.02% 64.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 204 0.23% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 122 0.14% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 133 0.15% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 389 0.43% 65.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 64 0.07% 65.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 2 0.00% 65.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 68 0.08% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 120 0.13% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 252 0.28% 65.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 133 0.15% 65.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 13 0.01% 66.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 68 0.08% 66.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 520 0.58% 66.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 68 0.08% 66.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 11 0.01% 66.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 136 0.15% 66.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 250 0.28% 67.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 121 0.13% 67.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 68 0.08% 67.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 65 0.07% 67.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 388 0.43% 67.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 132 0.15% 68.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10631 1 0.00% 68.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 121 0.13% 68.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10823 2 0.00% 68.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 55 0.06% 68.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 259 0.29% 68.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 71 0.08% 68.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11591 1 0.00% 68.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 69 0.08% 68.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 128 0.14% 68.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 328 0.36% 69.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 133 0.15% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 193 0.21% 69.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 136 0.15% 69.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 377 0.42% 70.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 11 0.01% 70.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 64 0.07% 70.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 70 0.08% 70.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 322 0.36% 70.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 132 0.15% 70.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 68 0.08% 70.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 129 0.14% 70.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 391 0.43% 71.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 67 0.07% 71.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 129 0.14% 71.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 641 0.71% 72.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 136 0.15% 72.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 66 0.07% 72.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 2 0.00% 72.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 391 0.43% 73.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 128 0.14% 73.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 67 0.07% 73.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 131 0.15% 73.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 320 0.35% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18624-18631 1 0.00% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 67 0.07% 73.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 67 0.07% 73.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 13 0.01% 73.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 1 0.00% 73.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 376 0.42% 74.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19591 1 0.00% 74.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 137 0.15% 74.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 192 0.21% 74.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 131 0.15% 74.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 326 0.36% 75.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 124 0.14% 75.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 68 0.08% 75.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21056-21063 1 0.00% 75.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 71 0.08% 75.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 259 0.29% 75.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 56 0.06% 75.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 1 0.00% 75.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 120 0.13% 75.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 134 0.15% 76.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 388 0.43% 76.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 64 0.07% 76.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 67 0.07% 76.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 121 0.13% 76.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 253 0.28% 77.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 133 0.15% 77.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 10 0.01% 77.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 70 0.08% 77.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 519 0.57% 77.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 69 0.08% 77.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 10 0.01% 77.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 133 0.15% 78.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 251 0.28% 78.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 120 0.13% 78.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 70 0.08% 78.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 64 0.07% 78.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 387 0.43% 79.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 134 0.15% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 119 0.13% 79.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 56 0.06% 79.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 259 0.29% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 71 0.08% 79.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 68 0.08% 79.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 125 0.14% 80.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 325 0.36% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 133 0.15% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 192 0.21% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 136 0.15% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29575 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 377 0.42% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 11 0.01% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 65 0.07% 81.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 69 0.08% 81.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 321 0.36% 81.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 130 0.14% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 67 0.07% 82.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 128 0.14% 82.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 390 0.43% 82.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 1 0.00% 82.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 67 0.07% 82.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 130 0.14% 82.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 640 0.71% 83.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 132 0.15% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 70 0.08% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 1 0.00% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 389 0.43% 84.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 128 0.14% 84.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 67 0.07% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 130 0.14% 84.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 318 0.35% 84.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 68 0.08% 85.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 64 0.07% 85.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 10 0.01% 85.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 377 0.42% 85.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 136 0.15% 85.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 192 0.21% 85.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 132 0.15% 86.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 324 0.36% 86.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 125 0.14% 86.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 68 0.08% 86.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 71 0.08% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 259 0.29% 86.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 56 0.06% 87.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 119 0.13% 87.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 134 0.15% 87.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 387 0.43% 87.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 64 0.07% 87.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 69 0.08% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 119 0.13% 88.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 251 0.28% 88.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 133 0.15% 88.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 9 0.01% 88.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 68 0.08% 88.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 518 0.57% 89.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 69 0.08% 89.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 10 0.01% 89.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 133 0.15% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 252 0.28% 89.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 120 0.13% 89.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 67 0.07% 89.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 64 0.07% 89.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 388 0.43% 90.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 134 0.15% 90.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 119 0.13% 90.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 1 0.00% 90.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 56 0.06% 90.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 260 0.29% 90.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 71 0.08% 91.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 69 0.08% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 124 0.14% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 325 0.36% 91.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 131 0.15% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 191 0.21% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 137 0.15% 92.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 375 0.42% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46208-46215 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 11 0.01% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 66 0.07% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 66 0.07% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-46983 1 0.00% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 319 0.35% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 133 0.15% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 90454 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11177.544033 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1030.436917 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16744.733089 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23393 25.86% 25.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14737 16.29% 42.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2929 3.24% 45.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2185 2.42% 47.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1403 1.55% 49.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1153 1.27% 50.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 940 1.04% 51.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1175 1.30% 52.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 610 0.67% 53.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 557 0.62% 54.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 555 0.61% 54.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 601 0.66% 55.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 293 0.32% 55.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 323 0.36% 56.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 207 0.23% 56.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 643 0.71% 57.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 173 0.19% 57.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 141 0.16% 57.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 139 0.15% 57.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 211 0.23% 57.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 108 0.12% 58.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2249 2.49% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 108 0.12% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 135 0.15% 60.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 71 0.08% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 48 0.05% 60.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 33 0.04% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 98 0.11% 61.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 34 0.04% 61.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 27 0.03% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 23 0.03% 61.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 231 0.26% 61.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 24 0.03% 61.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 27 0.03% 61.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 30 0.03% 61.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 143 0.16% 61.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 12 0.01% 61.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 18 0.02% 61.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 17 0.02% 61.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 86 0.10% 61.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 22 0.02% 61.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 12 0.01% 61.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 15 0.02% 61.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 205 0.23% 62.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 13 0.01% 62.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 20 0.02% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 10 0.01% 62.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 404 0.45% 62.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 18 0.02% 62.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 8 0.01% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 8 0.01% 62.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 21 0.02% 62.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 11 0.01% 62.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 14 0.02% 62.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 16 0.02% 62.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 82 0.09% 62.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 9 0.01% 62.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 15 0.02% 62.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 35 0.04% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 129 0.14% 62.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 12 0.01% 62.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 9 0.01% 62.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 7 0.01% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 283 0.31% 63.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 7 0.01% 63.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 5 0.01% 63.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 10 0.01% 63.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 6 0.01% 63.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 5 0.01% 63.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 11 0.01% 63.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 8 0.01% 63.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 271 0.30% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 14 0.02% 63.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 4 0.00% 63.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 9 0.01% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 136 0.15% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 4 0.00% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 11 0.01% 63.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 11 0.01% 63.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 341 0.38% 64.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 2 0.00% 64.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 14 0.02% 64.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 4 0.00% 64.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 205 0.23% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 168 0.19% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 59 0.07% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 3 0.00% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 126 0.14% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 267 0.30% 65.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 256 0.28% 65.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 2 0.00% 65.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 5 0.01% 65.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 65 0.07% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 454 0.50% 66.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 1 0.00% 66.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 9 0.01% 66.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 2 0.00% 66.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 192 0.21% 66.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 2 0.00% 66.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 261 0.29% 66.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 193 0.21% 66.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 9 0.01% 66.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 455 0.50% 67.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9351 1 0.00% 67.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 64 0.07% 67.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 5 0.01% 67.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 257 0.28% 67.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10183 1 0.00% 67.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 265 0.29% 67.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 124 0.14% 68.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 4 0.00% 68.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 195 0.22% 68.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11079 1 0.00% 68.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11207 1 0.00% 68.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 336 0.37% 68.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 123 0.14% 68.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 266 0.29% 69.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 267 0.30% 69.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 121 0.13% 69.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 75 0.08% 69.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 4 0.00% 69.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 387 0.43% 70.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 197 0.22% 70.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 78 0.09% 70.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13895 1 0.00% 70.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 129 0.14% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 206 0.23% 70.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 65 0.07% 70.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 65 0.07% 70.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 71 0.08% 70.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 1 0.00% 70.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 455 0.50% 71.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 66 0.07% 71.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 131 0.14% 71.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 128 0.14% 71.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 401 0.44% 72.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 130 0.14% 72.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 129 0.14% 72.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17095 1 0.00% 72.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 68 0.08% 72.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 460 0.51% 73.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17600-17607 1 0.00% 73.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 71 0.08% 73.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 66 0.07% 73.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 64 0.07% 73.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 208 0.23% 73.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 128 0.14% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 77 0.09% 73.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 196 0.22% 74.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 1 0.00% 74.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 386 0.43% 74.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 3 0.00% 74.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 72 0.08% 74.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 120 0.13% 74.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 270 0.30% 74.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 265 0.29% 75.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 123 0.14% 75.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 334 0.37% 75.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 195 0.22% 75.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21824-21831 1 0.00% 75.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 3 0.00% 76.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 127 0.14% 76.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 264 0.29% 76.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22720-22727 1 0.00% 76.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 255 0.28% 76.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 5 0.01% 76.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 65 0.07% 76.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 452 0.50% 77.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 9 0.01% 77.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 192 0.21% 77.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 3 0.00% 77.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 259 0.29% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 1 0.00% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 193 0.21% 78.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 7 0.01% 78.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 454 0.50% 78.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 66 0.07% 78.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 5 0.01% 78.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 256 0.28% 78.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 266 0.29% 79.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 124 0.14% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 2 0.00% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 195 0.22% 79.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 332 0.37% 79.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 123 0.14% 80.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 266 0.29% 80.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 267 0.30% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 122 0.13% 80.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 74 0.08% 80.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 4 0.00% 80.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 387 0.43% 81.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 194 0.21% 81.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 77 0.09% 81.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30272-30279 1 0.00% 81.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 128 0.14% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 1 0.00% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 205 0.23% 81.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 64 0.07% 82.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 66 0.07% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 71 0.08% 82.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 457 0.51% 82.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 65 0.07% 82.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 130 0.14% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 128 0.14% 83.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 400 0.44% 83.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 128 0.14% 83.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 135 0.15% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 65 0.07% 83.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 456 0.50% 84.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 71 0.08% 84.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 66 0.07% 84.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 64 0.07% 84.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 205 0.23% 84.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 128 0.14% 84.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 76 0.08% 85.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 194 0.21% 85.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 386 0.43% 85.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 3 0.00% 85.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 73 0.08% 85.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 121 0.13% 85.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 265 0.29% 86.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 265 0.29% 86.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 123 0.14% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 333 0.37% 86.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 195 0.22% 87.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 2 0.00% 87.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 125 0.14% 87.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 265 0.29% 87.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 256 0.28% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 5 0.01% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 65 0.07% 87.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 452 0.50% 88.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 7 0.01% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 192 0.21% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 259 0.29% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 3 0.00% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 192 0.21% 89.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 9 0.01% 89.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 452 0.50% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 64 0.07% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 5 0.01% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 255 0.28% 90.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 90.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 264 0.29% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 126 0.14% 90.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 3 0.00% 90.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 194 0.21% 90.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 335 0.37% 91.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 123 0.14% 91.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 264 0.29% 91.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 264 0.29% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 120 0.13% 91.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 72 0.08% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 4 0.00% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 385 0.43% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 194 0.21% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 76 0.08% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 128 0.14% 92.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 209 0.23% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 65 0.07% 93.19% # Bytes accessed per row activation system.physmem.bytesPerActivate::47616-47623 67 0.07% 93.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 129 0.14% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 390 0.43% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 1 0.00% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 67 0.07% 93.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 131 0.15% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 1 0.00% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5359 5.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90271 # Bytes accessed per row activation -system.physmem.totQLat 377292466250 # Total ticks spent queuing -system.physmem.totMemAccLat 474547986250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78454375000 # Total ticks spent in databus transfers -system.physmem.totBankLat 18801145000 # Total ticks spent accessing banks -system.physmem.avgQLat 24045.34 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1198.22 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::47744-47751 1 0.00% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 73 0.08% 93.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 459 0.51% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 3 0.00% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 69 0.08% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48448-48455 1 0.00% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 129 0.14% 94.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 129 0.14% 94.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 3 0.00% 94.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 1 0.00% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5220 5.77% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90454 # Bytes accessed per row activation +system.physmem.totQLat 377144928750 # Total ticks spent queuing +system.physmem.totMemAccLat 474552728750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78454360000 # Total ticks spent in databus transfers +system.physmem.totBankLat 18953440000 # Total ticks spent accessing banks +system.physmem.avgQLat 24035.94 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1207.93 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30243.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30243.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.93 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.96 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.00 # Data bus utilization in percentage @@ -489,268 +502,256 @@ system.physmem.busUtilRead 2.98 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 1.22 # Average write queue length when enqueuing -system.physmem.readRowHits 15616441 # Number of row buffer hits during reads -system.physmem.writeRowHits 91020 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.18 # Row buffer hit rate for writes -system.physmem.avgGap 159454.26 # Average gap between requests +system.physmem.readRowHits 15616330 # Number of row buffer hits during reads +system.physmem.writeRowHits 90931 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.11 # Row buffer hit rate for writes +system.physmem.avgGap 159351.16 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 2.38 # Percentage of time for which DRAM has all the banks in precharge state -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54391586 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743633 # Transaction distribution -system.membus.trans_dist::ReadResp 16743633 # Transaction distribution -system.membus.trans_dist::WriteReq 763392 # Transaction distribution -system.membus.trans_dist::WriteResp 763392 # Transaction distribution -system.membus.trans_dist::Writeback 57664 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution -system.membus.trans_dist::ReadExReq 131346 # Transaction distribution -system.membus.trans_dist::ReadExResp 131346 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) +system.physmem.prechargeAllPercent 2.39 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 54426353 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743636 # Transaction distribution +system.membus.trans_dist::ReadResp 16743636 # Transaction distribution +system.membus.trans_dist::WriteReq 763424 # Transaction distribution +system.membus.trans_dist::WriteResp 763424 # Transaction distribution +system.membus.trans_dist::Writeback 57656 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4518 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4518 # Transaction distribution +system.membus.trans_dist::ReadExReq 131342 # Transaction distribution +system.membus.trans_dist::ReadExResp 131342 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382990 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892518 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4279376 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892570 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279432 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35343440 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 35343496 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390397 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16472456 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18870589 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16471520 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18869661 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143126845 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143126845 # Total data (bytes) +system.membus.tot_pkt_size::total 143125917 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143125917 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1220589500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1225680000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3747000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3756000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 18118484000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 18171618500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4951896724 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4990533473 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 35075499000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 35075577250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 62057 # number of replacements -system.l2c.tags.tagsinuse 51615.015118 # Cycle average of tags in use -system.l2c.tags.total_refs 1699237 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127445 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.333101 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2576505750500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38217.986822 # Average occupied blocks per requestor +system.l2c.tags.replacements 62046 # number of replacements +system.l2c.tags.tagsinuse 51605.865819 # Cycle average of tags in use +system.l2c.tags.total_refs 1699437 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127429 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.336344 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2574782383500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38213.733489 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000701 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2603.292629 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3037.110347 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2749.245070 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3097.480060 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4418.327235 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3338.297198 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.583160 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 4271.539066 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3273.867246 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.583095 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.039723 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.046343 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.041950 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.047264 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.067418 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.050938 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.787583 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 9914 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3649 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 415311 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 183212 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 10008 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3517 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 429187 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 187142 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1241940 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596380 # number of Writeback hits -system.l2c.Writeback_hits::total 596380 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits +system.l2c.tags.occ_percent::cpu1.inst 0.065179 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.049955 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.787443 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 9827 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3607 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 412393 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 183168 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 10051 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3578 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 432141 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 187290 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1242055 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596450 # number of Writeback hits +system.l2c.Writeback_hits::total 596450 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56696 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 57849 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114545 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9914 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3649 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 415311 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 239908 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 10008 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3517 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 429187 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 244991 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356485 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9914 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3649 # number of overall hits -system.l2c.overall_hits::cpu0.inst 415311 # number of overall hits -system.l2c.overall_hits::cpu0.data 239908 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 10008 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3517 # number of overall hits -system.l2c.overall_hits::cpu1.inst 429187 # number of overall hits -system.l2c.overall_hits::cpu1.data 244991 # number of overall hits -system.l2c.overall_hits::total 1356485 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 57240 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 57291 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114531 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 9827 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3607 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 412393 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 240408 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 10051 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3578 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 432141 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 244581 # number of demand (read+write) hits +system.l2c.demand_hits::total 1356586 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 9827 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3607 # number of overall hits +system.l2c.overall_hits::cpu0.inst 412393 # number of overall hits +system.l2c.overall_hits::cpu0.data 240408 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 10051 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3578 # number of overall hits +system.l2c.overall_hits::cpu1.inst 432141 # number of overall hits +system.l2c.overall_hits::cpu1.data 244581 # number of overall hits +system.l2c.overall_hits::total 1356586 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 3942 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5224 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 4243 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5343 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6651 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 5006 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20826 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1375 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1512 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2887 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 69398 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 63578 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 132976 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 6349 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4883 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20821 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1353 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1530 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2883 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 68272 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 64705 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 132977 # number of ReadExReq misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 3942 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 74622 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 4243 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 73615 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6651 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 68584 # number of demand (read+write) misses -system.l2c.demand_misses::total 153802 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6349 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 69588 # number of demand (read+write) misses +system.l2c.demand_misses::total 153798 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 3942 # number of overall misses -system.l2c.overall_misses::cpu0.data 74622 # number of overall misses +system.l2c.overall_misses::cpu0.inst 4243 # number of overall misses +system.l2c.overall_misses::cpu0.data 73615 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6651 # number of overall misses -system.l2c.overall_misses::cpu1.data 68584 # number of overall misses -system.l2c.overall_misses::total 153802 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 150000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 279121500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 387849000 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu1.inst 6349 # number of overall misses +system.l2c.overall_misses::cpu1.data 69588 # number of overall misses +system.l2c.overall_misses::total 153798 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 301157500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 396109250 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 89250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 474818500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 382257500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1524285750 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 256989 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 208991 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 465980 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4923800203 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4505788417 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9429588620 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 150000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 279121500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 5311649203 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 450843500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 372813750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1521162750 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 232990 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 231990 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 464980 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4857371220 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4602598395 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9459969615 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 301157500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 5253480470 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 89250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 474818500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4888045917 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 10953874370 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 150000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 279121500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 5311649203 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu1.inst 450843500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4975412145 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 10981132365 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 301157500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 5253480470 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 89250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 474818500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4888045917 # number of overall miss cycles -system.l2c.overall_miss_latency::total 10953874370 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 9914 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3651 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 419253 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 188436 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 10009 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 3517 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 435838 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 192148 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1262766 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 596380 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 596380 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1389 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1524 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2913 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 126094 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 121427 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247521 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 9914 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3651 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 419253 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 314530 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 10009 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 3517 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 435838 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 313575 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1510287 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 9914 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3651 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 419253 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 314530 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 10009 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 3517 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 435838 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 313575 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1510287 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000548 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.009402 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.027723 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000100 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.015260 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.026053 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016492 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989921 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992126 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.991074 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.550367 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.523590 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.537231 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000548 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.009402 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.237249 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000100 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.015260 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.218716 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.101836 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000548 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.009402 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.237249 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000100 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.015260 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.218716 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.101836 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70807.077626 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 74243.683002 # average ReadReq miss latency +system.l2c.overall_miss_latency::cpu1.inst 450843500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4975412145 # number of overall miss cycles +system.l2c.overall_miss_latency::total 10981132365 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 9827 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3609 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 416636 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 188511 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 10052 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 3578 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 438490 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 192173 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1262876 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 596450 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 596450 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1366 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1543 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2909 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 125512 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 121996 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247508 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 9827 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3609 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 416636 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 314023 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 10052 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 3578 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 438490 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 314169 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1510384 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 9827 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3609 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 416636 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 314023 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 10052 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 3578 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 438490 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 314169 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1510384 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000554 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.010184 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.028343 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000099 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.014479 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.025409 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016487 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990483 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991575 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991062 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.543948 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.530386 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.537263 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000554 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.010184 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.234426 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000099 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.014479 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.221499 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.101827 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000554 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.010184 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.234426 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000099 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.014479 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.221499 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.101827 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70977.492340 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 74136.112671 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71390.542776 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 76359.868158 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 73191.479401 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 186.901091 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 138.221561 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 161.406304 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70950.174400 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70870.244692 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 70911.958699 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 70807.077626 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 71180.740304 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71010.159080 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 76349.324186 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 73059.062965 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 172.202513 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 151.627451 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 161.283385 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71147.340345 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71132.036087 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 71139.893478 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 70977.492340 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 71364.266386 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 71390.542776 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 71270.936618 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 71220.623724 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 70807.077626 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 71180.740304 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 71010.159080 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 71498.133946 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 71399.708481 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 70977.492340 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 71364.266386 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 71390.542776 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 71270.936618 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 71220.623724 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 71010.159080 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 71498.133946 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 71399.708481 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -759,129 +760,129 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 57664 # number of writebacks -system.l2c.writebacks::total 57664 # number of writebacks +system.l2c.writebacks::writebacks 57656 # number of writebacks +system.l2c.writebacks::total 57656 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 3942 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 5224 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 4243 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 5343 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6651 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 5006 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 20826 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1375 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1512 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2887 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 69398 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 63578 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 132976 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6349 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4883 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 20821 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1353 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1530 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2883 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 68272 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 64705 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 132977 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 3942 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 74622 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 4243 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 73615 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6651 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 68584 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 153802 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6349 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 69588 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 153798 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 3942 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 74622 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 4243 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 73615 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6651 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 68584 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 153802 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 6349 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 69588 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 153798 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 229630000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 322854500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 247421000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 329573750 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 391301000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 319831000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1263817750 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13751375 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15121512 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 28872887 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4053929797 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3708851583 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7762781380 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 370327500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 311886250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1259409750 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13531353 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15301530 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 28832883 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3982762780 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3773110105 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7755872885 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 229630000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 4376784297 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 247421000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 4312336530 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 391301000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 4028682583 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 9026599130 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 370327500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 4084996355 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 9015282635 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 229630000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 4376784297 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 247421000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 4312336530 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 391301000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 4028682583 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 9026599130 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 370327500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4084996355 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9015282635 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 343871250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83402251750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83755912750 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 842500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83269942750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167016908250 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8431436509 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8268193000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 16699629509 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82922372500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167022999000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8435630009 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8264647000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16700277009 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 343871250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 91833688259 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92191542759 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 842500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91538135750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 183716537759 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000548 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009402 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027723 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000100 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.015260 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026053 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016492 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.989921 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992126 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.991074 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.550367 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.523590 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.537231 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000548 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009402 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.237249 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000100 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015260 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.218716 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.101836 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000548 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009402 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.237249 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000100 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015260 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.218716 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.101836 # mshr miss rate for overall accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91187019500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183723276009 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000554 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.010184 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028343 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000099 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014479 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025409 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016487 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.990483 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991575 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991062 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.543948 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.530386 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.537263 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000554 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010184 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.234426 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000099 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014479 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.221499 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.101827 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000554 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010184 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.234426 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000099 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014479 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.221499 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.101827 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58252.156266 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61802.163093 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58312.750412 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61683.277185 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58833.408510 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63889.532561 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 60684.612984 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58328.476926 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63871.851321 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60487.476586 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 58415.657469 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58335.455393 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 58377.311545 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 58336.694106 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58312.496793 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 58324.919986 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58252.156266 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58652.733738 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58312.750412 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58579.590165 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58833.408510 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58740.851846 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58689.738300 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58328.476926 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58702.597502 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58617.684463 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58252.156266 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58652.733738 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58312.750412 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58579.590165 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58833.408510 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58740.851846 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58689.738300 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58328.476926 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58702.597502 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58617.684463 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -902,45 +903,45 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52751818 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2471631 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471631 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763392 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763392 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596380 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2913 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2913 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247521 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247521 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725079 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753474 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20108 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50543 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7549204 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54752376 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83781573 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79692 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138642313 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138642313 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 169620 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4808134500 # Layer occupancy (ticks) +system.toL2Bus.throughput 52790683 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2471881 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471881 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763424 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763424 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 596450 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2909 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2909 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 247508 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247508 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725145 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753790 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20211 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50526 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7549672 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54754616 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83791781 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28748 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79516 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138654661 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138654661 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 169908 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4808598000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3865505750 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3865648250 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4420696776 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4421117527 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12940000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 13024000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30620250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30647250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48128720 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16715358 # Transaction distribution -system.iobus.trans_dist::ReadResp 16715358 # Transaction distribution +system.iobus.throughput 48159799 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16715360 # Transaction distribution +system.iobus.trans_dist::ReadResp 16715360 # Transaction distribution system.iobus.trans_dist::WriteReq 8167 # Transaction distribution system.iobus.trans_dist::WriteResp 8167 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -962,12 +963,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382990 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33447050 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33447054 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -989,14 +990,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390397 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 126646645 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 126646645 # Total data (bytes) +system.iobus.tot_pkt_size::total 126646653 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 126646653 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1042,141 +1043,141 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374819000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374823000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42584048000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42583673750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7352406 # DTB read hits -system.cpu0.dtb.read_misses 6766 # DTB read misses -system.cpu0.dtb.write_hits 5599485 # DTB write hits -system.cpu0.dtb.write_misses 1847 # DTB write misses -system.cpu0.dtb.flush_tlb 1248 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 7421376 # DTB read hits +system.cpu0.dtb.read_misses 6854 # DTB read misses +system.cpu0.dtb.write_hits 5628030 # DTB write hits +system.cpu0.dtb.write_misses 1815 # DTB write misses +system.cpu0.dtb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 673 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6337 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 6418 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 131 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 151 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 221 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7359172 # DTB read accesses -system.cpu0.dtb.write_accesses 5601332 # DTB write accesses +system.cpu0.dtb.perms_faults 219 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7428230 # DTB read accesses +system.cpu0.dtb.write_accesses 5629845 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12951891 # DTB hits -system.cpu0.dtb.misses 8613 # DTB misses -system.cpu0.dtb.accesses 12960504 # DTB accesses -system.cpu0.itb.inst_hits 30170189 # ITB inst hits -system.cpu0.itb.inst_misses 3579 # ITB inst misses +system.cpu0.dtb.hits 13049406 # DTB hits +system.cpu0.dtb.misses 8669 # DTB misses +system.cpu0.dtb.accesses 13058075 # DTB accesses +system.cpu0.itb.inst_hits 30610107 # ITB inst hits +system.cpu0.itb.inst_misses 3562 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1248 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 673 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2699 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2748 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30173768 # ITB inst accesses -system.cpu0.itb.hits 30170189 # DTB hits -system.cpu0.itb.misses 3579 # DTB misses -system.cpu0.itb.accesses 30173768 # DTB accesses -system.cpu0.numCycles 2629696361 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30613669 # ITB inst accesses +system.cpu0.itb.hits 30610107 # DTB hits +system.cpu0.itb.misses 3562 # DTB misses +system.cpu0.itb.accesses 30613669 # DTB accesses +system.cpu0.numCycles 2628235952 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29597158 # Number of instructions committed -system.cpu0.committedOps 37762240 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33970200 # Number of integer alu accesses +system.cpu0.committedInsts 29990580 # Number of instructions committed +system.cpu0.committedOps 38158663 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34282971 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4584 # Number of float alu accesses -system.cpu0.num_func_calls 1050225 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3920547 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33970200 # number of integer instructions +system.cpu0.num_func_calls 1059870 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3968282 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34282971 # number of integer instructions system.cpu0.num_fp_insts 4584 # number of float instructions -system.cpu0.num_int_register_reads 194623734 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36521551 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3225 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1362 # number of times the floating registers were written -system.cpu0.num_mem_refs 13522491 # number of memory refs -system.cpu0.num_load_insts 7673972 # Number of load instructions -system.cpu0.num_store_insts 5848519 # Number of store instructions -system.cpu0.num_idle_cycles 2290697984.129271 # Number of idle cycles -system.cpu0.num_busy_cycles 338998376.870729 # Number of busy cycles -system.cpu0.not_idle_fraction 0.128912 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.871088 # Percentage of idle cycles +system.cpu0.num_int_register_reads 196555242 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36964020 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3346 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1240 # number of times the floating registers were written +system.cpu0.num_mem_refs 13622094 # number of memory refs +system.cpu0.num_load_insts 7743834 # Number of load instructions +system.cpu0.num_store_insts 5878260 # Number of store instructions +system.cpu0.num_idle_cycles 2282805163.828333 # Number of idle cycles +system.cpu0.num_busy_cycles 345430788.171666 # Number of busy cycles +system.cpu0.not_idle_fraction 0.131431 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.868569 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 83029 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 856199 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.856725 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60648231 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 856711 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.791937 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 20135568250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 208.641443 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 302.215282 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.407503 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.590264 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997767 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29750188 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30898043 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60648231 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29750188 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30898043 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60648231 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29750188 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 30898043 # number of overall hits -system.cpu0.icache.overall_hits::total 60648231 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 420001 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 436711 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 856712 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 420001 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 436711 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 856712 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 420001 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 436711 # number of overall misses -system.cpu0.icache.overall_misses::total 856712 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5711192500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6097938000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11809130500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5711192500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6097938000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11809130500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5711192500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6097938000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11809130500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30170189 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 31334754 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 61504943 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30170189 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 31334754 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 61504943 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30170189 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 31334754 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 61504943 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013921 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013937 # miss rate for ReadReq accesses +system.cpu0.icache.tags.replacements 856230 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.853093 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60649685 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 856742 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 70.791072 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 20173406250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 217.243034 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 293.610060 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.424303 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.573457 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997760 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 30192721 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 30456964 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60649685 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 30192721 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 30456964 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 60649685 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 30192721 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 30456964 # number of overall hits +system.cpu0.icache.overall_hits::total 60649685 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 417386 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 439357 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 856743 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 417386 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 439357 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 856743 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 417386 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 439357 # number of overall misses +system.cpu0.icache.overall_misses::total 856743 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5696153000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6111476500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11807629500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5696153000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6111476500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11807629500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5696153000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6111476500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11807629500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30610107 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 30896321 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 61506428 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30610107 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 30896321 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 61506428 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30610107 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 30896321 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 61506428 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013636 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014220 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.013929 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013921 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013937 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013636 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014220 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.013929 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013921 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.013937 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013636 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014220 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013929 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13598.045005 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13963.325861 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13784.247799 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13598.045005 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13963.325861 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13784.247799 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13598.045005 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13963.325861 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13784.247799 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13647.206662 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13910.046955 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13781.997052 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13647.206662 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13910.046955 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13781.997052 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13647.206662 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13910.046955 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13781.997052 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1185,48 +1186,48 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 420001 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 436711 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 856712 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 420001 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 436711 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 856712 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 420001 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 436711 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 856712 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869726500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5221934000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10091660500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869726500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5221934000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10091660500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869726500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5221934000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10091660500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 417386 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 439357 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 856743 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 417386 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 439357 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 856743 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 417386 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 439357 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 856743 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4859799000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5230292500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10090091500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4859799000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5230292500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10090091500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4859799000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5230292500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10090091500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 435321250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 1072000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 436393250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 1072500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 436393750 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 435321250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 1072000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 436393250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013921 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013937 # mshr miss rate for ReadReq accesses +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 1072500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 436393750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013636 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014220 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013929 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013921 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.013937 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013636 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014220 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.013929 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013921 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.013937 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013636 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014220 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.013929 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11594.559299 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11957.413484 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11779.525091 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11594.559299 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11957.413484 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11779.525091 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11594.559299 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11957.413484 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11779.525091 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11643.416406 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11904.425103 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11777.267512 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11643.416406 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11904.425103 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11777.267512 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11643.416406 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11904.425103 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11777.267512 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1234,113 +1235,113 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 627593 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.877442 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23660330 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 628105 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.669386 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 627680 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.877363 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 23660930 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 628192 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 37.665125 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 664004250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 182.884282 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 328.993161 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.357196 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.642565 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999761 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6452957 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6745780 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13198737 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4964348 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 5010385 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9974733 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 118524 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117664 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 236188 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 124634 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 123125 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247759 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11417305 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 11756165 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 23173470 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11417305 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 11756165 # number of overall hits -system.cpu0.dcache.overall_hits::total 23173470 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 182326 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 186686 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 369012 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 127483 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 122951 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 250434 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6110 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5462 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11572 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 309809 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 309637 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 619446 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 309809 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 309637 # number of overall misses -system.cpu0.dcache.overall_misses::total 619446 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2717177250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2764634500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5481811750 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5932563172 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5512471095 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 11445034267 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 81881250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 78503500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 160384750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8649740422 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 8277105595 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 16926846017 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8649740422 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 8277105595 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 16926846017 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6635283 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6932466 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13567749 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5091831 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5133336 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10225167 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124634 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 123126 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 247760 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 124634 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 123125 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247759 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11727114 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12065802 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 23792916 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11727114 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12065802 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23792916 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027478 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026929 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.027198 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025037 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.023951 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.024492 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.049024 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044361 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046706 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026418 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025662 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026035 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026418 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025662 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.026035 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14902.851212 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14809.008174 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14855.375299 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46536.112046 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44834.699148 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45700.800478 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13401.186579 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14372.665690 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13859.726063 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27919.590528 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26731.642520 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 27325.781451 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27919.590528 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26731.642520 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 27325.781451 # average overall miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.794485 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 327.082879 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.360927 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.638834 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999760 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6519451 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6679636 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13199087 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4994316 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 4980652 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9974968 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 118550 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117644 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 236194 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 124564 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 123208 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247772 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11513767 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 11660288 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 23174055 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11513767 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 11660288 # number of overall hits +system.cpu0.dcache.overall_hits::total 23174055 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 182495 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 186610 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 369105 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 126878 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 123539 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 250417 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6016 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5563 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11579 # number of LoadLockedReq misses +system.cpu0.dcache.demand_misses::cpu0.data 309373 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 310149 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 619522 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 309373 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 310149 # number of overall misses +system.cpu0.dcache.overall_misses::total 619522 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2725951250 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2755941500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5481892750 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5868624133 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5606519635 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 11475143768 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 81127500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 79383250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 160510750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8594575383 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 8362461135 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 16957036518 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8594575383 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 8362461135 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 16957036518 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6701946 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6866246 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13568192 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5121194 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5104191 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10225385 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124566 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 123207 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 247773 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 124564 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 123208 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247772 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11823140 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 11970437 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 23793577 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11823140 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 11970437 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 23793577 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027230 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.027178 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.027204 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024775 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024203 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.024490 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048296 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045152 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046732 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026167 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025910 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.026037 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026167 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025910 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.026037 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14937.128414 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14768.455603 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14851.851777 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46254.071888 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45382.588778 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45824.140406 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13485.289229 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14269.863383 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13862.229035 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27780.625274 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26962.721579 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 27371.161182 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27780.625274 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26962.721579 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 27371.161182 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1349,77 +1350,77 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 596380 # number of writebacks -system.cpu0.dcache.writebacks::total 596380 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182326 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 186686 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 369012 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 127483 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 122951 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 250434 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6110 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5462 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11572 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 309809 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 309637 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 619446 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 309809 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 309637 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 619446 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2351238750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2390198500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4741437250 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5650406828 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5242308905 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10892715733 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69656750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67531500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137188250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8001645578 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7632507405 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15634152983 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8001645578 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7632507405 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15634152983 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91105263250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90961118500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182066381750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13264461491 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12970911500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26235372991 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104369724741 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103932030000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208301754741 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027478 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026929 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027198 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025037 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023951 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024492 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.049024 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044361 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046706 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026418 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025662 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026418 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025662 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12895.795169 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12803.308764 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12849.005588 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44322.826008 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42637.383226 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43495.354996 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11400.450082 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12363.877700 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11855.189250 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25827.673108 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24649.855815 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25238.927982 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25827.673108 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24649.855815 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25238.927982 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 596450 # number of writebacks +system.cpu0.dcache.writebacks::total 596450 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182495 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 186610 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 369105 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126878 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 123539 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 250417 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6016 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5563 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11579 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 309373 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 310149 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 619522 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 309373 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 310149 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619522 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2359626750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2381686500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4741313250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5588242867 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5334624365 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10922867232 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69088500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68209750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137298250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7947869617 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7716310865 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15664180482 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7947869617 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7716310865 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15664180482 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91489795250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90582792250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182072587500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13259276491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12977158000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26236434491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104749071741 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103559950250 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208309021991 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027230 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027178 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027204 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024775 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024203 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024490 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048296 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.045152 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046732 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026167 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025910 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.026037 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026167 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025910 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026037 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12929.815885 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12762.909276 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12845.432194 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44044.222537 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43181.702661 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43618.712915 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11484.125665 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12261.324825 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11857.522239 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25690.249689 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24879.367223 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25284.300609 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25690.249689 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24879.367223 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25284.300609 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1432,68 +1433,68 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7647205 # DTB read hits -system.cpu1.dtb.read_misses 7298 # DTB read misses -system.cpu1.dtb.write_hits 5633094 # DTB write hits -system.cpu1.dtb.write_misses 1843 # DTB write misses -system.cpu1.dtb.flush_tlb 1248 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 7578699 # DTB read hits +system.cpu1.dtb.read_misses 7251 # DTB read misses +system.cpu1.dtb.write_hits 5604812 # DTB write hits +system.cpu1.dtb.write_misses 1846 # DTB write misses +system.cpu1.dtb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 730 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 766 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6730 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 6708 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 231 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7654503 # DTB read accesses -system.cpu1.dtb.write_accesses 5634937 # DTB write accesses +system.cpu1.dtb.perms_faults 233 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7585950 # DTB read accesses +system.cpu1.dtb.write_accesses 5606658 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13280299 # DTB hits -system.cpu1.dtb.misses 9141 # DTB misses -system.cpu1.dtb.accesses 13289440 # DTB accesses -system.cpu1.itb.inst_hits 31334771 # ITB inst hits -system.cpu1.itb.inst_misses 3728 # ITB inst misses +system.cpu1.dtb.hits 13183511 # DTB hits +system.cpu1.dtb.misses 9097 # DTB misses +system.cpu1.dtb.accesses 13192608 # DTB accesses +system.cpu1.itb.inst_hits 30896338 # ITB inst hits +system.cpu1.itb.inst_misses 3789 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1248 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 730 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 766 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2858 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2857 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 31338499 # ITB inst accesses -system.cpu1.itb.hits 31334771 # DTB hits -system.cpu1.itb.misses 3728 # DTB misses -system.cpu1.itb.accesses 31338499 # DTB accesses -system.cpu1.numCycles 2633133982 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 30900127 # ITB inst accesses +system.cpu1.itb.hits 30896338 # DTB hits +system.cpu1.itb.misses 3789 # DTB misses +system.cpu1.itb.accesses 30900127 # DTB accesses +system.cpu1.numCycles 2631198481 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30613725 # Number of instructions committed -system.cpu1.committedOps 38855266 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34913201 # Number of integer alu accesses +system.cpu1.committedInsts 30221754 # Number of instructions committed +system.cpu1.committedOps 38460770 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34602143 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5685 # Number of float alu accesses -system.cpu1.num_func_calls 1090107 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4028756 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34913201 # number of integer instructions +system.cpu1.num_func_calls 1080538 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3981203 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34602143 # number of integer instructions system.cpu1.num_fp_insts 5685 # number of float instructions -system.cpu1.num_int_register_reads 200222637 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37674133 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4268 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1418 # number of times the floating registers were written -system.cpu1.num_mem_refs 13877284 # number of memory refs -system.cpu1.num_load_insts 7989860 # Number of load instructions -system.cpu1.num_store_insts 5887424 # Number of store instructions -system.cpu1.num_idle_cycles 2288817928.029144 # Number of idle cycles -system.cpu1.num_busy_cycles 344316053.970855 # Number of busy cycles -system.cpu1.not_idle_fraction 0.130763 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.869237 # Percentage of idle cycles +system.cpu1.num_int_register_reads 198301383 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37233535 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4147 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1540 # number of times the floating registers were written +system.cpu1.num_mem_refs 13778426 # number of memory refs +system.cpu1.num_load_insts 7920474 # Number of load instructions +system.cpu1.num_store_insts 5857952 # Number of store instructions +system.cpu1.num_idle_cycles 2292395060.642381 # Number of idle cycles +system.cpu1.num_busy_cycles 338803420.357619 # Number of busy cycles +system.cpu1.not_idle_fraction 0.128764 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.871236 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements @@ -1510,10 +1511,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557205456000 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1557205456000 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557205456000 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1557205456000 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557221573750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1557221573750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557221573750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1557221573750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index c0ebf9d4a..c331380ec 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -14,10 +16,11 @@ boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 cache_line_size=64 clk_domain=system.clk_domain e820_table=system.e820_table +eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing mem_ranges=0:134217727 @@ -38,6 +41,7 @@ system_port=system.membus.slave[1] [system.acpi_description_table_pointer] type=X86ACPIRSDP children=xsdt +eventq_index=0 oem_id= revision=2 rsdt=Null @@ -48,6 +52,7 @@ type=X86ACPIXSDT creator_id= creator_revision=0 entries= +eventq_index=0 oem_id= oem_revision=0 oem_table_id= @@ -56,6 +61,7 @@ oem_table_id= type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=11529215046068469760:11529215046068473855 req_size=16 resp_size=16 @@ -66,6 +72,7 @@ slave=system.iobus.master[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615 req_size=16 resp_size=16 @@ -75,6 +82,7 @@ slave=system.membus.master[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -106,6 +114,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -167,6 +177,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.branchPred] type=BranchPredictor @@ -175,6 +186,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -190,6 +202,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -212,18 +225,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.dtb_walker_cache.cpu_side @@ -234,6 +250,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -256,6 +273,7 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=1024 @@ -263,15 +281,18 @@ size=1024 type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -280,16 +301,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -298,22 +322,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -322,22 +350,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -346,10 +378,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -358,124 +392,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -484,10 +539,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -496,16 +553,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -514,10 +574,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -528,6 +590,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -550,12 +613,14 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -566,16 +631,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.itb_walker_cache.cpu_side @@ -586,6 +654,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -608,6 +677,7 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=1024 @@ -617,6 +687,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -639,12 +710,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -654,44 +727,52 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.e820_table] type=X86E820Table children=entries0 entries1 entries2 entries3 entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 +eventq_index=0 [system.e820_table.entries0] type=X86E820Entry addr=0 +eventq_index=0 range_type=1 size=654336 [system.e820_table.entries1] type=X86E820Entry addr=654336 +eventq_index=0 range_type=2 size=394240 [system.e820_table.entries2] type=X86E820Entry addr=1048576 +eventq_index=0 range_type=1 size=133169152 [system.e820_table.entries3] type=X86E820Entry addr=4294901760 +eventq_index=0 range_type=2 size=65536 [system.intel_mp_pointer] type=X86IntelMPFloatingPointer default_config=0 +eventq_index=0 imcr_present=true spec_rev=4 @@ -699,6 +780,7 @@ spec_rev=4 type=X86IntelMPConfigTable children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32 +eventq_index=0 ext_entries=system.intel_mp_table.ext_entries local_apic=4276092928 oem_id= @@ -711,6 +793,7 @@ spec_rev=4 type=X86IntelMPProcessor bootstrap=true enable=true +eventq_index=0 family=0 feature_flags=0 local_apic_id=0 @@ -722,6 +805,7 @@ stepping=0 type=X86IntelMPIOAPIC address=4273995776 enable=true +eventq_index=0 id=1 version=17 @@ -729,16 +813,19 @@ version=17 type=X86IntelMPBus bus_id=0 bus_type=ISA +eventq_index=0 [system.intel_mp_table.base_entries03] type=X86IntelMPBus bus_id=1 bus_type=PCI +eventq_index=0 [system.intel_mp_table.base_entries04] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=16 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=1 @@ -749,6 +836,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -759,6 +847,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=2 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -769,6 +858,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -779,6 +869,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=1 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -789,6 +880,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -799,6 +891,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=3 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -809,6 +902,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -819,6 +913,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=4 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -829,6 +924,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -839,6 +935,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=5 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -849,6 +946,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -859,6 +957,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=6 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -869,6 +968,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -879,6 +979,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=7 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -889,6 +990,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -899,6 +1001,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=8 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -909,6 +1012,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -919,6 +1023,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=9 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -929,6 +1034,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -939,6 +1045,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=10 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -949,6 +1056,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -959,6 +1067,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=11 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -969,6 +1078,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -979,6 +1089,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=12 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -989,6 +1100,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -999,6 +1111,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=13 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -1009,6 +1122,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -1019,6 +1133,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=14 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -1028,16 +1143,19 @@ trigger=ConformTrigger [system.intel_mp_table.ext_entries] type=X86IntelMPBusHierarchy bus_id=0 +eventq_index=0 parent_bus=1 subtractive_decode=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -1051,6 +1169,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -1073,6 +1192,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -1080,6 +1200,7 @@ size=1024 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1091,6 +1212,7 @@ slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side sy [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1107,13 +1229,15 @@ pio=system.membus.default [system.pc] type=Pc -children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal +children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge +eventq_index=0 intrctrl=system.intrctrl system=system [system.pc.behind_pci] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854779128 pio_latency=100000 @@ -1132,6 +1256,7 @@ pio=system.iobus.master[12] type=Uart8250 children=terminal clk_domain=system.clk_domain +eventq_index=0 pio_addr=9223372036854776824 pio_latency=100000 platform=system.pc @@ -1141,13 +1266,7 @@ pio=system.iobus.master[13] [system.pc.com_1.terminal] type=Terminal -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.pc.com_1.terminal] -type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1156,6 +1275,7 @@ port=3456 [system.pc.fake_com_2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776568 pio_latency=100000 @@ -1173,6 +1293,7 @@ pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776808 pio_latency=100000 @@ -1190,6 +1311,7 @@ pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776552 pio_latency=100000 @@ -1207,6 +1329,7 @@ pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776818 pio_latency=100000 @@ -1224,6 +1347,7 @@ pio=system.iobus.master[17] [system.pc.i_dont_exist] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854775936 pio_latency=100000 @@ -1242,6 +1366,7 @@ pio=system.iobus.master[11] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.pc @@ -1254,6 +1379,7 @@ type=SouthBridge children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker cmos=system.pc.south_bridge.cmos dma1=system.pc.south_bridge.dma1 +eventq_index=0 io_apic=system.pc.south_bridge.io_apic keyboard=system.pc.south_bridge.keyboard pic1=system.pc.south_bridge.pic1 @@ -1266,6 +1392,7 @@ speaker=system.pc.south_bridge.speaker type=Cmos children=int_pin clk_domain=system.clk_domain +eventq_index=0 int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=100000 @@ -1275,10 +1402,12 @@ pio=system.iobus.master[1] [system.pc.south_bridge.cmos.int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.dma1] type=I8237 clk_domain=system.clk_domain +eventq_index=0 pio_addr=9223372036854775808 pio_latency=100000 system=system @@ -1307,6 +1436,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -1316,8 +1446,40 @@ HeaderType=0 InterruptLine=14 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=128 Revision=0 Status=640 @@ -1329,6 +1491,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=4 @@ -1345,19 +1508,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.pc.south_bridge.ide.disks0.image [system.pc.south_bridge.ide.disks0.image] type=CowDiskImage children=child child=system.pc.south_bridge.ide.disks0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1365,102 +1531,120 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.pc.south_bridge.ide.disks1.image [system.pc.south_bridge.ide.disks1.image] type=CowDiskImage children=child child=system.pc.south_bridge.ide.disks1.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines0.sink source=system.pc.south_bridge.pic1.output [system.pc.south_bridge.int_lines0.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=0 [system.pc.south_bridge.int_lines1] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines1.sink source=system.pc.south_bridge.pic2.output [system.pc.south_bridge.int_lines1.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 +eventq_index=0 number=2 [system.pc.south_bridge.int_lines2] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines2.sink source=system.pc.south_bridge.cmos.int_pin [system.pc.south_bridge.int_lines2.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic2 +eventq_index=0 number=0 [system.pc.south_bridge.int_lines3] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines3.sink source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines3.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 +eventq_index=0 number=0 [system.pc.south_bridge.int_lines4] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines4.sink source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines4.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=2 [system.pc.south_bridge.int_lines5] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines5.sink source=system.pc.south_bridge.keyboard.keyboard_int_pin [system.pc.south_bridge.int_lines5.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=1 [system.pc.south_bridge.int_lines6] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines6.sink source=system.pc.south_bridge.keyboard.mouse_int_pin [system.pc.south_bridge.int_lines6.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=12 [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 clk_domain=system.clk_domain +eventq_index=0 external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 @@ -1475,6 +1659,7 @@ children=keyboard_int_pin mouse_int_pin clk_domain=system.clk_domain command_port=9223372036854775908 data_port=9223372036854775904 +eventq_index=0 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 @@ -1484,14 +1669,17 @@ pio=system.iobus.master[5] [system.pc.south_bridge.keyboard.keyboard_int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.keyboard.mouse_int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pic1] type=I8259 children=output clk_domain=system.clk_domain +eventq_index=0 mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 @@ -1502,11 +1690,13 @@ pio=system.iobus.master[6] [system.pc.south_bridge.pic1.output] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pic2] type=I8259 children=output clk_domain=system.clk_domain +eventq_index=0 mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 @@ -1517,11 +1707,13 @@ pio=system.iobus.master[7] [system.pc.south_bridge.pic2.output] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pit] type=I8254 children=int_pin clk_domain=system.clk_domain +eventq_index=0 int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=100000 @@ -1530,10 +1722,12 @@ pio=system.iobus.master[8] [system.pc.south_bridge.pit.int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.speaker] type=PcSpeaker clk_domain=system.clk_domain +eventq_index=0 i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=100000 @@ -1552,6 +1746,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -1563,19 +1758,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[3] [system.smbios_table] type=X86SMBiosSMBiosTable children=structures +eventq_index=0 major_version=2 minor_version=5 structures=system.smbios_table.structures @@ -1586,6 +1785,7 @@ characteristic_ext_bytes= characteristics= emb_cont_firmware_major=0 emb_cont_firmware_minor=0 +eventq_index=0 major=0 minor=0 release_date=06/08/2008 @@ -1596,5 +1796,6 @@ version= [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 8fd17006a..f9f231b7b 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,135 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.133932 # Number of seconds simulated -sim_ticks 5133932129000 # Number of ticks simulated -final_tick 5133932129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.133933 # Number of seconds simulated +sim_ticks 5133933067000 # Number of ticks simulated +final_tick 5133933067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 157497 # Simulator instruction rate (inst/s) -host_op_rate 311329 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1982921852 # Simulator tick rate (ticks/s) -host_mem_usage 759792 # Number of bytes of host memory used -host_seconds 2589.07 # Real time elapsed on the host -sim_insts 407772261 # Number of instructions simulated -sim_ops 806052921 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2442496 # Number of bytes read from this memory +host_inst_rate 121984 # Simulator instruction rate (inst/s) +host_op_rate 241126 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1535878817 # Simulator tick rate (ticks/s) +host_mem_usage 781700 # Number of bytes of host memory used +host_seconds 3342.67 # Real time elapsed on the host +sim_insts 407751929 # Number of instructions simulated +sim_ops 806002693 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2437184 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1029568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10759232 # Number of bytes read from this memory -system.physmem.bytes_read::total 14235520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1029568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1029568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9509568 # Number of bytes written to this memory -system.physmem.bytes_written::total 9509568 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38164 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1029376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10746496 # Number of bytes read from this memory +system.physmem.bytes_read::total 14217280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1029376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1029376 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9492672 # Number of bytes written to this memory +system.physmem.bytes_written::total 9492672 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38081 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16087 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168113 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222430 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 148587 # Number of write requests responded to by this memory -system.physmem.num_writes::total 148587 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 475755 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16084 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 167914 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222145 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 148323 # Number of write requests responded to by this memory +system.physmem.num_writes::total 148323 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 474721 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 760 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 200542 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2095710 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2772830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 200542 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 200542 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1852297 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1852297 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1852297 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 475755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 200504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2093229 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2769276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 200504 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 200504 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1849006 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1849006 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1849006 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 474721 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 760 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 200542 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2095710 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4625127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222430 # Number of read requests accepted -system.physmem.writeReqs 148587 # Number of write requests accepted -system.physmem.readBursts 222430 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 148587 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 14231616 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3904 # Total number of bytes read from write queue -system.physmem.bytesWritten 9508480 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 14235520 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9509568 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 61 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.inst 200504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2093229 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4618282 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222145 # Number of read requests accepted +system.physmem.writeReqs 148323 # Number of write requests accepted +system.physmem.readBursts 222145 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 148323 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14211648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue +system.physmem.bytesWritten 9492416 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14217280 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9492672 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1723 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 14853 # Per bank write bursts -system.physmem.perBankRdBursts::1 13635 # Per bank write bursts -system.physmem.perBankRdBursts::2 14415 # Per bank write bursts -system.physmem.perBankRdBursts::3 13770 # Per bank write bursts -system.physmem.perBankRdBursts::4 14136 # Per bank write bursts -system.physmem.perBankRdBursts::5 13341 # Per bank write bursts -system.physmem.perBankRdBursts::6 13755 # Per bank write bursts -system.physmem.perBankRdBursts::7 13953 # Per bank write bursts -system.physmem.perBankRdBursts::8 13590 # Per bank write bursts -system.physmem.perBankRdBursts::9 13369 # Per bank write bursts -system.physmem.perBankRdBursts::10 13469 # Per bank write bursts -system.physmem.perBankRdBursts::11 13962 # Per bank write bursts -system.physmem.perBankRdBursts::12 14252 # Per bank write bursts -system.physmem.perBankRdBursts::13 14454 # Per bank write bursts -system.physmem.perBankRdBursts::14 13844 # Per bank write bursts -system.physmem.perBankRdBursts::15 13571 # Per bank write bursts -system.physmem.perBankWrBursts::0 10225 # Per bank write bursts -system.physmem.perBankWrBursts::1 9089 # Per bank write bursts -system.physmem.perBankWrBursts::2 9605 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 1715 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 14970 # Per bank write bursts +system.physmem.perBankRdBursts::1 13960 # Per bank write bursts +system.physmem.perBankRdBursts::2 14769 # Per bank write bursts +system.physmem.perBankRdBursts::3 13764 # Per bank write bursts +system.physmem.perBankRdBursts::4 13644 # Per bank write bursts +system.physmem.perBankRdBursts::5 13392 # Per bank write bursts +system.physmem.perBankRdBursts::6 13407 # Per bank write bursts +system.physmem.perBankRdBursts::7 13589 # Per bank write bursts +system.physmem.perBankRdBursts::8 13408 # Per bank write bursts +system.physmem.perBankRdBursts::9 13258 # Per bank write bursts +system.physmem.perBankRdBursts::10 13821 # Per bank write bursts +system.physmem.perBankRdBursts::11 13878 # Per bank write bursts +system.physmem.perBankRdBursts::12 14332 # Per bank write bursts +system.physmem.perBankRdBursts::13 14527 # Per bank write bursts +system.physmem.perBankRdBursts::14 13749 # Per bank write bursts +system.physmem.perBankRdBursts::15 13589 # Per bank write bursts +system.physmem.perBankWrBursts::0 10370 # Per bank write bursts +system.physmem.perBankWrBursts::1 9405 # Per bank write bursts +system.physmem.perBankWrBursts::2 9871 # Per bank write bursts system.physmem.perBankWrBursts::3 9165 # Per bank write bursts -system.physmem.perBankWrBursts::4 9475 # Per bank write bursts -system.physmem.perBankWrBursts::5 8866 # Per bank write bursts -system.physmem.perBankWrBursts::6 9032 # Per bank write bursts -system.physmem.perBankWrBursts::7 9363 # Per bank write bursts -system.physmem.perBankWrBursts::8 8843 # Per bank write bursts -system.physmem.perBankWrBursts::9 8764 # Per bank write bursts -system.physmem.perBankWrBursts::10 9099 # Per bank write bursts -system.physmem.perBankWrBursts::11 9352 # Per bank write bursts -system.physmem.perBankWrBursts::12 9596 # Per bank write bursts -system.physmem.perBankWrBursts::13 9639 # Per bank write bursts -system.physmem.perBankWrBursts::14 9447 # Per bank write bursts -system.physmem.perBankWrBursts::15 9010 # Per bank write bursts +system.physmem.perBankWrBursts::4 9017 # Per bank write bursts +system.physmem.perBankWrBursts::5 8953 # Per bank write bursts +system.physmem.perBankWrBursts::6 8740 # Per bank write bursts +system.physmem.perBankWrBursts::7 8992 # Per bank write bursts +system.physmem.perBankWrBursts::8 8721 # Per bank write bursts +system.physmem.perBankWrBursts::9 8568 # Per bank write bursts +system.physmem.perBankWrBursts::10 9309 # Per bank write bursts +system.physmem.perBankWrBursts::11 9216 # Per bank write bursts +system.physmem.perBankWrBursts::12 9686 # Per bank write bursts +system.physmem.perBankWrBursts::13 9800 # Per bank write bursts +system.physmem.perBankWrBursts::14 9415 # Per bank write bursts +system.physmem.perBankWrBursts::15 9091 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 5133932076000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry +system.physmem.totGap 5133933013500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 222430 # Read request sizes (log2) +system.physmem.readPktSize::6 222145 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 148587 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 174915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21440 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2079 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1580 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1083 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148323 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 174666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2066 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1506 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1430 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1072 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 864 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 749 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 676 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 638 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 585 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 656 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 606 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 571 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 555 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -139,266 +139,264 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 6034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 6271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 7025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 7124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 7641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 7124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 7239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 25 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69161 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 343.214933 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 150.395098 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1078.627974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 31181 45.08% 45.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 10634 15.38% 60.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 6892 9.97% 70.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 4363 6.31% 76.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 2774 4.01% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 2145 3.10% 83.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1632 2.36% 86.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 1184 1.71% 87.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 1083 1.57% 89.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 997 1.44% 90.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 641 0.93% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 593 0.86% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 458 0.66% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 430 0.62% 93.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 348 0.50% 94.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 543 0.79% 95.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 251 0.36% 95.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 231 0.33% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 148 0.21% 96.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 131 0.19% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 159 0.23% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 414 0.60% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 146 0.21% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 132 0.19% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 102 0.15% 97.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 88 0.13% 97.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 59 0.09% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 56 0.08% 98.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 31 0.04% 98.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 34 0.05% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 24 0.03% 98.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 33 0.05% 98.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 49 0.07% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 19 0.03% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 13 0.02% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 10 0.01% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 32 0.05% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 8 0.01% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 7 0.01% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 11 0.02% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 29 0.04% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 12 0.02% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 12 0.02% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 3 0.00% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 32 0.05% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 7 0.01% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 13 0.02% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 8 0.01% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 25 0.04% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 5 0.01% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 4 0.01% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 26 0.04% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 2 0.00% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 7 0.01% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 5 0.01% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 31 0.04% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 9 0.01% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 7 0.01% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 28 0.04% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 5 0.01% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 17 0.02% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 2 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 24 0.03% 98.94% # Bytes accessed per row activation +system.physmem.wrQLenPdf::0 6022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 6256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 7022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 7020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 7083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 7644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 7121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 7236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 68754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 344.735608 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 150.882581 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1084.800437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 30893 44.93% 44.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 10573 15.38% 60.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 6859 9.98% 70.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 4406 6.41% 76.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 2663 3.87% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 2166 3.15% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1652 2.40% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 1226 1.78% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 1018 1.48% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 978 1.42% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 656 0.95% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 637 0.93% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 446 0.65% 93.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 438 0.64% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 344 0.50% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 542 0.79% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 252 0.37% 95.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 218 0.32% 95.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 163 0.24% 96.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 136 0.20% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 158 0.23% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 420 0.61% 97.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 150 0.22% 97.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 127 0.18% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 107 0.16% 97.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 87 0.13% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 59 0.09% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 64 0.09% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 17 0.02% 98.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 43 0.06% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 19 0.03% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 31 0.05% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 40 0.06% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 10 0.01% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 13 0.02% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 16 0.02% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 31 0.05% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 10 0.01% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 6 0.01% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 13 0.02% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 31 0.05% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 12 0.02% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 4 0.01% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 6 0.01% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 27 0.04% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 9 0.01% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 12 0.02% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 6 0.01% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 28 0.04% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 7 0.01% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 25 0.04% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 3 0.00% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 5 0.01% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 5 0.01% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 26 0.04% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 10 0.01% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 5 0.01% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 9 0.01% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 28 0.04% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 4 0.01% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 15 0.02% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 3 0.00% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 27 0.04% 98.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::4288-4291 3 0.00% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 2 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 1 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 22 0.03% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 2 0.00% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 2 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 23 0.03% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 3 0.00% 98.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 3 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 28 0.04% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 2 0.00% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 5 0.01% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 25 0.04% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 4 0.01% 99.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::4864-4867 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 2 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 23 0.03% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 3 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 22 0.03% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 2 0.00% 99.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::5120-5123 3 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 3 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 4 0.01% 99.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::5248-5251 26 0.04% 99.12% # Bytes accessed per row activation system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 1 0.00% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 2 0.00% 99.12% # Bytes accessed per row activation system.physmem.bytesPerActivate::5504-5507 22 0.03% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 5 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 4 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 2 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 26 0.04% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 3 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 25 0.04% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 6 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 3 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 5 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 25 0.04% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 2 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 3 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 26 0.04% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 3 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 76 0.11% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 4 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 6 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 6 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 6 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 11 0.02% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 3 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 3 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 4 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 2 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 2 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 14 0.02% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 3 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 3 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 6 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9731 3 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 3 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 4 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10243 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 4 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 3 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 24 0.03% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 4 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 24 0.03% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 3 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 24 0.03% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 3 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 4 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 23 0.03% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 4 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 75 0.11% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 3 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 2 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 5 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 5 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 3 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 9 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 11 0.02% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7491 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 3 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 4 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 3 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 5 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 3 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 15 0.02% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8515 5 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8643 2 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 2 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 4 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 4 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9603 4 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9923 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9987 3 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 3 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.65% # Bytes accessed per row activation system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11267 4 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11331 2 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 2 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11971 3 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12099 4 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11139 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11203 2 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 3 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 3 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 2 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11907 1 0.00% 99.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::12160-12163 2 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12611 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12739 2 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12995 1 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13443 2 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13891 6 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 2 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 3 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 5 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 5 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 3 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 20 0.03% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 9 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 2 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 3 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12931 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 2 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 3 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 6 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 5 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 4 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 2 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 25 0.04% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 6 0.01% 99.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::15040-15043 8 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 5 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 7 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 3 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 4 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 14 0.02% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 5 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 3 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 2 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 2 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 4 0.01% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 9 0.01% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 5 0.01% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 4 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 3 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 8 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 3 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 14 0.02% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 2 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 4 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 5 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 4 0.01% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 10 0.01% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 9 0.01% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::16384-16387 42 0.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69161 # Bytes accessed per row activation -system.physmem.totQLat 5163279754 # Total ticks spent queuing -system.physmem.totMemAccLat 9388468504 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1111845000 # Total ticks spent in databus transfers -system.physmem.totBankLat 3113343750 # Total ticks spent accessing banks -system.physmem.avgQLat 23219.42 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14000.80 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::total 68754 # Bytes accessed per row activation +system.physmem.totQLat 5103462500 # Total ticks spent queuing +system.physmem.totMemAccLat 9310522500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1110285000 # Total ticks spent in databus transfers +system.physmem.totBankLat 3096775000 # Total ticks spent accessing banks +system.physmem.avgQLat 22982.67 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13945.86 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42220.22 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 41928.53 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.77 # Average system read bandwidth in MiByte/s @@ -408,71 +406,71 @@ system.physmem.busUtil 0.04 # Da system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.54 # Average write queue length when enqueuing -system.physmem.readRowHits 193089 # Number of row buffer hits during reads -system.physmem.writeRowHits 108689 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes -system.physmem.avgGap 13837457.79 # Average gap between requests -system.physmem.pageHitRate 81.35 # Row buffer hit rate, read and write combined +system.physmem.avgWrQLen 8.57 # Average write queue length when enqueuing +system.physmem.readRowHits 193293 # Number of row buffer hits during reads +system.physmem.writeRowHits 108329 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.04 # Row buffer hit rate for writes +system.physmem.avgGap 13857966.18 # Average gap between requests +system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 0.14 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 5101771 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 662370 # Transaction distribution -system.membus.trans_dist::ReadResp 662362 # Transaction distribution -system.membus.trans_dist::WriteReq 13778 # Transaction distribution -system.membus.trans_dist::WriteResp 13778 # Transaction distribution -system.membus.trans_dist::Writeback 148587 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2227 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1742 # Transaction distribution -system.membus.trans_dist::ReadExReq 179504 # Transaction distribution -system.membus.trans_dist::ReadExResp 179502 # Transaction distribution -system.membus.trans_dist::MessageReq 1643 # Transaction distribution -system.membus.trans_dist::MessageResp 1643 # Transaction distribution -system.membus.trans_dist::BadAddressError 8 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721244 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132462 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 132462 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1856992 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550145 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18315904 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20107877 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5429184 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5429184 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25543633 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25543633 # Total data (bytes) -system.membus.snoop_data_through_bus 648512 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 250559500 # Layer occupancy (ticks) +system.membus.throughput 5095991 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 662317 # Transaction distribution +system.membus.trans_dist::ReadResp 662311 # Transaction distribution +system.membus.trans_dist::WriteReq 13762 # Transaction distribution +system.membus.trans_dist::WriteResp 13762 # Transaction distribution +system.membus.trans_dist::Writeback 148323 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2201 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1734 # Transaction distribution +system.membus.trans_dist::ReadExReq 179351 # Transaction distribution +system.membus.trans_dist::ReadExResp 179346 # Transaction distribution +system.membus.trans_dist::MessageReq 1642 # Transaction distribution +system.membus.trans_dist::MessageResp 1642 # Transaction distribution +system.membus.trans_dist::BadAddressError 6 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471038 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 474374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1720496 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132379 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 132379 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1856159 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241802 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18286080 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20078023 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5423872 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5423872 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25508463 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25508463 # Total data (bytes) +system.membus.snoop_data_through_bus 654016 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 250556000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583301000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583258500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3284000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1608447497 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1605908499 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1642000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3153020380 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3150989153 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 429468745 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 429464748 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 47576 # number of replacements -system.iocache.tags.tagsinuse 0.103982 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.103980 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992954297000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103982 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 4992951939000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103980 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006499 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.006499 # Average percentage of cache occupancy system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses @@ -483,14 +481,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47631 system.iocache.demand_misses::total 47631 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses system.iocache.overall_misses::total 47631 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149420946 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 149420946 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11534885027 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11534885027 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 11684305973 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11684305973 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 11684305973 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11684305973 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151022435 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 151022435 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11480088301 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11480088301 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 11631110736 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11631110736 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 11631110736 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11631110736 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) @@ -507,19 +505,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 164018.601537 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 164018.601537 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 246893.943215 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 246893.943215 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 245308.852911 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 245308.852911 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 245308.852911 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 245308.852911 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 173314 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165776.547750 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 165776.547750 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 245721.068086 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 245721.068086 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 244192.033256 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 244192.033256 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 244192.033256 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 244192.033256 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 172788 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10321 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10383 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 16.792365 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 16.641433 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -533,14 +531,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 102021946 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 102021946 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9103892537 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9103892537 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9205914483 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9205914483 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9205914483 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9205914483 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 103624935 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 103624935 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9049102305 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9049102305 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9152727240 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9152727240 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9152727240 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9152727240 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -549,18 +547,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111988.963776 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 111988.963776 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 194860.713549 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 194860.713549 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 193275.691944 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 193275.691944 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 193275.691944 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 193275.691944 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113748.556531 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 113748.556531 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 193687.977419 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 193687.977419 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 192159.040121 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 192159.040121 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 192159.040121 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 192159.040121 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -570,16 +568,16 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 638153 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 225567 # Transaction distribution -system.iobus.trans_dist::ReadResp 225567 # Transaction distribution -system.iobus.trans_dist::WriteReq 57606 # Transaction distribution -system.iobus.trans_dist::WriteResp 57606 # Transaction distribution -system.iobus.trans_dist::MessageReq 1643 # Transaction distribution -system.iobus.trans_dist::MessageResp 1643 # Transaction distribution +system.iobus.throughput 638147 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 225559 # Transaction distribution +system.iobus.trans_dist::ReadResp 225559 # Transaction distribution +system.iobus.trans_dist::WriteReq 57591 # Transaction distribution +system.iobus.trans_dist::WriteResp 57591 # Transaction distribution +system.iobus.trans_dist::MessageReq 1642 # Transaction distribution +system.iobus.trans_dist::MessageResp 1642 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) @@ -595,15 +593,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 471038 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95262 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95262 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 569632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3284 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 569584 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) @@ -619,20 +617,20 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 241802 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027832 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027832 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3276232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3276232 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3917850 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3276202 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3276202 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3916600 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -662,153 +660,153 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424362228 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 424364988 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 460167000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 53078255 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 53080252 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1642000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 85592238 # Number of BP lookups -system.cpu.branchPred.condPredicted 85592238 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 882873 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79245732 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77532748 # Number of BTB hits +system.cpu.branchPred.lookups 85602749 # Number of BP lookups +system.cpu.branchPred.condPredicted 85602749 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 882967 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79146839 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77528417 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.838390 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1439092 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 180819 # Number of incorrect RAS predictions. -system.cpu.numCycles 453841851 # number of cpu cycles simulated +system.cpu.branchPred.BTBHitPct 97.955165 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1444593 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 180696 # Number of incorrect RAS predictions. +system.cpu.numCycles 453810576 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25587982 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 422693278 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85592238 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 78971840 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 162652701 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3982002 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 104057 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 71419426 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 42857 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 89331 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 200 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8481476 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 385696 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2322 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 262951613 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.174902 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.411090 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25587128 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 422793434 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85602749 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 78973010 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162653475 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3995125 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 108453 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 71359520 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 43835 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87857 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 286 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8489508 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 384110 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2391 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 262908725 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.175877 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.411274 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 100714901 38.30% 38.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1542522 0.59% 38.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71823019 27.31% 66.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 902488 0.34% 66.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1566536 0.60% 67.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2391041 0.91% 68.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1017988 0.39% 68.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1324647 0.50% 68.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81668471 31.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 100670178 38.29% 38.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1530444 0.58% 38.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71820335 27.32% 66.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 896426 0.34% 66.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1566584 0.60% 67.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2396730 0.91% 68.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1019321 0.39% 68.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1330214 0.51% 68.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81678493 31.07% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 262951613 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.188595 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.931367 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29471400 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 68588335 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158500700 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3336119 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3055059 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 832519072 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 997 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3055059 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32166739 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 43365867 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12492763 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158788078 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13083107 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 829619005 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21424 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6060149 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5145730 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 991238350 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1800229618 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1106821161 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 116 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 963974807 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27263541 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 455448 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 461036 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 29565034 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 16718678 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9823839 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1099301 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 921701 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 824848453 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1187045 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 820941370 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 145995 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19149103 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29112205 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 132366 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 262951613 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.122024 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.401319 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 262908725 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.188631 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.931652 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29469022 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 68533895 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158500921 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3336716 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3068171 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 832628882 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1005 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3068171 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32166033 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 43333689 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12473461 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158788115 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13079256 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 829706187 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21464 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6056720 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5143219 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 991368832 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1800529447 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1106981108 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 114 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963921381 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27447449 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 454679 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 459073 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 29562257 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 16738170 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9831898 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1099509 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 931888 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 824922108 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1185282 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 820965230 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 150616 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19266581 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29327510 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 130776 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 262908725 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.122625 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.401229 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 76573555 29.12% 29.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15783174 6.00% 35.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10543493 4.01% 39.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7363188 2.80% 41.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75733020 28.80% 70.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3745069 1.42% 72.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72294186 27.49% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 768319 0.29% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 147609 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 76541753 29.11% 29.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15760378 5.99% 35.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10546081 4.01% 39.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7369618 2.80% 41.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75729447 28.80% 70.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3748882 1.43% 72.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72293205 27.50% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 772480 0.29% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 146881 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 262951613 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 262908725 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 346888 33.04% 33.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 241 0.02% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 2034 0.19% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547279 52.12% 85.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 153573 14.63% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 349560 33.18% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 241 0.02% 33.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 1967 0.19% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 548780 52.08% 85.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 153094 14.53% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 309747 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 793469361 96.65% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 149710 0.02% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 124599 0.02% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 307236 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 793474466 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 149866 0.02% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 124488 0.02% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued @@ -835,283 +833,283 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17668051 2.15% 98.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9219902 1.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17682042 2.15% 98.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9227132 1.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 820941370 # Type of FU issued -system.cpu.iq.rate 1.808871 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1050015 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001279 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1906138377 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 845194990 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 817033315 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 197 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 821681548 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1692176 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 820965230 # Type of FU issued +system.cpu.iq.rate 1.809048 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1053642 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001283 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1906151693 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 845384400 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 817050943 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 198 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 821711543 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 93 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1694469 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2727781 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18489 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12047 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1402321 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2748093 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 19141 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11819 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1409863 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1931655 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 11924 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1931395 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11998 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3055059 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 31495600 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2151607 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 826035498 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 247681 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 16718678 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9823839 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 691406 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1620111 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12282 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12047 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 498908 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 509123 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1008031 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819536653 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17366589 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1404716 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3068171 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 31463417 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2151711 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 826107390 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 248376 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 16738170 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9831898 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 690155 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1620159 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12279 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11819 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 498534 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 508074 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1006608 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819554351 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17378079 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1410878 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26403509 # number of memory reference insts executed -system.cpu.iew.exec_branches 83090404 # Number of branches executed -system.cpu.iew.exec_stores 9036920 # Number of stores executed -system.cpu.iew.exec_rate 1.805776 # Inst execution rate -system.cpu.iew.wb_sent 819134916 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 817033367 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638560375 # num instructions producing a value -system.cpu.iew.wb_consumers 1043850178 # num instructions consuming a value +system.cpu.iew.exec_refs 26421028 # number of memory reference insts executed +system.cpu.iew.exec_branches 83090233 # Number of branches executed +system.cpu.iew.exec_stores 9042949 # Number of stores executed +system.cpu.iew.exec_rate 1.805939 # Inst execution rate +system.cpu.iew.wb_sent 819150966 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 817050997 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638575855 # num instructions producing a value +system.cpu.iew.wb_consumers 1043882621 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.800260 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611736 # average fanout of values written-back +system.cpu.iew.wb_rate 1.800423 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611731 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19875138 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1054679 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 892733 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 259896554 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.101438 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.863911 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 19994665 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1054506 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 892807 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 259840554 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.101913 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.863847 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 88349043 33.99% 33.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11862829 4.56% 38.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3832305 1.47% 40.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74754047 28.76% 68.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2383630 0.92% 69.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1474941 0.57% 70.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 857586 0.33% 70.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70848784 27.26% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5533389 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 88304488 33.98% 33.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11858711 4.56% 38.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3833949 1.48% 40.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74748511 28.77% 68.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2384583 0.92% 69.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1475819 0.57% 70.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 859128 0.33% 70.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70844564 27.26% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5530801 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 259896554 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407772261 # Number of instructions committed -system.cpu.commit.committedOps 806052921 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 259840554 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407751929 # Number of instructions committed +system.cpu.commit.committedOps 806002693 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22412414 # Number of memory references committed -system.cpu.commit.loads 13990896 # Number of loads committed -system.cpu.commit.membars 474709 # Number of memory barriers committed -system.cpu.commit.branches 82160310 # Number of branches committed +system.cpu.commit.refs 22412111 # Number of memory references committed +system.cpu.commit.loads 13990076 # Number of loads committed +system.cpu.commit.membars 474663 # Number of memory barriers committed +system.cpu.commit.branches 82157264 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 734896243 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155289 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5533389 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 734852381 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155163 # Number of function calls committed. +system.cpu.commit.bw_lim_events 5530801 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1080212949 # The number of ROB reads -system.cpu.rob.rob_writes 1654925831 # The number of ROB writes -system.cpu.timesIdled 1261862 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 190890238 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9814027971 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407772261 # Number of Instructions Simulated -system.cpu.committedOps 806052921 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407772261 # Number of Instructions Simulated -system.cpu.cpi 1.112979 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.112979 # CPI: Total CPI of All Threads -system.cpu.ipc 0.898490 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.898490 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1088746320 # number of integer regfile reads -system.cpu.int_regfile_writes 653799671 # number of integer regfile writes -system.cpu.fp_regfile_reads 52 # number of floating regfile reads -system.cpu.cc_regfile_reads 415603862 # number of cc regfile reads -system.cpu.cc_regfile_writes 321491324 # number of cc regfile writes -system.cpu.misc_regfile_reads 264059604 # number of misc regfile reads -system.cpu.misc_regfile_writes 402440 # number of misc regfile writes -system.cpu.toL2Bus.throughput 53738291 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3018879 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3018337 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13778 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13778 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1585586 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2261 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2261 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 334835 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 288140 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1919324 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6124632 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18318 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159709 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8221983 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61414400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207642981 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 603136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5731328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 275391845 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 275366117 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 522624 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4046374411 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 1080228878 # The number of ROB reads +system.cpu.rob.rob_writes 1655077473 # The number of ROB writes +system.cpu.timesIdled 1260592 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 190901851 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9814061063 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407751929 # Number of Instructions Simulated +system.cpu.committedOps 806002693 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407751929 # Number of Instructions Simulated +system.cpu.cpi 1.112958 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.112958 # CPI: Total CPI of All Threads +system.cpu.ipc 0.898507 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.898507 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1088763208 # number of integer regfile reads +system.cpu.int_regfile_writes 653821136 # number of integer regfile writes +system.cpu.fp_regfile_reads 54 # number of floating regfile reads +system.cpu.cc_regfile_reads 415622850 # number of cc regfile reads +system.cpu.cc_regfile_writes 321492626 # number of cc regfile writes +system.cpu.misc_regfile_reads 264082516 # number of misc regfile reads +system.cpu.misc_regfile_writes 402300 # number of misc regfile writes +system.cpu.toL2Bus.throughput 53661983 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3016761 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3016231 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13762 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13762 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1581663 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2241 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2241 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 334732 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 288041 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916491 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6123200 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19443 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 154439 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8213573 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61324288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207594695 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 616960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5463872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 274999815 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 274973191 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 523840 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4039348922 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 603000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 624000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1442983054 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1440815600 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3140518579 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3139539816 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 13344744 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 14707994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 105297384 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 103656142 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 959142 # number of replacements -system.cpu.icache.tags.tagsinuse 509.299647 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7468451 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 959654 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.782441 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 957724 # number of replacements +system.cpu.icache.tags.tagsinuse 509.254964 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7477774 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 958236 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.803687 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 147611306250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.299647 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994726 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994726 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7468451 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7468451 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7468451 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7468451 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7468451 # number of overall hits -system.cpu.icache.overall_hits::total 7468451 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1013022 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1013022 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1013022 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1013022 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1013022 # number of overall misses -system.cpu.icache.overall_misses::total 1013022 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14172498740 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14172498740 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14172498740 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14172498740 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14172498740 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14172498740 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8481473 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8481473 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8481473 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8481473 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8481473 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8481473 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119439 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.119439 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.119439 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.119439 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.119439 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.119439 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13990.316834 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13990.316834 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13990.316834 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13990.316834 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13990.316834 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13990.316834 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 509.254964 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994639 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994639 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7477774 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7477774 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7477774 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7477774 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7477774 # number of overall hits +system.cpu.icache.overall_hits::total 7477774 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1011731 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1011731 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1011731 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1011731 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1011731 # number of overall misses +system.cpu.icache.overall_misses::total 1011731 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14180716030 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14180716030 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14180716030 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14180716030 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14180716030 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14180716030 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8489505 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8489505 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8489505 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8489505 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8489505 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8489505 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119174 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.119174 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.119174 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.119174 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.119174 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.119174 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14016.290921 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14016.290921 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14016.290921 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14016.290921 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14016.290921 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14016.290921 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5333 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 172 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 185 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 26.023256 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.827027 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53298 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 53298 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 53298 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 53298 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 53298 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 53298 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 959724 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 959724 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 959724 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 959724 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 959724 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 959724 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11694537694 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11694537694 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11694537694 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11694537694 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11694537694 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11694537694 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.113155 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.113155 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.113155 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12185.313376 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12185.313376 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12185.313376 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12185.313376 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12185.313376 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12185.313376 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53432 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 53432 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 53432 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 53432 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 53432 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 53432 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958299 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 958299 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 958299 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 958299 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 958299 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 958299 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11693776143 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11693776143 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11693776143 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11693776143 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11693776143 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11693776143 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112880 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112880 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112880 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.112880 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112880 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.112880 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12202.638365 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12202.638365 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12202.638365 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12202.638365 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12202.638365 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12202.638365 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 8004 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.959011 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 21893 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 8020 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.729800 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5103903665500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.959011 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.434938 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.434938 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21891 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 21891 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 8926 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.004704 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 20407 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 8940 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.282662 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5105549292500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.004704 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375294 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.375294 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20415 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 20415 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21893 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 21893 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21893 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 21893 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8894 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 8894 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8894 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 8894 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8894 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 8894 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 101842497 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 101842497 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 101842497 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 101842497 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 101842497 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 101842497 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30785 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 30785 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 20417 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 20417 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 20417 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 20417 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9803 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 9803 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9803 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 9803 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9803 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 9803 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 109186247 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 109186247 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 109186247 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 109186247 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 109186247 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 109186247 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30218 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 30218 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30787 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 30787 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30787 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 30787 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.288907 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.288907 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.288888 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.288888 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.288888 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.288888 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11450.696762 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11450.696762 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11450.696762 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11450.696762 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11450.696762 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11450.696762 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30220 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 30220 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30220 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 30220 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.324409 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.324409 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.324388 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.324388 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.324388 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.324388 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11138.044170 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11138.044170 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11138.044170 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11138.044170 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11138.044170 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11138.044170 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1120,78 +1118,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 2197 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 2197 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8894 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8894 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8894 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 8894 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8894 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 8894 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 84047009 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 84047009 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 84047009 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 84047009 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 84047009 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 84047009 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.288907 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.288907 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.288888 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.288888 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.288888 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.288888 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9449.854846 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9449.854846 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9449.854846 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1993 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1993 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9803 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9803 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9803 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 9803 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9803 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 9803 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 89573259 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 89573259 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 89573259 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 89573259 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 89573259 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 89573259 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.324409 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.324409 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.324388 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.324388 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.324388 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.324388 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9137.331327 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9137.331327 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9137.331327 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9137.331327 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9137.331327 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9137.331327 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 69051 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 14.134079 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 90874 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 69067 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.315737 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 4994243678000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.134079 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.883380 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.883380 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90874 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 90874 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90874 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 90874 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90874 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 90874 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 70157 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 70157 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 70157 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 70157 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 70157 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 70157 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 871654701 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 871654701 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 871654701 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 871654701 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 871654701 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 871654701 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 161031 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 161031 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 161031 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 161031 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 161031 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 161031 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.435674 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.435674 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.435674 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.435674 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.435674 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.435674 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12424.343986 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12424.343986 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12424.343986 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12424.343986 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12424.343986 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12424.343986 # average overall miss latency +system.cpu.dtb_walker_cache.tags.replacements 68011 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 14.842846 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 91726 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 68027 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.348376 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 4994240386000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.842846 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.927678 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.927678 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 91726 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 91726 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 91726 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 91726 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 91726 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 91726 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 69066 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 69066 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 69066 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 69066 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 69066 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 69066 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 860977213 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 860977213 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 860977213 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 860977213 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 860977213 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 860977213 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 160792 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 160792 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 160792 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 160792 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 160792 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 160792 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429536 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429536 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429536 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429536 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429536 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429536 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12466.006617 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12466.006617 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12466.006617 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12466.006617 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12466.006617 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12466.006617 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1200,146 +1198,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 24645 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 24645 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 70157 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 70157 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 70157 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 70157 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 70157 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 70157 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 731216933 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 731216933 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 731216933 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 731216933 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 731216933 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 731216933 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.435674 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.435674 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.435674 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10422.579828 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10422.579828 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10422.579828 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 21216 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 21216 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 69066 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 69066 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 69066 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 69066 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 69066 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 69066 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 722730929 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 722730929 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 722730929 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 722730929 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 722730929 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 722730929 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429536 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429536 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429536 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429536 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429536 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429536 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10464.351910 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10464.351910 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10464.351910 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1657437 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.988912 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18989388 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1657949 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.453542 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1656829 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997280 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18997986 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1657341 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.462931 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 39724250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.988912 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999978 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999978 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10890920 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10890920 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8095777 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8095777 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 18986697 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18986697 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18986697 # number of overall hits -system.cpu.dcache.overall_hits::total 18986697 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2234479 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2234479 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316198 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316198 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2550677 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2550677 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2550677 # number of overall misses -system.cpu.dcache.overall_misses::total 2550677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33004921637 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33004921637 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12257889032 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12257889032 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45262810669 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45262810669 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45262810669 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45262810669 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13125399 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13125399 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8411975 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8411975 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21537374 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21537374 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21537374 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21537374 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170241 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.170241 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037589 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037589 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118430 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118430 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118430 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118430 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14770.745949 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14770.745949 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38766.497676 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38766.497676 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17745.410598 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17745.410598 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17745.410598 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17745.410598 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 397669 # number of cycles access was blocked +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997280 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10898836 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10898836 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8096443 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8096443 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 18995279 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18995279 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18995279 # number of overall hits +system.cpu.dcache.overall_hits::total 18995279 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2236048 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2236048 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316058 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316058 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2552106 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2552106 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2552106 # number of overall misses +system.cpu.dcache.overall_misses::total 2552106 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33041447208 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33041447208 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12234670517 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12234670517 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45276117725 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45276117725 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45276117725 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45276117725 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13134884 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13134884 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8412501 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8412501 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21547385 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21547385 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21547385 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21547385 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170237 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.170237 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037570 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037570 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118442 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118442 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118442 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118442 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14776.716425 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14776.716425 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38710.206725 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38710.206725 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17740.688563 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17740.688563 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17740.688563 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17740.688563 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 395761 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42042 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42262 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.458851 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.364465 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1558744 # number of writebacks -system.cpu.dcache.writebacks::total 1558744 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864490 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 864490 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25919 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 25919 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 890409 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 890409 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 890409 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 890409 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369989 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1369989 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290279 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 290279 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1660268 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1660268 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1660268 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1660268 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17836083706 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17836083706 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11362753211 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11362753211 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29198836917 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29198836917 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29198836917 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29198836917 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364613500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364613500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2538583500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2538583500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903197000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903197000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104377 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104377 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034508 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034508 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.077088 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077088 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13019.143735 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13019.143735 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39144.248158 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39144.248158 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17586.821475 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17586.821475 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17586.821475 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17586.821475 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1558454 # number of writebacks +system.cpu.dcache.writebacks::total 1558454 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 866560 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 866560 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25905 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 25905 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 892465 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 892465 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 892465 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 892465 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369488 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1369488 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290153 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 290153 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1659641 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1659641 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1659641 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1659641 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17811534705 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17811534705 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11340798474 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11340798474 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29152333179 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29152333179 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29152333179 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29152333179 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97363398000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97363398000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2536146500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2536146500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99899544500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99899544500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104263 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104263 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034491 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034491 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077023 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.077023 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077023 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077023 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13005.980852 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13005.980852 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39085.580621 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39085.580621 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17565.445285 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17565.445285 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17565.445285 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17565.445285 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1347,141 +1345,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 111632 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64821.705622 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3786761 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 175570 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 21.568383 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 111322 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64824.350244 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3788284 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 175285 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 21.612140 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50709.515998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 7.756367 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.126012 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3028.517183 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11075.790063 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.773766 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000118 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50850.934653 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 9.783858 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.126014 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3002.561725 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10960.943994 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.775924 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000149 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046212 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.169003 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989101 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64846 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7222 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 943511 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1333169 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2348748 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1585586 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1585586 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 314 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 314 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 155047 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 155047 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 64846 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 7222 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 943511 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1488216 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2503795 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 64846 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 7222 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 943511 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1488216 # number of overall hits -system.cpu.l2cache.overall_hits::total 2503795 # number of overall hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045815 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.167251 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.989141 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64096 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7642 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 942107 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1332840 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2346685 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1581663 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1581663 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 320 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 320 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 155094 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 155094 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 64096 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 7642 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 942107 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1487934 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2501779 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 64096 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 7642 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 942107 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1487934 # number of overall hits +system.cpu.l2cache.overall_hits::total 2501779 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16089 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 36006 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 52161 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1462 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1462 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133062 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133062 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 16085 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 35964 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 52115 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1454 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1454 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 132906 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 132906 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16089 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 169068 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 185223 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 16085 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 168870 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 185021 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 61 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16089 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 169068 # number of overall misses -system.cpu.l2cache.overall_misses::total 185223 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5260500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1277797734 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2940044940 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 4223492924 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17900790 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 17900790 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9477459899 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9477459899 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5260500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1277797734 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12417504839 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13700952823 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5260500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1277797734 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12417504839 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13700952823 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 64907 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7227 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 959600 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1369175 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2400909 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1585586 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1585586 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1776 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1776 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 288109 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 288109 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64907 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 7227 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 959600 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1657284 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2689018 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64907 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 7227 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 959600 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1657284 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2689018 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000940 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000692 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016766 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026298 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021726 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823198 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823198 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461846 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.461846 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000940 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000692 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016766 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102015 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.068881 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000940 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000692 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016766 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102015 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.068881 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86237.704918 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77950 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79420.581391 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81654.305949 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 80970.321198 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12244.042408 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12244.042408 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71225.893937 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71225.893937 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86237.704918 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77950 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79420.581391 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73446.807433 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73970.040562 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86237.704918 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77950 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79420.581391 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73446.807433 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73970.040562 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.inst 16085 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 168870 # number of overall misses +system.cpu.l2cache.overall_misses::total 185021 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5922249 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 375500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1293203490 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2919351194 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 4218852433 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17719300 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 17719300 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9455061655 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9455061655 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5922249 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 375500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1293203490 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12374412849 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13673914088 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5922249 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 375500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1293203490 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12374412849 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13673914088 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 64157 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7647 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 958192 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1368804 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2398800 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1581663 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1581663 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1774 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1774 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 288000 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 288000 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64157 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 7647 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 958192 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1656804 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2686800 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64157 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 7647 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 958192 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1656804 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2686800 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000951 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000654 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016787 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026274 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021725 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.819617 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.819617 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461479 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.461479 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000951 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000654 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016787 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.101925 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.068863 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000951 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000654 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016787 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.101925 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.068863 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 97086.049180 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75100 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80398.103202 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81174.262985 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80952.747443 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12186.588721 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12186.588721 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71140.969219 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71140.969219 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 97086.049180 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75100 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80398.103202 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73277.745301 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73904.659947 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 97086.049180 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75100 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80398.103202 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73277.745301 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73904.659947 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1490,99 +1488,99 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 101920 # number of writebacks -system.cpu.l2cache.writebacks::total 101920 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 101656 # number of writebacks +system.cpu.l2cache.writebacks::total 101656 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 61 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16087 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36005 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 52158 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1462 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1462 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133062 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133062 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16084 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35963 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 52113 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1454 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1454 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132906 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 132906 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 61 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16087 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 169067 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 185220 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16084 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 168869 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 185019 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 61 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16087 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 169067 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 185220 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4502000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 326250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1075523016 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2491735810 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3572087076 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15586943 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15586943 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7807116101 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7807116101 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4502000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 326250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1075523016 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10298851911 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11379203177 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4502000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 326250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1075523016 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10298851911 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11379203177 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251387000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251387000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2372677500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2372677500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624064500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624064500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026297 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021724 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823198 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823198 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461846 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461846 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102015 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.068880 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102015 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.068880 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66856.655436 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69205.271768 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68485.890487 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10661.383721 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10661.383721 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58672.769844 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58672.769844 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66856.655436 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60915.802084 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61436.147160 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66856.655436 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60915.802084 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61436.147160 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16084 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 168869 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 185019 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5166251 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 312500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1091253760 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2471371556 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3568104067 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15558435 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15558435 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7786682845 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7786682845 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5166251 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 312500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1091253760 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10258054401 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11354786912 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5166251 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 312500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1091253760 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10258054401 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11354786912 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89250274500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89250274500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370476500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370476500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91620751000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91620751000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000951 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000654 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016786 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026273 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021725 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.819617 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.819617 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461479 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461479 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000951 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000654 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016786 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101925 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.068862 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000951 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000654 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016786 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101925 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.068862 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 84692.639344 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67847.162397 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68719.838612 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68468.598373 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10700.436726 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10700.436726 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58587.895543 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58587.895543 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 84692.639344 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67847.162397 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60745.633604 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61370.923592 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 84692.639344 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67847.162397 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60745.633604 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61370.923592 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini index 404746deb..4079b1ad3 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -14,10 +16,11 @@ boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 cache_line_size=64 clk_domain=system.clk_domain e820_table=system.e820_table +eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=atomic mem_ranges=0:134217727 @@ -38,6 +41,7 @@ system_port=system.membus.slave[1] [system.acpi_description_table_pointer] type=X86ACPIRSDP children=xsdt +eventq_index=0 oem_id= revision=2 rsdt=Null @@ -48,6 +52,7 @@ type=X86ACPIXSDT creator_id= creator_revision=0 entries= +eventq_index=0 oem_id= oem_revision=0 oem_table_id= @@ -56,6 +61,7 @@ oem_table_id= type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=11529215046068469760:11529215046068473855 req_size=16 resp_size=16 @@ -66,6 +72,7 @@ slave=system.iobus.master[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615 req_size=16 resp_size=16 @@ -75,6 +82,7 @@ slave=system.membus.master[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -87,6 +95,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -118,6 +127,7 @@ icache_port=system.cpu0.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu0.dcache] type=BaseCache @@ -125,6 +135,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -147,18 +158,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.toL2Bus.slave[3] @@ -169,6 +183,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -191,12 +206,14 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=X86LocalApic clk_domain=system.cpu0.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -207,22 +224,26 @@ pio=system.membus.master[1] [system.cpu0.isa] type=X86ISA +eventq_index=0 [system.cpu0.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=TimingSimpleCPU @@ -234,6 +255,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=Null @@ -255,32 +277,38 @@ workload= [system.cpu1.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system [system.cpu1.isa] type=X86ISA +eventq_index=0 [system.cpu1.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu2] type=DerivO3CPU @@ -311,6 +339,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu2.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -373,6 +403,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -385,12 +416,14 @@ predType=tournament [system.cpu2.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu2.dtb.walker [system.cpu2.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system @@ -398,15 +431,18 @@ system=system type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 +eventq_index=0 [system.cpu2.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu2.fuPool.FUList0.opList [system.cpu2.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -415,16 +451,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 [system.cpu2.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu2.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -433,22 +472,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 [system.cpu2.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu2.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu2.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -457,22 +500,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 [system.cpu2.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu2.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu2.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -481,10 +528,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList4.opList [system.cpu2.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -493,124 +542,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 [system.cpu2.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu2.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu2.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu2.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu2.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu2.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu2.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu2.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu2.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu2.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu2.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu2.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu2.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu2.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu2.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu2.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu2.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu2.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -619,10 +689,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList6.opList [system.cpu2.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -631,16 +703,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 [system.cpu2.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu2.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -649,69 +724,82 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu2.fuPool.FUList8.opList [system.cpu2.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 [system.cpu2.isa] type=X86ISA +eventq_index=0 [system.cpu2.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu2.itb.walker [system.cpu2.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system [system.cpu2.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.e820_table] type=X86E820Table children=entries0 entries1 entries2 entries3 entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 +eventq_index=0 [system.e820_table.entries0] type=X86E820Entry addr=0 +eventq_index=0 range_type=1 size=654336 [system.e820_table.entries1] type=X86E820Entry addr=654336 +eventq_index=0 range_type=2 size=394240 [system.e820_table.entries2] type=X86E820Entry addr=1048576 +eventq_index=0 range_type=1 size=133169152 [system.e820_table.entries3] type=X86E820Entry addr=4294901760 +eventq_index=0 range_type=2 size=65536 [system.intel_mp_pointer] type=X86IntelMPFloatingPointer default_config=0 +eventq_index=0 imcr_present=true spec_rev=4 @@ -719,6 +807,7 @@ spec_rev=4 type=X86IntelMPConfigTable children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32 +eventq_index=0 ext_entries=system.intel_mp_table.ext_entries local_apic=4276092928 oem_id= @@ -731,6 +820,7 @@ spec_rev=4 type=X86IntelMPProcessor bootstrap=true enable=true +eventq_index=0 family=0 feature_flags=0 local_apic_id=0 @@ -742,6 +832,7 @@ stepping=0 type=X86IntelMPIOAPIC address=4273995776 enable=true +eventq_index=0 id=1 version=17 @@ -749,16 +840,19 @@ version=17 type=X86IntelMPBus bus_id=0 bus_type=ISA +eventq_index=0 [system.intel_mp_table.base_entries03] type=X86IntelMPBus bus_id=1 bus_type=PCI +eventq_index=0 [system.intel_mp_table.base_entries04] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=16 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=1 @@ -769,6 +863,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -779,6 +874,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=2 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -789,6 +885,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -799,6 +896,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=1 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -809,6 +907,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -819,6 +918,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=3 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -829,6 +929,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -839,6 +940,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=4 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -849,6 +951,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -859,6 +962,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=5 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -869,6 +973,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -879,6 +984,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=6 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -889,6 +995,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -899,6 +1006,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=7 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -909,6 +1017,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -919,6 +1028,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=8 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -929,6 +1039,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -939,6 +1050,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=9 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -949,6 +1061,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -959,6 +1072,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=10 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -969,6 +1083,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -979,6 +1094,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=11 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -989,6 +1105,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -999,6 +1116,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=12 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -1009,6 +1127,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -1019,6 +1138,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=13 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -1029,6 +1149,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -1039,6 +1160,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=14 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -1048,16 +1170,19 @@ trigger=ConformTrigger [system.intel_mp_table.ext_entries] type=X86IntelMPBusHierarchy bus_id=0 +eventq_index=0 parent_bus=1 subtractive_decode=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -1071,6 +1196,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -1093,6 +1219,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -1102,6 +1229,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -1124,6 +1252,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -1131,6 +1260,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1142,6 +1272,7 @@ slave=system.apicbridge.master system.system_port system.l2c.mem_side system.cpu [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1158,13 +1289,15 @@ pio=system.membus.default [system.pc] type=Pc -children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal +children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge +eventq_index=0 intrctrl=system.intrctrl system=system [system.pc.behind_pci] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854779128 pio_latency=100000 @@ -1183,6 +1316,7 @@ pio=system.iobus.master[12] type=Uart8250 children=terminal clk_domain=system.clk_domain +eventq_index=0 pio_addr=9223372036854776824 pio_latency=100000 platform=system.pc @@ -1192,13 +1326,7 @@ pio=system.iobus.master[13] [system.pc.com_1.terminal] type=Terminal -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.pc.com_1.terminal] -type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1207,6 +1335,7 @@ port=3456 [system.pc.fake_com_2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776568 pio_latency=100000 @@ -1224,6 +1353,7 @@ pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776808 pio_latency=100000 @@ -1241,6 +1371,7 @@ pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776552 pio_latency=100000 @@ -1258,6 +1389,7 @@ pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776818 pio_latency=100000 @@ -1275,6 +1407,7 @@ pio=system.iobus.master[17] [system.pc.i_dont_exist] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854775936 pio_latency=100000 @@ -1293,6 +1426,7 @@ pio=system.iobus.master[11] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.pc @@ -1305,6 +1439,7 @@ type=SouthBridge children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker cmos=system.pc.south_bridge.cmos dma1=system.pc.south_bridge.dma1 +eventq_index=0 io_apic=system.pc.south_bridge.io_apic keyboard=system.pc.south_bridge.keyboard pic1=system.pc.south_bridge.pic1 @@ -1317,6 +1452,7 @@ speaker=system.pc.south_bridge.speaker type=Cmos children=int_pin clk_domain=system.clk_domain +eventq_index=0 int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=100000 @@ -1326,10 +1462,12 @@ pio=system.iobus.master[1] [system.pc.south_bridge.cmos.int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.dma1] type=I8237 clk_domain=system.clk_domain +eventq_index=0 pio_addr=9223372036854775808 pio_latency=100000 system=system @@ -1358,6 +1496,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -1367,8 +1506,40 @@ HeaderType=0 InterruptLine=14 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=128 Revision=0 Status=640 @@ -1380,6 +1551,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=4 @@ -1396,19 +1568,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.pc.south_bridge.ide.disks0.image [system.pc.south_bridge.ide.disks0.image] type=CowDiskImage children=child child=system.pc.south_bridge.ide.disks0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1416,102 +1591,120 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.pc.south_bridge.ide.disks1.image [system.pc.south_bridge.ide.disks1.image] type=CowDiskImage children=child child=system.pc.south_bridge.ide.disks1.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines0.sink source=system.pc.south_bridge.pic1.output [system.pc.south_bridge.int_lines0.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=0 [system.pc.south_bridge.int_lines1] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines1.sink source=system.pc.south_bridge.pic2.output [system.pc.south_bridge.int_lines1.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 +eventq_index=0 number=2 [system.pc.south_bridge.int_lines2] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines2.sink source=system.pc.south_bridge.cmos.int_pin [system.pc.south_bridge.int_lines2.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic2 +eventq_index=0 number=0 [system.pc.south_bridge.int_lines3] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines3.sink source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines3.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 +eventq_index=0 number=0 [system.pc.south_bridge.int_lines4] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines4.sink source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines4.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=2 [system.pc.south_bridge.int_lines5] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines5.sink source=system.pc.south_bridge.keyboard.keyboard_int_pin [system.pc.south_bridge.int_lines5.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=1 [system.pc.south_bridge.int_lines6] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines6.sink source=system.pc.south_bridge.keyboard.mouse_int_pin [system.pc.south_bridge.int_lines6.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=12 [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 clk_domain=system.clk_domain +eventq_index=0 external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 @@ -1526,6 +1719,7 @@ children=keyboard_int_pin mouse_int_pin clk_domain=system.clk_domain command_port=9223372036854775908 data_port=9223372036854775904 +eventq_index=0 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 @@ -1535,14 +1729,17 @@ pio=system.iobus.master[5] [system.pc.south_bridge.keyboard.keyboard_int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.keyboard.mouse_int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pic1] type=I8259 children=output clk_domain=system.clk_domain +eventq_index=0 mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 @@ -1553,11 +1750,13 @@ pio=system.iobus.master[6] [system.pc.south_bridge.pic1.output] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pic2] type=I8259 children=output clk_domain=system.clk_domain +eventq_index=0 mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 @@ -1568,11 +1767,13 @@ pio=system.iobus.master[7] [system.pc.south_bridge.pic2.output] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pit] type=I8254 children=int_pin clk_domain=system.clk_domain +eventq_index=0 int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=100000 @@ -1581,10 +1782,12 @@ pio=system.iobus.master[8] [system.pc.south_bridge.pit.int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.speaker] type=PcSpeaker clk_domain=system.clk_domain +eventq_index=0 i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=100000 @@ -1603,6 +1806,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -1614,19 +1818,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[3] [system.smbios_table] type=X86SMBiosSMBiosTable children=structures +eventq_index=0 major_version=2 minor_version=5 structures=system.smbios_table.structures @@ -1637,6 +1845,7 @@ characteristic_ext_bytes= characteristics= emb_cont_firmware_major=0 emb_cont_firmware_minor=0 +eventq_index=0 major=0 minor=0 release_date=06/08/2008 @@ -1648,6 +1857,7 @@ version= [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1657,5 +1867,6 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index e884e1c2d..2b6efde37 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,159 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.137942 # Number of seconds simulated -sim_ticks 5137941673500 # Number of ticks simulated -final_tick 5137941673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.137456 # Number of seconds simulated +sim_ticks 5137456264000 # Number of ticks simulated +final_tick 5137456264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 248874 # Simulator instruction rate (inst/s) -host_op_rate 494699 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5246911955 # Simulator tick rate (ticks/s) -host_mem_usage 994832 # Number of bytes of host memory used -host_seconds 979.23 # Real time elapsed on the host -sim_insts 243705182 # Number of instructions simulated -sim_ops 484425104 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2466368 # Number of bytes read from this memory +host_inst_rate 176189 # Simulator instruction rate (inst/s) +host_op_rate 350219 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3709429360 # Simulator tick rate (ticks/s) +host_mem_usage 1030148 # Number of bytes of host memory used +host_seconds 1384.97 # Real time elapsed on the host +sim_insts 244016231 # Number of instructions simulated +sim_ops 485043652 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2422400 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 426944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5894144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1789248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 385728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2633280 # Number of bytes read from this memory -system.physmem.bytes_read::total 13744640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 426944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 385728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 959872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9091584 # Number of bytes written to this memory -system.physmem.bytes_written::total 9091584 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38537 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu0.inst 383808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5693376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 137536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1729152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 448384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2947264 # Number of bytes read from this memory +system.physmem.bytes_read::total 13764480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 383808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 137536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 448384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 969728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9086592 # Number of bytes written to this memory +system.physmem.bytes_written::total 9086592 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 37850 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6671 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 92096 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2300 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 27957 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 6027 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 41145 # Number of read requests responded to by this memory -system.physmem.num_reads::total 214760 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 142056 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142056 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 480030 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 5997 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 88959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2149 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 27018 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 34 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 7006 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 46051 # Number of read requests responded to by this memory +system.physmem.num_reads::total 215070 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 141978 # Number of write requests responded to by this memory +system.physmem.num_writes::total 141978 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 471517 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 83096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1147180 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 28650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 348242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 274 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 75074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 512517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2675126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 83096 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 28650 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 75074 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 186820 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1769499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1769499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1769499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 480030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 74708 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1108209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 336577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 87277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 573682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2679240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 74708 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26771 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 87277 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 188756 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1768695 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1768695 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1768695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 471517 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 83096 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1147180 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 28650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 348242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 274 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 75074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 512517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4444625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 100936 # Number of read requests accepted -system.physmem.writeReqs 78380 # Number of write requests accepted -system.physmem.readBursts 100936 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 78380 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6458816 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1088 # Total number of bytes read from write queue -system.physmem.bytesWritten 5015040 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6459904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5016320 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 17 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 74708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1108209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 26771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 336577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 87277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 573682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4447935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 102292 # Number of read requests accepted +system.physmem.writeReqs 78374 # Number of write requests accepted +system.physmem.readBursts 102292 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 78374 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6544384 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2304 # Total number of bytes read from write queue +system.physmem.bytesWritten 5015936 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6546688 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5015936 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 36 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 699 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5898 # Per bank write bursts -system.physmem.perBankRdBursts::1 6403 # Per bank write bursts -system.physmem.perBankRdBursts::2 6411 # Per bank write bursts -system.physmem.perBankRdBursts::3 6523 # Per bank write bursts -system.physmem.perBankRdBursts::4 6306 # Per bank write bursts -system.physmem.perBankRdBursts::5 6840 # Per bank write bursts -system.physmem.perBankRdBursts::6 6199 # Per bank write bursts -system.physmem.perBankRdBursts::7 6896 # Per bank write bursts -system.physmem.perBankRdBursts::8 5528 # Per bank write bursts -system.physmem.perBankRdBursts::9 5898 # Per bank write bursts -system.physmem.perBankRdBursts::10 6128 # Per bank write bursts -system.physmem.perBankRdBursts::11 6570 # Per bank write bursts -system.physmem.perBankRdBursts::12 6317 # Per bank write bursts -system.physmem.perBankRdBursts::13 6334 # Per bank write bursts -system.physmem.perBankRdBursts::14 6542 # Per bank write bursts -system.physmem.perBankRdBursts::15 6126 # Per bank write bursts -system.physmem.perBankWrBursts::0 4721 # Per bank write bursts -system.physmem.perBankWrBursts::1 4902 # Per bank write bursts -system.physmem.perBankWrBursts::2 4923 # Per bank write bursts -system.physmem.perBankWrBursts::3 5159 # Per bank write bursts -system.physmem.perBankWrBursts::4 5192 # Per bank write bursts -system.physmem.perBankWrBursts::5 5457 # Per bank write bursts -system.physmem.perBankWrBursts::6 4843 # Per bank write bursts -system.physmem.perBankWrBursts::7 5797 # Per bank write bursts -system.physmem.perBankWrBursts::8 4085 # Per bank write bursts -system.physmem.perBankWrBursts::9 4367 # Per bank write bursts -system.physmem.perBankWrBursts::10 4807 # Per bank write bursts -system.physmem.perBankWrBursts::11 4903 # Per bank write bursts -system.physmem.perBankWrBursts::12 4884 # Per bank write bursts -system.physmem.perBankWrBursts::13 4699 # Per bank write bursts -system.physmem.perBankWrBursts::14 5116 # Per bank write bursts -system.physmem.perBankWrBursts::15 4505 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 862 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6805 # Per bank write bursts +system.physmem.perBankRdBursts::1 7244 # Per bank write bursts +system.physmem.perBankRdBursts::2 6375 # Per bank write bursts +system.physmem.perBankRdBursts::3 6857 # Per bank write bursts +system.physmem.perBankRdBursts::4 6927 # Per bank write bursts +system.physmem.perBankRdBursts::5 6780 # Per bank write bursts +system.physmem.perBankRdBursts::6 5925 # Per bank write bursts +system.physmem.perBankRdBursts::7 6310 # Per bank write bursts +system.physmem.perBankRdBursts::8 5868 # Per bank write bursts +system.physmem.perBankRdBursts::9 5795 # Per bank write bursts +system.physmem.perBankRdBursts::10 5783 # Per bank write bursts +system.physmem.perBankRdBursts::11 6231 # Per bank write bursts +system.physmem.perBankRdBursts::12 6160 # Per bank write bursts +system.physmem.perBankRdBursts::13 6316 # Per bank write bursts +system.physmem.perBankRdBursts::14 6211 # Per bank write bursts +system.physmem.perBankRdBursts::15 6669 # Per bank write bursts +system.physmem.perBankWrBursts::0 5462 # Per bank write bursts +system.physmem.perBankWrBursts::1 5811 # Per bank write bursts +system.physmem.perBankWrBursts::2 4880 # Per bank write bursts +system.physmem.perBankWrBursts::3 5445 # Per bank write bursts +system.physmem.perBankWrBursts::4 5542 # Per bank write bursts +system.physmem.perBankWrBursts::5 5461 # Per bank write bursts +system.physmem.perBankWrBursts::6 4520 # Per bank write bursts +system.physmem.perBankWrBursts::7 4685 # Per bank write bursts +system.physmem.perBankWrBursts::8 4152 # Per bank write bursts +system.physmem.perBankWrBursts::9 4422 # Per bank write bursts +system.physmem.perBankWrBursts::10 4208 # Per bank write bursts +system.physmem.perBankWrBursts::11 4507 # Per bank write bursts +system.physmem.perBankWrBursts::12 4889 # Per bank write bursts +system.physmem.perBankWrBursts::13 4664 # Per bank write bursts +system.physmem.perBankWrBursts::14 4834 # Per bank write bursts +system.physmem.perBankWrBursts::15 4892 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 5136941479000 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 5136272146500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 100936 # Read request sizes (log2) +system.physmem.readPktSize::6 102292 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 78380 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 75816 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3848 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 976 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 667 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 539 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 430 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 78374 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 79930 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8799 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 828 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 776 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -163,226 +163,227 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3499 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 35607 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 322.217991 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 144.094116 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1121.662575 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 16547 46.47% 46.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 5535 15.54% 62.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3551 9.97% 71.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2213 6.22% 78.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1334 3.75% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1101 3.09% 85.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 807 2.27% 87.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 584 1.64% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 515 1.45% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 517 1.45% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 309 0.87% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 309 0.87% 93.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 205 0.58% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 200 0.56% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 177 0.50% 95.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 272 0.76% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 139 0.39% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 84 0.24% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 95 0.27% 96.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 94 0.26% 97.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 81 0.23% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 178 0.50% 97.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 83 0.23% 98.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 58 0.16% 98.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 45 0.13% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 38 0.11% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 29 0.08% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 19 0.05% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 15 0.04% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 14 0.04% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 11 0.03% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 10 0.03% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 8 0.02% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 10 0.03% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 8 0.02% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 6 0.02% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 6 0.02% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 5 0.01% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 6 0.02% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 3 0.01% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 5 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 4 0.01% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 4 0.01% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 6 0.02% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 5 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 2 0.01% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 8 0.02% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 5 0.01% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.01% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 3 0.01% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 8 0.02% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 3 0.01% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 4 0.01% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 5 0.01% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 6 0.02% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 1 0.00% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 10 0.03% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 3 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 6 0.02% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 3 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 4 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 4 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 4 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 2 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 2 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 3 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 3 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 2 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 2 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 4 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 2 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 3 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 2 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 3 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 3 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 20 0.06% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 2 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 2 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 4 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 2 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 6 0.02% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 2 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 2 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 2 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 2 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 3 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 2 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 2 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10435 2 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10563 2 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11267 2 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11395 3 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 2 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12611 2 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12867 2 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13891 3 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 2 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 2 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 3 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 12 0.03% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 3 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 7 0.02% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 5 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 4 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 2 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 6 0.02% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 10 0.03% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 5 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 3 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 2 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 4 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 3 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 5 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 9 0.03% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 8 0.02% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 29 0.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 35607 # Bytes accessed per row activation -system.physmem.totQLat 2741683498 # Total ticks spent queuing -system.physmem.totMemAccLat 4643457248 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 504595000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1397178750 # Total ticks spent accessing banks -system.physmem.avgQLat 27167.17 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13844.56 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::31 11 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 37207 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 310.623700 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.064630 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1005.971949 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 16908 45.44% 45.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 5765 15.49% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3845 10.33% 71.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2398 6.45% 77.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1477 3.97% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1206 3.24% 84.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 882 2.37% 87.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 634 1.70% 89.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 564 1.52% 90.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 479 1.29% 91.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 331 0.89% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 285 0.77% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 209 0.56% 94.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 204 0.55% 94.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 197 0.53% 95.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 303 0.81% 95.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 153 0.41% 96.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 117 0.31% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 75 0.20% 96.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 61 0.16% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 106 0.28% 97.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 199 0.53% 97.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 97 0.26% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 87 0.23% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 45 0.12% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 43 0.12% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 26 0.07% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 28 0.08% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 16 0.04% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 12 0.03% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 10 0.03% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 10 0.03% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 17 0.05% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 7 0.02% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 10 0.03% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 3 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 3 0.01% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 7 0.02% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 3 0.01% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 7 0.02% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 9 0.02% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 4 0.01% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 6 0.02% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 6 0.02% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 2 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 2 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 13 0.03% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 4 0.01% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.01% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 3 0.01% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 4 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 4 0.01% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 2 0.01% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 3 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 7 0.02% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 2 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 3 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 2 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 24 0.06% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 2 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 10 0.03% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 4 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 25 0.07% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 2 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 3 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 2 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 2 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 23 0.06% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 2 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 5 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 6 0.02% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 2 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 2 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 3 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 4 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 2 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8643 2 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9411 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 2 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11139 2 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 2 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 2 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 2 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 2 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 2 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 2 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 4 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 2 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 3 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 2 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 3 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 5 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 8 0.02% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 1 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 2 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 2 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 3 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 11 0.03% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 14 0.04% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 22 0.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37207 # Bytes accessed per row activation +system.physmem.totQLat 2596442750 # Total ticks spent queuing +system.physmem.totMemAccLat 4566061500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 511280000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1458338750 # Total ticks spent accessing banks +system.physmem.avgQLat 25391.59 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14261.64 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46011.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44653.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.26 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.27 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.98 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage @@ -390,322 +391,318 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.11 # Average write queue length when enqueuing -system.physmem.readRowHits 85240 # Number of row buffer hits during reads -system.physmem.writeRowHits 58432 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.46 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.55 # Row buffer hit rate for writes -system.physmem.avgGap 28647423.98 # Average gap between requests -system.physmem.pageHitRate 80.13 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.12 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 6427951 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 423177 # Transaction distribution -system.membus.trans_dist::ReadResp 423176 # Transaction distribution -system.membus.trans_dist::WriteReq 6474 # Transaction distribution -system.membus.trans_dist::WriteResp 6474 # Transaction distribution -system.membus.trans_dist::Writeback 78380 # Transaction distribution -system.membus.trans_dist::UpgradeReq 714 # Transaction distribution -system.membus.trans_dist::UpgradeResp 714 # Transaction distribution -system.membus.trans_dist::ReadExReq 80216 # Transaction distribution -system.membus.trans_dist::ReadExResp 80216 # Transaction distribution -system.membus.trans_dist::MessageReq 892 # Transaction distribution -system.membus.trans_dist::MessageResp 892 # Transaction distribution -system.membus.trans_dist::BadAddressError 1 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1784 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 1784 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 310648 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497624 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 207711 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1015985 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 78748 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 78748 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1096517 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 3568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 159467 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995245 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8228608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 9383320 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3247616 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 3247616 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 12634504 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 32719620 # Total data (bytes) -system.membus.snoop_data_through_bus 306816 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 163512000 # Layer occupancy (ticks) +system.physmem.readRowHits 86197 # Number of row buffer hits during reads +system.physmem.writeRowHits 57226 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.30 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.02 # Row buffer hit rate for writes +system.physmem.avgGap 28429655.53 # Average gap between requests +system.physmem.pageHitRate 79.40 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.13 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6440814 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 424797 # Transaction distribution +system.membus.trans_dist::ReadResp 424797 # Transaction distribution +system.membus.trans_dist::WriteReq 7056 # Transaction distribution +system.membus.trans_dist::WriteResp 7056 # Transaction distribution +system.membus.trans_dist::Writeback 78374 # Transaction distribution +system.membus.trans_dist::UpgradeReq 877 # Transaction distribution +system.membus.trans_dist::UpgradeResp 877 # Transaction distribution +system.membus.trans_dist::ReadExReq 80570 # Transaction distribution +system.membus.trans_dist::ReadExResp 80570 # Transaction distribution +system.membus.trans_dist::MessageReq 957 # Transaction distribution +system.membus.trans_dist::MessageResp 957 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1914 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 1914 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312158 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497710 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 221000 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1030868 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 68894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 68894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1101676 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3828 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 3828 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 160435 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995417 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8741760 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 9897612 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2820864 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2820864 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 12722304 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 32756791 # Total data (bytes) +system.membus.snoop_data_through_bus 332608 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 164980499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 315210000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 315323500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1784000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1914000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 830204748 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 859913497 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 892000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 957000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1595294481 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1658568572 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 252511249 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 223775499 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 103855 # number of replacements -system.l2c.tags.tagsinuse 64822.347448 # Cycle average of tags in use -system.l2c.tags.total_refs 3646219 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 167877 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.719586 # Average number of references to valid blocks. +system.l2c.tags.replacements 103968 # number of replacements +system.l2c.tags.tagsinuse 64819.095791 # Cycle average of tags in use +system.l2c.tags.total_refs 3669692 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168243 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.811855 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51292.264352 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121895 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1278.615227 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4499.945934 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 292.458405 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1505.357985 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.212632 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003182 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1370.507166 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4576.860668 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.782658 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51211.809516 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121912 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1304.363790 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4492.907273 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 251.742289 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1518.622796 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.780510 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.958868 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1352.233300 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4674.555536 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.781430 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.019510 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.068664 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004463 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.022970 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000095 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.020912 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.069837 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989111 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 19693 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10326 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 346717 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 513928 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 10907 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5932 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 155624 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 223811 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 47020 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 9087 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 331652 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 566093 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2240790 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.019903 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.068556 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003841 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.023172 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000180 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.020633 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.071328 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989061 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 21716 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 11486 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 326601 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 505560 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 10498 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5651 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 148959 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 223967 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 55385 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 11312 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 366888 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 576803 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2264826 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1542501 # number of Writeback hits -system.l2c.Writeback_hits::total 1542501 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 139 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 58 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 57 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 254 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 70841 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 36082 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 59675 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 166598 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 19693 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 10328 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 346717 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 584769 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 10907 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5932 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 155624 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 259893 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 47020 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 9087 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 331652 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 625768 # number of demand (read+write) hits -system.l2c.demand_hits::total 2407390 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 19693 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 10328 # number of overall hits -system.l2c.overall_hits::cpu0.inst 346717 # number of overall hits -system.l2c.overall_hits::cpu0.data 584769 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 10907 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5932 # number of overall hits -system.l2c.overall_hits::cpu1.inst 155624 # number of overall hits -system.l2c.overall_hits::cpu1.data 259893 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 47020 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 9087 # number of overall hits -system.l2c.overall_hits::cpu2.inst 331652 # number of overall hits -system.l2c.overall_hits::cpu2.data 625768 # number of overall hits -system.l2c.overall_hits::total 2407390 # number of overall hits +system.l2c.Writeback_hits::writebacks 1544272 # number of Writeback hits +system.l2c.Writeback_hits::total 1544272 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 123 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 38 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 95 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 256 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 65648 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 35064 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 65209 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 165921 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 21716 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 11488 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 326601 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 571208 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 10498 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5651 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 148959 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 259031 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 55385 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 11312 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 366888 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 642012 # number of demand (read+write) hits +system.l2c.demand_hits::total 2430749 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 21716 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 11488 # number of overall hits +system.l2c.overall_hits::cpu0.inst 326601 # number of overall hits +system.l2c.overall_hits::cpu0.data 571208 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 10498 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5651 # number of overall hits +system.l2c.overall_hits::cpu1.inst 148959 # number of overall hits +system.l2c.overall_hits::cpu1.data 259031 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 55385 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 11312 # number of overall hits +system.l2c.overall_hits::cpu2.inst 366888 # number of overall hits +system.l2c.overall_hits::cpu2.data 642012 # number of overall hits +system.l2c.overall_hits::total 2430749 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6671 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 16268 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2301 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4539 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 22 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 6029 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 11901 # number of ReadReq misses -system.l2c.ReadReq_misses::total 47736 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 761 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 281 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 269 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1311 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 76320 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 23649 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 29451 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 129420 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu0.inst 5997 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 15878 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2150 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4005 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 34 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 7008 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 12968 # number of ReadReq misses +system.l2c.ReadReq_misses::total 48046 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 707 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 185 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 493 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1385 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 73415 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 23238 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 33467 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 130120 # number of ReadExReq misses system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6671 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 92588 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2301 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 28188 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 22 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 6029 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 41352 # number of demand (read+write) misses -system.l2c.demand_misses::total 177156 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 5997 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 89293 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2150 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 27243 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 34 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 7008 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 46435 # number of demand (read+write) misses +system.l2c.demand_misses::total 178166 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6671 # number of overall misses -system.l2c.overall_misses::cpu0.data 92588 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2301 # number of overall misses -system.l2c.overall_misses::cpu1.data 28188 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 22 # number of overall misses -system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu2.inst 6029 # number of overall misses -system.l2c.overall_misses::cpu2.data 41352 # number of overall misses -system.l2c.overall_misses::total 177156 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.inst 178484750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 352246744 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2002250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.itb.walker 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 488673998 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 943243246 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1964725488 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 3587383 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 3136875 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 6724258 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1676320610 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 2179701143 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 3856021753 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.inst 178484750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2028567354 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 2002250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.itb.walker 74500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 488673998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 3122944389 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 5820747241 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.inst 178484750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2028567354 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 2002250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.itb.walker 74500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 488673998 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 3122944389 # number of overall miss cycles -system.l2c.overall_miss_latency::total 5820747241 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 19693 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 10330 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 353388 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 530196 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 10907 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 5932 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 157925 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 228350 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 47042 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 9088 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 337681 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 577994 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2288526 # number of ReadReq accesses(hits+misses) +system.l2c.overall_misses::cpu0.inst 5997 # number of overall misses +system.l2c.overall_misses::cpu0.data 89293 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2150 # number of overall misses +system.l2c.overall_misses::cpu1.data 27243 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 34 # number of overall misses +system.l2c.overall_misses::cpu2.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu2.inst 7008 # number of overall misses +system.l2c.overall_misses::cpu2.data 46435 # number of overall misses +system.l2c.overall_misses::total 178166 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.inst 161561250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 314335492 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2727499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.itb.walker 170750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 583607489 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 1035968985 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2098371465 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 3143902 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 6170749 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 9314651 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1653854893 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 2482673598 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 4136528491 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 161561250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1968190385 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 2727499 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.itb.walker 170750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 583607489 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 3518642583 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 6234899956 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 161561250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1968190385 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 2727499 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.itb.walker 170750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 583607489 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 3518642583 # number of overall miss cycles +system.l2c.overall_miss_latency::total 6234899956 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 21716 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 11490 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 332598 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 521438 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 10498 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 5651 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 151109 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 227972 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 55419 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 11314 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 373896 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 589771 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2312872 # number of ReadReq accesses(hits+misses) system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses) system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1542501 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1542501 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 900 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 339 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 326 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1565 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 147161 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 59731 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 89126 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296018 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 19693 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 10332 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 353388 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 677357 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 10907 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 5932 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 157925 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 288081 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 47042 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 9088 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 337681 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 667120 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2584546 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 19693 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 10332 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 353388 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 677357 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 10907 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5932 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 157925 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 288081 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 47042 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 9088 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 337681 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 667120 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2584546 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000387 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.018877 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.030683 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.014570 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.019877 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000468 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000110 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.017854 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.020590 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.020859 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.845556 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.828909 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.825153 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.837700 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.518616 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.395925 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.330442 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.437203 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000387 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018877 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.136690 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.014570 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.097847 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000468 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.itb.walker 0.000110 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.017854 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.061986 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.068544 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000387 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018877 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.136690 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.014570 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.097847 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000468 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.itb.walker 0.000110 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.017854 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.061986 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.068544 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77568.339852 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 77604.482045 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 91011.363636 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 74500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 81053.905789 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 79257.478027 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 41158.150830 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12766.487544 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11661.245353 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 5129.106026 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70883.361241 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74011.108044 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 29794.635705 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 77568.339852 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 71965.636228 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 91011.363636 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.itb.walker 74500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 81053.905789 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 75520.999927 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 32856.619256 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 77568.339852 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 71965.636228 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 91011.363636 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.itb.walker 74500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 81053.905789 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 75520.999927 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 32856.619256 # average overall miss latency +system.l2c.Writeback_accesses::writebacks 1544272 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1544272 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 830 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 223 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 588 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1641 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 139063 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 58302 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 98676 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 296041 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 21716 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 11492 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 332598 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 660501 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 10498 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5651 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 151109 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 286274 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 55419 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 11314 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 373896 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 688447 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2608915 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 21716 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 11492 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 332598 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 660501 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 10498 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5651 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 151109 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 286274 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 55419 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 11314 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 373896 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 688447 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2608915 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000348 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.018031 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.030450 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.014228 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.017568 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000614 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000177 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.018743 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.021988 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.020773 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.851807 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.829596 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.838435 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.843998 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.527926 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.398580 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.339160 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.439534 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000348 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018031 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.135190 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.014228 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.095164 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000614 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.itb.walker 0.000177 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.018743 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.067449 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.068291 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000348 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018031 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.135190 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.014228 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.095164 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000614 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.itb.walker 0.000177 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.018743 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.067449 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.068291 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75144.767442 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 78485.765793 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 80220.558824 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 85375 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 83277.324344 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 79886.565777 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 43674.217729 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16994.064865 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12516.732252 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 6725.379783 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71170.276831 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74182.735172 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 31790.105218 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 75144.767442 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 72245.728628 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 80220.558824 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.itb.walker 85375 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 83277.324344 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 75775.655928 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 34994.892157 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 75144.767442 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 72245.728628 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 80220.558824 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.itb.walker 85375 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 83277.324344 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 75775.655928 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 34994.892157 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -714,131 +711,131 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 95389 # number of writebacks -system.l2c.writebacks::total 95389 # number of writebacks +system.l2c.writebacks::writebacks 95311 # number of writebacks +system.l2c.writebacks::total 95311 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu2.inst 2 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu2.inst 2 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu2.inst 2 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu1.inst 2301 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4539 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 22 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 6027 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 11901 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 24791 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 281 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 269 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 550 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 23649 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 29451 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 53100 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2301 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 28188 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 22 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 6027 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 41352 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 77891 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2301 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 28188 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 22 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 6027 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 41352 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 77891 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 149580250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 295478756 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 1731250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 413107752 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 794213750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1654174258 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3410269 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 2847765 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 6258034 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1378867890 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1809513813 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 3188381703 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 149580250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1674346646 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 1731250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 413107752 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 2603727563 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 4842555961 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 149580250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1674346646 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 1731250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 413107752 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 2603727563 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 4842555961 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28165267500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30426261500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 58591529000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 495358500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 671313500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1166672000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28660626000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31097575000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 59758201000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014570 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.019877 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000468 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000110 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.017848 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.020590 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.010833 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.828909 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.825153 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.351438 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.395925 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.330442 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.179381 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014570 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.097847 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000468 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000110 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.017848 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.061986 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.030137 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014570 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.097847 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000468 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000110 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.017848 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.061986 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.030137 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65006.627553 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65097.765147 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 78693.181818 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 68542.849179 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 66735.043274 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 66724.789561 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12136.188612 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10586.486989 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 11378.243636 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58305.547380 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61441.506672 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60044.853164 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65006.627553 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59399.270824 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 78693.181818 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 68542.849179 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62964.972988 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 62170.930672 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65006.627553 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59399.270824 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 78693.181818 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 68542.849179 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62964.972988 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 62170.930672 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu1.inst 2150 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4005 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 34 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 7006 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 12968 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 26165 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 185 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 493 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 678 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 23238 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 33467 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 56705 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2150 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 27243 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 34 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 7006 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 46435 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 82870 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2150 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 27243 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 34 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 7006 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 46435 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 82870 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 134244250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 264246008 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2308001 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 145750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 495740261 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 873454007 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1770138277 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 2450173 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 5190488 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 7640661 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1355864107 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2052275856 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 3408139963 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 134244250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1620110115 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2308001 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 145750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 495740261 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2925729863 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5178278240 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 134244250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1620110115 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2308001 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 145750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 495740261 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2925729863 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5178278240 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28143642000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30477969500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 58621611500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 483707000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 766316000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1250023000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28627349000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31244285500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 59871634500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014228 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017568 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000614 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000177 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.018738 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.021988 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.011313 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.829596 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.838435 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.413163 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.398580 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.339160 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.191544 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014228 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.095164 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000614 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000177 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.018738 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.067449 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.031764 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014228 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.095164 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000614 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000177 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.018738 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.067449 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.031764 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62439.186047 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65979.028215 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 67882.382353 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 72875 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 70759.386383 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 67354.565623 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 67652.905676 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 13244.178378 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10528.373225 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 11269.411504 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58346.850288 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61322.372964 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60102.988502 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62439.186047 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59468.858606 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 67882.382353 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 72875 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 70759.386383 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63006.996081 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62486.765295 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62439.186047 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59468.858606 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 67882.382353 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 72875 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 70759.386383 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63006.996081 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62486.765295 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -849,39 +846,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 47575 # number of replacements -system.iocache.tags.tagsinuse 0.094274 # Cycle average of tags in use +system.iocache.tags.replacements 47574 # number of replacements +system.iocache.tags.tagsinuse 0.092731 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000200819009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.094274 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005892 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005892 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses -system.iocache.ReadReq_misses::total 910 # number of ReadReq misses +system.iocache.tags.warmup_cycle 5000213887009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.092731 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005796 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005796 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses +system.iocache.ReadReq_misses::total 909 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses -system.iocache.demand_misses::total 47630 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses -system.iocache.overall_misses::total 47630 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 129801048 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 129801048 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6845673540 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 6845673540 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 6975474588 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 6975474588 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 6975474588 # number of overall miss cycles -system.iocache.overall_miss_latency::total 6975474588 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47629 # number of demand (read+write) misses +system.iocache.demand_misses::total 47629 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47629 # number of overall misses +system.iocache.overall_misses::total 47629 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 135882017 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 135882017 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 5955673280 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5955673280 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 6091555297 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 6091555297 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 6091555297 # number of overall miss cycles +system.iocache.overall_miss_latency::total 6091555297 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47629 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47629 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -890,56 +887,56 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 142638.514286 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 142638.514286 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 146525.546661 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 146525.546661 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 146451.282553 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 146451.282553 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 146451.282553 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 146451.282553 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 105453 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 149485.167217 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 149485.167217 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 127475.883562 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 127475.883562 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 127895.930987 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 127895.930987 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 127895.930987 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 127895.930987 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 91729 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 6453 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5124 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 16.341702 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 17.901835 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 724 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 724 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 27280 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 27280 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 28004 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 28004 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 28004 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 28004 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92126548 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 92126548 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 5426189542 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5426189542 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 5518316090 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5518316090 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 5518316090 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5518316090 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.795604 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.795604 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.583904 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.583904 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.587949 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.587949 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.587949 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.587949 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127246.613260 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 127246.613260 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 198907.241276 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 198907.241276 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 197054.566848 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 197054.566848 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 197054.566848 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 197054.566848 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 754 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 754 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 24064 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 24064 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 24818 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 24818 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 24818 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 24818 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96648017 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 96648017 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4703544282 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4703544282 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4800192299 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4800192299 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4800192299 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4800192299 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.829483 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.829483 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.515068 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.515068 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.521069 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.521069 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.521069 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.521069 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 128180.393899 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 128180.393899 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 195459.785655 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 195459.785655 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 193415.758683 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 193415.758683 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 193415.758683 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 193415.758683 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -953,459 +950,458 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 52188015 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1787129 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1786595 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 6474 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 6474 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 905502 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 665 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 665 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 176137 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 148862 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 991248 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3625702 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 34347 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 125379 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4776676 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31718784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120252184 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 120160 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 463592 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 152554720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 268001344 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 137632 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5049278590 # Layer occupancy (ticks) +system.toL2Bus.throughput 52370833 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1836862 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1836332 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 7056 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 7056 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 922959 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 811 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 811 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 181042 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 156978 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1050040 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3684115 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 38115 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 140219 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4912489 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 33600320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 122621708 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 135720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 527336 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 156885084 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 268925359 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 127504 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5157428290 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 882000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1008000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2232669307 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2365130940 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4714355905 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4803653283 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 19343965 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 21171206 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 67521559 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 74417261 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1276093 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 150466 # Transaction distribution -system.iobus.trans_dist::ReadResp 150466 # Transaction distribution -system.iobus.trans_dist::WriteReq 32862 # Transaction distribution -system.iobus.trans_dist::WriteResp 32862 # Transaction distribution -system.iobus.trans_dist::MessageReq 892 # Transaction distribution -system.iobus.trans_dist::MessageResp 892 # Transaction distribution +system.iobus.throughput 1276721 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 150736 # Transaction distribution +system.iobus.trans_dist::ReadResp 150736 # Transaction distribution +system.iobus.trans_dist::WriteReq 30161 # Transaction distribution +system.iobus.trans_dist::WriteResp 30161 # Transaction distribution +system.iobus.trans_dist::MessageReq 957 # Transaction distribution +system.iobus.trans_dist::MessageResp 957 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4556 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5986 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1160 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 46 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 500 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287076 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 580 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 14980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 15082 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 310648 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 56008 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 56008 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1784 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1784 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 368440 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 312158 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 49636 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 49636 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 363708 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2572 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3380 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 17 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 23 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143595 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1000 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143538 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1160 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7490 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7541 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4128 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 159467 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1782176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1782176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1945211 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6556491 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2113460 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 160435 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1576592 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1576592 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3828 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3828 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1740855 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 6559098 # Total data (bytes) +system.iobus.reqLayer0.occupancy 2255722 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 3772000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4948000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 39000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 143596000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 143539000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 394000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 458000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11170000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11248000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 248070339 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 218954798 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 305066000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 306061000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 32957751 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 29747501 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 892000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 957000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.numCycles 1184263733 # number of cpu cycles simulated +system.cpu0.numCycles 1152461068 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72124506 # Number of instructions committed -system.cpu0.committedOps 146682326 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 134713165 # Number of integer alu accesses +system.cpu0.committedInsts 71542662 # Number of instructions committed +system.cpu0.committedOps 145644721 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 133686522 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 981373 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14229217 # number of instructions that are conditional controls -system.cpu0.num_int_insts 134713165 # number of integer instructions +system.cpu0.num_func_calls 963574 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14130614 # number of instructions that are conditional controls +system.cpu0.num_int_insts 133686522 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 247622256 # number of times the integer registers were read -system.cpu0.num_int_register_writes 115606613 # number of times the integer registers were written +system.cpu0.num_int_register_reads 245609809 # number of times the integer registers were read +system.cpu0.num_int_register_writes 114802156 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 83816060 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55907358 # number of times the CC registers were written -system.cpu0.num_mem_refs 14049102 # number of memory refs -system.cpu0.num_load_insts 10253492 # Number of load instructions -system.cpu0.num_store_insts 3795610 # Number of store instructions -system.cpu0.num_idle_cycles 1123870108.492543 # Number of idle cycles -system.cpu0.num_busy_cycles 60393624.507457 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050997 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949003 # Percentage of idle cycles +system.cpu0.num_cc_register_reads 83145706 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55494396 # number of times the CC registers were written +system.cpu0.num_mem_refs 13834339 # number of memory refs +system.cpu0.num_load_insts 10142209 # Number of load instructions +system.cpu0.num_store_insts 3692130 # Number of store instructions +system.cpu0.num_idle_cycles 1095316733.110107 # Number of idle cycles +system.cpu0.num_busy_cycles 57144334.889893 # Number of busy cycles +system.cpu0.not_idle_fraction 0.049585 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.950415 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 848510 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.789516 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 129618382 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 849022 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 152.667872 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 147463418500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 302.993641 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 130.368033 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 77.427843 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.591784 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.254625 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.151226 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997636 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 87771297 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 39145197 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2701888 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 129618382 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 87771297 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 39145197 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2701888 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 129618382 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 87771297 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 39145197 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2701888 # number of overall hits -system.cpu0.icache.overall_hits::total 129618382 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 353389 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 157925 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 356099 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 867413 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 353389 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 157925 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 356099 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 867413 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 353389 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 157925 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 356099 # number of overall misses -system.cpu0.icache.overall_misses::total 867413 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2216316250 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5093590204 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7309906454 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2216316250 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5093590204 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7309906454 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2216316250 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5093590204 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7309906454 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 88124686 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 39303122 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3057987 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 130485795 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 88124686 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 39303122 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3057987 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 130485795 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 88124686 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 39303122 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3057987 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 130485795 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.004010 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004018 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.116449 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006648 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.004010 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004018 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.116449 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006648 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.004010 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004018 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.116449 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006648 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14033.979737 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14303.859893 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8427.250288 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14033.979737 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14303.859893 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8427.250288 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14033.979737 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14303.859893 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8427.250288 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4049 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 857108 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.816977 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 128607019 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 857620 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 149.958046 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 147466681500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 303.791229 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 134.865519 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 72.160229 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.593342 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.263409 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.140938 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997689 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 87032678 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 38704601 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2869740 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 128607019 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 87032678 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 38704601 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2869740 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 128607019 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 87032678 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 38704601 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2869740 # number of overall hits +system.cpu0.icache.overall_hits::total 128607019 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 332599 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 151109 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 394689 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 878397 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 332599 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 151109 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 394689 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 878397 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 332599 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 151109 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 394689 # number of overall misses +system.cpu0.icache.overall_misses::total 878397 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2111983250 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5690259841 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7802243091 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2111983250 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 5690259841 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7802243091 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2111983250 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 5690259841 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7802243091 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 87365277 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 38855710 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 3264429 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 129485416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 87365277 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 38855710 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 3264429 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 129485416 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 87365277 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 38855710 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3264429 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 129485416 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003807 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.003889 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.120906 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.006784 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003807 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.003889 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.120906 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.006784 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003807 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.003889 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.120906 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.006784 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13976.555003 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14417.072280 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8882.365367 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13976.555003 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14417.072280 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8882.365367 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13976.555003 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14417.072280 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8882.365367 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6122 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 236 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 230 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.156780 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.617391 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 18382 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 18382 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 18382 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 18382 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 18382 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 18382 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 157925 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 337717 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 495642 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 157925 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 337717 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 495642 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 157925 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 337717 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 495642 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1899637750 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4221033432 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6120671182 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1899637750 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4221033432 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6120671182 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1899637750 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4221033432 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6120671182 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004018 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110438 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003798 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004018 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110438 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.003798 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004018 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110438 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.003798 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12028.733576 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12498.729504 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12348.976039 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12028.733576 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12498.729504 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12348.976039 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12028.733576 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12498.729504 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12348.976039 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 20763 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 20763 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 20763 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 20763 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 20763 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 20763 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 151109 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 373926 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 525035 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 151109 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 373926 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 525035 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 151109 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 373926 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 525035 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1808966750 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4711215798 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6520182548 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1808966750 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4711215798 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6520182548 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1808966750 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4711215798 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6520182548 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.003889 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.114546 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004055 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.003889 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.114546 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004055 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.003889 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.114546 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004055 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11971.270738 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12599.326599 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12418.567425 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11971.270738 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12599.326599 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12418.567425 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11971.270738 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12599.326599 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12418.567425 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1632030 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997838 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19577218 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1632542 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 11.991862 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1634697 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999455 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19613816 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1635209 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 11.994684 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 205.523243 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 299.707974 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.766620 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.401413 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.585367 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013216 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5112635 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2556554 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 3831407 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11500596 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3643791 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1689050 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2742153 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8074994 # number of WriteReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8756426 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 4245604 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6573560 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19575590 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8756426 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 4245604 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6573560 # number of overall hits -system.cpu0.dcache.overall_hits::total 19575590 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 530196 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 228350 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 940486 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1699032 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 148061 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 60070 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 106578 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 314709 # number of WriteReq misses -system.cpu0.dcache.demand_misses::cpu0.data 678257 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 288420 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1047064 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2013741 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 678257 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 288420 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1047064 # number of overall misses -system.cpu0.dcache.overall_misses::total 2013741 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3284093256 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15033857981 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 18317951237 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2239487659 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3281341546 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5520829205 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 5523580915 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 18315199527 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 23838780442 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 5523580915 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 18315199527 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 23838780442 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5642831 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2784904 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4771893 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13199628 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3791852 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1749120 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2848731 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8389703 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 9434683 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4534024 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7620624 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21589331 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9434683 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4534024 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7620624 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21589331 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.093959 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.081996 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.197089 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.128718 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.039047 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.034343 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.037412 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.037511 # miss rate for WriteReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.071890 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.063612 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.137399 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.093275 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.071890 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.063612 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.137399 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.093275 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14381.840403 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15985.201248 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10781.404492 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37281.299467 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30788.169660 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17542.647986 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19151.171607 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17491.958015 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 11838.056851 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19151.171607 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17491.958015 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 11838.056851 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 171453 # number of cycles access was blocked +system.cpu0.dcache.tags.occ_blocks::cpu0.data 200.851253 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 304.204078 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.944124 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.392288 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.594149 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013563 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5007486 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 2456211 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4066814 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11530511 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3548930 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1627224 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2905330 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 8081484 # number of WriteReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8556416 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 4083435 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6972144 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 19611995 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8556416 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 4083435 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6972144 # number of overall hits +system.cpu0.dcache.overall_hits::total 19611995 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 521438 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 227972 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 965445 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1714855 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 139893 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 58525 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 116582 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 315000 # number of WriteReq misses +system.cpu0.dcache.demand_misses::cpu0.data 661331 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 286497 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1082027 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2029855 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 661331 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 286497 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1082027 # number of overall misses +system.cpu0.dcache.overall_misses::total 2029855 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3246346508 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15541427611 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 18787774119 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2199408780 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3682017546 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5881426326 # number of WriteReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 5445755288 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 19223445157 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 24669200445 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 5445755288 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 19223445157 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 24669200445 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5528924 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 2684183 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 5032259 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13245366 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3688823 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1685749 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 3021912 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 8396484 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 9217747 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 4369932 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 8054171 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21641850 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 9217747 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 4369932 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 8054171 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 21641850 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.094311 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.084932 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.191851 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.129468 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.037923 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.034718 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.038579 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.037516 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.071745 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.065561 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.134344 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.093793 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.071745 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.065561 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.134344 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.093793 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14240.110663 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16097.683049 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10955.896632 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37580.671166 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31583.070680 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18671.194686 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19008.070898 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17766.141840 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 12153.183575 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19008.070898 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17766.141840 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12153.183575 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 177963 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 11788 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 11847 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.544706 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.021778 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1542501 # number of writebacks -system.cpu0.dcache.writebacks::total 1542501 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 362466 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 362466 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 17153 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 17153 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 379619 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 379619 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 379619 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 379619 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 228350 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 578020 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 806370 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 60070 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 89425 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 149495 # number of WriteReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 288420 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 667445 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 955865 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 288420 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 667445 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 955865 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2826173744 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8314744809 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11140918553 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2108252341 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2905747700 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5014000041 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4934426085 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11220492509 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16154918594 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4934426085 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11220492509 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16154918594 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30636255000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33190282000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63826537000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 532271000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 712236000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1244507000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31168526000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33902518000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65071044000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.081996 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.121130 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.061090 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034343 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031391 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017819 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.063612 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.087584 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.044275 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.063612 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087584 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.044275 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12376.499864 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14384.873895 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13816.137199 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35096.592992 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32493.684093 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33539.583538 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17108.474048 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16811.111790 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16900.837037 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17108.474048 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16811.111790 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16900.837037 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1544272 # number of writebacks +system.cpu0.dcache.writebacks::total 1544272 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 375629 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 375629 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 17363 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 17363 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 392992 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 392992 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 392992 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 392992 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 227972 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 589816 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 817788 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 58525 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 99219 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 157744 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 286497 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 689035 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 975532 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 286497 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 689035 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 975532 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2789367492 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8524003053 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11313370545 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2071430220 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3281431451 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5352861671 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4860797712 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11805434504 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16666232216 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4860797712 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11805434504 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16666232216 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30612926500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33246502500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63859429000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 519657500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 815190500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1334848000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31132584000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34061693000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65194277000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.084932 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.117207 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.061741 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034718 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032833 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018787 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065561 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.085550 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.045076 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065561 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.085550 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.045076 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12235.570561 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14451.969857 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13834.111707 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35393.937975 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33072.611607 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33933.852768 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16966.312778 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17133.287139 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17084.249636 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16966.312778 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17133.287139 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17084.249636 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1416,306 +1412,306 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606010326 # number of cpu cycles simulated +system.cpu1.numCycles 2606011326 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35502902 # Number of instructions committed -system.cpu1.committedOps 69019443 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64128875 # Number of integer alu accesses +system.cpu1.committedInsts 35164948 # Number of instructions committed +system.cpu1.committedOps 68413270 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 63529188 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 466888 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6511590 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64128875 # number of integer instructions +system.cpu1.num_func_calls 457891 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6471423 # number of instructions that are conditional controls +system.cpu1.num_int_insts 63529188 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 118555351 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55341107 # number of times the integer registers were written +system.cpu1.num_int_register_reads 117257194 # number of times the integer registers were read +system.cpu1.num_int_register_writes 54850904 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36337345 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27074895 # number of times the CC registers were written -system.cpu1.num_mem_refs 4724906 # number of memory refs -system.cpu1.num_load_insts 2973846 # Number of load instructions -system.cpu1.num_store_insts 1751060 # Number of store instructions -system.cpu1.num_idle_cycles 2477242501.972853 # Number of idle cycles -system.cpu1.num_busy_cycles 128767824.027147 # Number of busy cycles -system.cpu1.not_idle_fraction 0.049412 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.950588 # Percentage of idle cycles +system.cpu1.num_cc_register_reads 36014934 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26882843 # number of times the CC registers were written +system.cpu1.num_mem_refs 4560424 # number of memory refs +system.cpu1.num_load_insts 2872895 # Number of load instructions +system.cpu1.num_store_insts 1687529 # Number of store instructions +system.cpu1.num_idle_cycles 2475874291.383945 # Number of idle cycles +system.cpu1.num_busy_cycles 130137034.616055 # Number of busy cycles +system.cpu1.not_idle_fraction 0.049937 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.950063 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28668505 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28668505 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 293936 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26313496 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25716329 # Number of BTB hits +system.cpu2.branchPred.lookups 29049356 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29049356 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 330189 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26516680 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25920061 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.730568 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 531231 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 59742 # Number of incorrect RAS predictions. -system.cpu2.numCycles 154176343 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.750024 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 553809 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 66194 # Number of incorrect RAS predictions. +system.cpu2.numCycles 157465018 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9183670 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 141279801 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28668505 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26247560 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 54165747 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1372429 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 60595 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 24017130 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 2633 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 7414 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 19025 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 334 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3057990 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 134510 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1720 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 88520588 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.147296 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.411069 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10014190 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 143120520 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29049356 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26473870 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 54776048 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1540394 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 78659 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 25463388 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 3574 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 6100 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 25165 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 454 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3264432 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 152504 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2125 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 91560833 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 3.080398 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.405930 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 34483261 38.96% 38.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 569039 0.64% 39.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23712203 26.79% 66.39% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 303942 0.34% 66.73% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 596203 0.67% 67.40% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 791828 0.89% 68.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 321684 0.36% 68.66% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 518300 0.59% 69.25% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27224128 30.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 36927513 40.33% 40.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 611138 0.67% 41.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23812381 26.01% 67.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 328703 0.36% 67.36% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 619714 0.68% 68.04% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 832275 0.91% 68.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 355282 0.39% 69.34% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 540716 0.59% 69.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27533111 30.07% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 88520588 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.185946 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.916352 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10629848 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 22917593 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 30946726 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1286674 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1067388 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 277843876 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 5 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1067388 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 11607450 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 13707721 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4125990 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 31086433 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5253313 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 276918591 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 6816 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2458805 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 2129053 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 330941436 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 602250525 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 370032440 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 42 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 321416172 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 9525262 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 139074 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 139963 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 11350220 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6069912 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3334552 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 325084 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 284462 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 275324678 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 401766 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 273874447 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 58026 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 6719880 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10332541 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 51920 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 88520588 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.093907 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.392477 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 91560833 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.184481 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.908904 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 11521398 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 24357574 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 32837645 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1316376 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1196608 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 281192085 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 11 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1196608 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 12539536 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 14626708 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4503596 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 32964525 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5398696 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 280154725 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 7234 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2491982 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 2219031 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 334708153 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 610319016 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 374834819 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 324049688 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10658465 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 153621 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 154561 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 11685330 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6409686 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3556417 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 350066 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 288206 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 278401976 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 420214 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 276663998 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 65469 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7519016 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11586940 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 57670 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 91560833 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 3.021641 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.405034 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 25429283 28.73% 28.73% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6033030 6.82% 35.54% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3870306 4.37% 39.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2690716 3.04% 42.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 25010151 28.25% 71.21% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1323131 1.49% 72.70% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23827077 26.92% 99.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 285216 0.32% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 51678 0.06% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 27548029 30.09% 30.09% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6302445 6.88% 36.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 4040687 4.41% 41.38% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2809709 3.07% 44.45% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 25166051 27.49% 71.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1389542 1.52% 73.46% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23947180 26.15% 99.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 301462 0.33% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 55728 0.06% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 88520588 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 91560833 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 120453 33.21% 33.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 124 0.03% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 190037 52.39% 85.63% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 52134 14.37% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 136321 35.17% 35.17% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 124 0.03% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 194124 50.09% 85.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 56993 14.71% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 69880 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 264196051 96.47% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 53857 0.02% 96.51% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 45427 0.02% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6378380 2.33% 98.86% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3130852 1.14% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 81905 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 266468718 96.31% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 56660 0.02% 96.37% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 48242 0.02% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6674536 2.41% 98.79% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3333937 1.21% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 273874447 # Type of FU issued -system.cpu2.iq.rate 1.776371 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 362748 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001325 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 636728050 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 282449613 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 272560977 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 75 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 74 # Number of floating instruction queue writes +system.cpu2.iq.FU_type_0::total 276663998 # Type of FU issued +system.cpu2.iq.rate 1.756987 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 387562 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001401 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 645385259 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 286345237 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 275267423 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 94 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 106 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 22 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 274167280 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 35 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 638144 # Number of loads that had data forwarded from stores +system.cpu2.iq.int_alu_accesses 276969613 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 42 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 657734 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 933920 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 7005 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 3826 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 481474 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1052819 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6947 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4672 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 529632 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 656274 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 10618 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 656268 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 10631 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1067388 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9024497 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 812904 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 275726444 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 67814 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6069912 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3334552 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 224273 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 631637 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 3885 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 3826 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 167894 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 164610 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 332504 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 273407129 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6276348 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 467317 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1196608 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 9811775 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 820688 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 278822190 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 75669 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6409704 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3556417 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 239796 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 634227 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 4101 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4672 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 184871 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 190702 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 375573 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 276137017 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6556879 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 526981 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9343774 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27815177 # Number of branches executed -system.cpu2.iew.exec_stores 3067426 # Number of stores executed -system.cpu2.iew.exec_rate 1.773340 # Inst execution rate -system.cpu2.iew.wb_sent 273265355 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 272560999 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 212629872 # num instructions producing a value -system.cpu2.iew.wb_consumers 347702126 # num instructions consuming a value +system.cpu2.iew.exec_refs 9821909 # number of memory reference insts executed +system.cpu2.iew.exec_branches 28090459 # Number of branches executed +system.cpu2.iew.exec_stores 3265030 # Number of stores executed +system.cpu2.iew.exec_rate 1.753640 # Inst execution rate +system.cpu2.iew.wb_sent 275979435 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 275267445 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 214496489 # num instructions producing a value +system.cpu2.iew.wb_consumers 350700107 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.767852 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.611529 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.748118 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.611624 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7002811 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 349846 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 295934 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 87453200 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 3.072767 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.870996 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7834345 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 362544 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 332977 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 90364225 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 2.998816 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.871519 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 30168588 34.50% 34.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4310788 4.93% 39.43% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1198483 1.37% 40.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24616834 28.15% 68.95% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 847666 0.97% 69.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 576601 0.66% 70.57% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 339942 0.39% 70.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23302626 26.65% 97.61% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2091672 2.39% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 32381210 35.83% 35.83% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4545159 5.03% 40.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1281676 1.42% 42.28% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24783522 27.43% 69.71% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 890698 0.99% 70.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 597656 0.66% 71.36% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 358639 0.40% 71.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23381642 25.87% 97.63% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2144023 2.37% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 87453200 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 136077774 # Number of instructions committed -system.cpu2.commit.committedOps 268723335 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 90364225 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 137308621 # Number of instructions committed +system.cpu2.commit.committedOps 270985661 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 7989069 # Number of memory references committed -system.cpu2.commit.loads 5135991 # Number of loads committed -system.cpu2.commit.membars 163538 # Number of memory barriers committed -system.cpu2.commit.branches 27499066 # Number of branches committed +system.cpu2.commit.refs 8383670 # Number of memory references committed +system.cpu2.commit.loads 5356885 # Number of loads committed +system.cpu2.commit.membars 165489 # Number of memory barriers committed +system.cpu2.commit.branches 27738642 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 245318960 # Number of committed integer instructions. -system.cpu2.commit.function_calls 428759 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 2091672 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 247503684 # Number of committed integer instructions. +system.cpu2.commit.function_calls 442390 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 2144023 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 361063162 # The number of ROB reads -system.cpu2.rob.rob_writes 552523197 # The number of ROB writes -system.cpu2.timesIdled 466136 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65655755 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4909695924 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 136077774 # Number of Instructions Simulated -system.cpu2.committedOps 268723335 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 136077774 # Number of Instructions Simulated -system.cpu2.cpi 1.133002 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.133002 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.882611 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.882611 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 363659019 # number of integer regfile reads -system.cpu2.int_regfile_writes 218348978 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72934 # number of floating regfile reads +system.cpu2.rob.rob_reads 367011505 # The number of ROB reads +system.cpu2.rob.rob_writes 558841004 # The number of ROB writes +system.cpu2.timesIdled 481956 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 65904185 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4905068069 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 137308621 # Number of Instructions Simulated +system.cpu2.committedOps 270985661 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 137308621 # Number of Instructions Simulated +system.cpu2.cpi 1.146796 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.146796 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.871994 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.871994 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 367544012 # number of integer regfile reads +system.cpu2.int_regfile_writes 220503659 # number of integer regfile writes +system.cpu2.fp_regfile_reads 72990 # number of floating regfile reads system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes -system.cpu2.cc_regfile_reads 138971726 # number of cc regfile reads -system.cpu2.cc_regfile_writes 107072573 # number of cc regfile writes -system.cpu2.misc_regfile_reads 88484504 # number of misc regfile reads -system.cpu2.misc_regfile_writes 124462 # number of misc regfile writes +system.cpu2.cc_regfile_reads 140406201 # number of cc regfile reads +system.cpu2.cc_regfile_writes 108013944 # number of cc regfile writes +system.cpu2.misc_regfile_reads 89640596 # number of misc regfile reads +system.cpu2.misc_regfile_writes 136839 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index e070ad588..ab0c1f304 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,18 +173,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -202,16 +216,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -220,22 +237,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -244,22 +265,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -268,10 +293,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -280,124 +307,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -406,10 +454,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -418,16 +468,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -436,10 +489,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -450,6 +505,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -472,14 +528,17 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -498,12 +557,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -514,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -536,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -560,9 +625,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -574,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -598,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -609,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 6e907f4cc..a6e3b7d23 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026913 # Number of seconds simulated -sim_ticks 26912680500 # Number of ticks simulated -final_tick 26912680500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026911 # Number of seconds simulated +sim_ticks 26911413000 # Number of ticks simulated +final_tick 26911413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145850 # Simulator instruction rate (inst/s) -host_op_rate 146897 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43329539 # Simulator tick rate (ticks/s) -host_mem_usage 407732 # Number of bytes of host memory used -host_seconds 621.12 # Real time elapsed on the host +host_inst_rate 116759 # Simulator instruction rate (inst/s) +host_op_rate 117598 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34685583 # Simulator tick rate (ticks/s) +host_mem_usage 427272 # Number of bytes of host memory used +host_seconds 775.87 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory -system.physmem.bytes_read::total 992896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15514 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1681289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35211951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36893241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1681289 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1681289 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1681289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35211951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 36893241 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15514 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 45440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947712 # Number of bytes read from this memory +system.physmem.bytes_read::total 993152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 45440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45440 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 710 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14808 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15518 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1688503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35215988 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36904491 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1688503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1688503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1688503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35215988 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 36904491 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15518 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 15514 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 15518 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 992896 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 993152 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 992896 # Total read bytes from the system interface side +system.physmem.bytesReadSys 993152 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 988 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 987 # Per bank write bursts system.physmem.perBankRdBursts::1 886 # Per bank write bursts -system.physmem.perBankRdBursts::2 943 # Per bank write bursts +system.physmem.perBankRdBursts::2 942 # Per bank write bursts system.physmem.perBankRdBursts::3 1028 # Per bank write bursts -system.physmem.perBankRdBursts::4 1049 # Per bank write bursts +system.physmem.perBankRdBursts::4 1050 # Per bank write bursts system.physmem.perBankRdBursts::5 1105 # Per bank write bursts system.physmem.perBankRdBursts::6 1078 # Per bank write bursts -system.physmem.perBankRdBursts::7 1078 # Per bank write bursts +system.physmem.perBankRdBursts::7 1080 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts -system.physmem.perBankRdBursts::9 956 # Per bank write bursts +system.physmem.perBankRdBursts::9 959 # Per bank write bursts system.physmem.perBankRdBursts::10 938 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts system.physmem.perBankRdBursts::12 904 # Per bank write bursts @@ -73,14 +73,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26912480500 # Total gap between requests +system.physmem.totGap 26911220500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15514 # Read request sizes (log2) +system.physmem.readPktSize::6 15518 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -88,9 +88,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 11168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 11172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 169 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see @@ -152,125 +152,126 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 617 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1603.423015 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 482.832317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2202.245443 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 156 25.28% 25.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 69 11.18% 36.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 40 6.48% 42.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 21 3.40% 46.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 12 1.94% 48.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 6 0.97% 49.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 26 4.21% 53.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 13 2.11% 55.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 5 0.81% 56.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 9 1.46% 57.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 4 0.65% 58.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 4 0.65% 59.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 5 0.81% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 8 1.30% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 3 0.49% 61.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 3 0.49% 62.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 6 0.97% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 2 0.32% 63.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.32% 63.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.49% 64.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.32% 64.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 4 0.65% 65.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 6 0.97% 66.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 19 3.08% 69.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 6 0.97% 70.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 6 0.97% 71.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 3 0.49% 71.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 3 0.49% 72.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 1 0.16% 72.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 6 0.97% 73.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.32% 73.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 6 0.97% 74.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.32% 75.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.16% 75.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 3 0.49% 75.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.16% 75.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 2 0.32% 76.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.16% 76.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 5 0.81% 77.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 4 0.65% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 2 0.32% 78.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 3 0.49% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 4 0.65% 79.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 2 0.32% 79.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 2 0.32% 79.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 2 0.32% 80.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 3 0.49% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.16% 80.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 2 0.32% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.16% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 3 0.49% 81.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 3 0.49% 82.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 2 0.32% 82.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.16% 82.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 1 0.16% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.16% 83.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 3 0.49% 83.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 2 0.32% 83.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.16% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 3 0.49% 84.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 4 0.65% 85.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 4 0.65% 85.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.16% 86.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 3 0.49% 86.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 2 0.32% 86.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 2 0.32% 87.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.16% 87.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 2 0.32% 87.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.16% 87.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 2 0.32% 88.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 5 0.81% 88.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 3 0.49% 89.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 4 0.65% 90.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 2 0.32% 90.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 7 1.13% 91.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 2 0.32% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 1 0.16% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 1 0.16% 92.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 1 0.16% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.16% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 3 0.49% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 1 0.16% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.32% 93.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 1 0.16% 93.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 2 0.32% 94.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 3 0.49% 94.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.16% 94.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 2 0.32% 94.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.16% 95.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 3 0.49% 95.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.16% 95.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.16% 95.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.16% 96.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.16% 96.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.16% 96.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.32% 96.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.16% 96.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.16% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.16% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.32% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.16% 97.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 1598.759289 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 481.680955 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2200.761860 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 153 24.72% 24.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 75 12.12% 36.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 40 6.46% 43.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 20 3.23% 46.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 12 1.94% 48.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 6 0.97% 49.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 27 4.36% 53.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 12 1.94% 55.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 5 0.81% 56.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 10 1.62% 58.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 3 0.48% 58.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 4 0.65% 59.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 5 0.81% 60.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 8 1.29% 61.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 3 0.48% 61.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 3 0.48% 62.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 6 0.97% 63.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 2 0.32% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 2 0.32% 63.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 3 0.48% 64.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 2 0.32% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 4 0.65% 65.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 6 0.97% 66.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 19 3.07% 69.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 6 0.97% 70.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 6 0.97% 71.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 3 0.48% 71.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 3 0.48% 72.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 1 0.16% 72.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 6 0.97% 73.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.32% 73.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 6 0.97% 74.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.32% 75.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.16% 75.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 3 0.48% 75.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 1 0.16% 75.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 2 0.32% 76.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.16% 76.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 5 0.81% 77.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 4 0.65% 77.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 2 0.32% 78.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 3 0.48% 78.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 4 0.65% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 2 0.32% 79.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 2 0.32% 79.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 2 0.32% 80.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 3 0.48% 80.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.16% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 2 0.32% 81.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.16% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 3 0.48% 81.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 3 0.48% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 2 0.32% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.16% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 1 0.16% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.16% 83.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 3 0.48% 83.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 2 0.32% 84.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 1 0.16% 84.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 3 0.48% 84.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 4 0.65% 85.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 4 0.65% 85.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.16% 86.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 3 0.48% 86.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 2 0.32% 86.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 2 0.32% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.16% 87.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 2 0.32% 87.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.16% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 2 0.32% 88.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 5 0.81% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 3 0.48% 89.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 4 0.65% 90.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 2 0.32% 90.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 6 0.97% 91.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 3 0.48% 91.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 1 0.16% 92.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 1 0.16% 92.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 1 0.16% 92.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.16% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 3 0.48% 93.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 1 0.16% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.32% 93.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 1 0.16% 93.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 2 0.32% 94.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 3 0.48% 94.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.16% 94.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 2 0.32% 94.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.16% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 3 0.48% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.16% 95.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.16% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.16% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.16% 96.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.16% 96.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 2 0.32% 96.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.16% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.16% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.16% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 1 0.16% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 1 0.16% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 1 0.16% 97.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 2 0.32% 98.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 12 1.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 617 # Bytes accessed per row activation -system.physmem.totQLat 103133500 # Total ticks spent queuing -system.physmem.totMemAccLat 356414750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77570000 # Total ticks spent in databus transfers -system.physmem.totBankLat 175711250 # Total ticks spent accessing banks -system.physmem.avgQLat 6647.77 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 11325.98 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::total 619 # Bytes accessed per row activation +system.physmem.totQLat 103760250 # Total ticks spent queuing +system.physmem.totMemAccLat 357130250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77590000 # Total ticks spent in databus transfers +system.physmem.totBankLat 175780000 # Total ticks spent accessing banks +system.physmem.avgQLat 6686.44 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11327.49 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 22973.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23013.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 36.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.89 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 36.90 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.29 # Data bus utilization in percentage @@ -278,37 +279,39 @@ system.physmem.busUtilRead 0.29 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14897 # Number of row buffer hits during reads +system.physmem.readRowHits 14899 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.02 # Row buffer hit rate for reads +system.physmem.readRowHitRate 96.01 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1734722.22 # Average gap between requests -system.physmem.pageHitRate 96.02 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.95 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 36893241 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 976 # Transaction distribution -system.membus.trans_dist::ReadResp 976 # Transaction distribution +system.physmem.avgGap 1734193.87 # Average gap between requests +system.physmem.pageHitRate 96.01 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.04 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 36904491 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 980 # Transaction distribution +system.membus.trans_dist::ReadResp 980 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1 # Transaction distribution system.membus.trans_dist::ReadExReq 14538 # Transaction distribution system.membus.trans_dist::ReadExResp 14538 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31028 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31028 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992896 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 992896 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 992896 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31038 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31038 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 993152 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 993152 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 993152 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 19247000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 19253000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 145153250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 145189999 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu.branchPred.lookups 26684421 # Number of BP lookups -system.cpu.branchPred.condPredicted 22003515 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 842640 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11361703 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11279248 # Number of BTB hits +system.cpu.branchPred.lookups 26686306 # Number of BP lookups +system.cpu.branchPred.condPredicted 22003847 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 843168 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11366672 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11283030 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.274273 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 70578 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 175 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.264147 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 70474 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 170 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -352,99 +355,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53825362 # number of cpu cycles simulated +system.cpu.numCycles 53822827 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14170521 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127888749 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26684421 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11349826 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24033756 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4765472 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11324127 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 14174375 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127897951 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26686306 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11353504 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24037647 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4766390 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11312706 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 108 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13841798 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 328713 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53434811 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.409872 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.214791 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13845393 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 329438 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53431463 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.410222 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.214882 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29439353 55.09% 55.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3386965 6.34% 61.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2028576 3.80% 65.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1554110 2.91% 68.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1668608 3.12% 71.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2917595 5.46% 76.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1511603 2.83% 79.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1091436 2.04% 81.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9836565 18.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29432152 55.08% 55.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3389873 6.34% 61.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2028658 3.80% 65.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1553769 2.91% 68.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1668148 3.12% 71.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2920061 5.47% 76.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1509677 2.83% 79.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1090745 2.04% 81.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9838380 18.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53434811 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.495759 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.375994 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16934142 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9169646 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22402191 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1031199 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3897633 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4442994 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8719 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126071688 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42592 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3897633 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18714767 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3594336 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 187938 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21550636 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5489501 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123153089 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 427273 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4600360 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1278 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143605134 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536434214 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 500014017 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 784 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 53431463 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.495818 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.376277 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16937925 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9159010 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22405754 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1030805 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3897969 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4444268 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8691 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126081524 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42632 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3897969 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18719458 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3589629 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 186437 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21552986 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5484984 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123156725 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 9 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 425837 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4596994 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1284 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143603336 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536446832 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 500029218 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 672 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36190948 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4612 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4610 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12546346 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29477793 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5522687 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2151443 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1269536 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118168344 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8478 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105154526 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 78994 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26741749 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65618769 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 260 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53434811 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.967903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.908534 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 36189150 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4635 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4633 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12540789 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29477429 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5520545 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2151265 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1294097 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118170448 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8500 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105167442 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 79307 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26742090 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65583646 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53431463 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.968268 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.908949 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15376938 28.78% 28.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11654897 21.81% 50.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8243564 15.43% 66.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6824643 12.77% 78.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4966766 9.30% 88.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2946722 5.51% 93.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2453138 4.59% 98.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 526074 0.98% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 442069 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15374280 28.77% 28.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11649569 21.80% 50.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8250468 15.44% 66.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6827782 12.78% 78.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4953380 9.27% 88.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2948609 5.52% 93.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2456731 4.60% 98.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 528512 0.99% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 442132 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53434811 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53431463 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45800 6.91% 6.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45750 6.92% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 27 0.00% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available @@ -473,13 +476,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 340417 51.39% 58.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 276226 41.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 340320 51.44% 58.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 275443 41.64% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74421271 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10977 0.01% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74429619 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10979 0.01% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued @@ -501,90 +504,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 148 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 129 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 190 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 165 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25608548 24.35% 95.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5113387 4.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25613153 24.35% 95.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5113394 4.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105154526 # Type of FU issued -system.cpu.iq.rate 1.953624 # Inst issue rate -system.cpu.iq.fu_busy_cnt 662470 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006300 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264484578 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144923147 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102682900 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 749 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1045 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 323 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105816623 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 373 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 441366 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105167442 # Type of FU issued +system.cpu.iq.rate 1.953956 # Inst issue rate +system.cpu.iq.fu_busy_cnt 661540 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006290 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 264506537 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144925816 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102691564 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 657 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 923 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 287 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105828655 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 327 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 441760 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6903827 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6492 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6312 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 777843 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6903463 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6716 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6442 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 775701 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31495 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 31606 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3897633 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 959563 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 126871 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118189516 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 310121 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29477793 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5522687 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4590 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 65719 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6709 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6312 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 446751 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 446217 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892968 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104180481 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25289750 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 974045 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3897969 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 957023 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 126637 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118191644 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 310003 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29477429 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5520545 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4612 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 65722 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6738 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6442 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 447212 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 446019 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 893231 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104191675 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25292948 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 975767 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12694 # number of nop insts executed -system.cpu.iew.exec_refs 30346354 # number of memory reference insts executed -system.cpu.iew.exec_branches 21325110 # Number of branches executed -system.cpu.iew.exec_stores 5056604 # Number of stores executed -system.cpu.iew.exec_rate 1.935528 # Inst execution rate -system.cpu.iew.wb_sent 102961531 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102683223 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62241416 # num instructions producing a value -system.cpu.iew.wb_consumers 104299638 # num instructions consuming a value +system.cpu.iew.exec_nop 12696 # number of nop insts executed +system.cpu.iew.exec_refs 30349771 # number of memory reference insts executed +system.cpu.iew.exec_branches 21326762 # Number of branches executed +system.cpu.iew.exec_stores 5056823 # Number of stores executed +system.cpu.iew.exec_rate 1.935827 # Inst execution rate +system.cpu.iew.wb_sent 102970942 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102691851 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62249009 # num instructions producing a value +system.cpu.iew.wb_consumers 104309545 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.907711 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596756 # average fanout of values written-back +system.cpu.iew.wb_rate 1.907961 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596772 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26939491 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 26941617 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 834010 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49537178 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.842111 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.540648 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 834570 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49533494 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.842248 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.540561 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20048697 40.47% 40.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13146284 26.54% 67.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4166513 8.41% 75.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3429547 6.92% 82.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1533299 3.10% 85.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 729419 1.47% 86.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 954733 1.93% 88.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 253168 0.51% 89.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5275518 10.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20042935 40.46% 40.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13146551 26.54% 67.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4167484 8.41% 75.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3431298 6.93% 82.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1535317 3.10% 85.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 726626 1.47% 86.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 954928 1.93% 88.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 253259 0.51% 89.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5275096 10.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49537178 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 49533494 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -595,218 +598,222 @@ system.cpu.commit.branches 18732304 # Nu system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5275518 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5275096 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162448377 # The number of ROB reads -system.cpu.rob.rob_writes 240302265 # The number of ROB writes -system.cpu.timesIdled 46020 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 390551 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 162447241 # The number of ROB reads +system.cpu.rob.rob_writes 240306728 # The number of ROB writes +system.cpu.timesIdled 46009 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 391364 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated -system.cpu.cpi 0.594166 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.594166 # CPI: Total CPI of All Threads -system.cpu.ipc 1.683032 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.683032 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495553334 # number of integer regfile reads -system.cpu.int_regfile_writes 120547287 # number of integer regfile writes -system.cpu.fp_regfile_reads 170 # number of floating regfile reads -system.cpu.fp_regfile_writes 410 # number of floating regfile writes -system.cpu.misc_regfile_reads 29088502 # number of misc regfile reads +system.cpu.cpi 0.594138 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.594138 # CPI: Total CPI of All Threads +system.cpu.ipc 1.683111 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.683111 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495604527 # number of integer regfile reads +system.cpu.int_regfile_writes 120552200 # number of integer regfile writes +system.cpu.fp_regfile_reads 148 # number of floating regfile reads +system.cpu.fp_regfile_writes 360 # number of floating regfile writes +system.cpu.misc_regfile_reads 29090078 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4497529557 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 904650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 942911 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43698 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43698 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1465 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838143 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2839608 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120993664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 121040512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 121040512 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 1888541000 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 4497665284 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 904635 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904635 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 942892 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 43700 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 43700 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1472 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838092 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2839564 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 47040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120991360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 121038400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 121038400 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 1888506500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1216499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1222499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1424134990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1424110491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 633.195127 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13840808 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 732 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18908.207650 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 632.612747 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13844401 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 735 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18835.919728 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 633.195127 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.309177 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.309177 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13840808 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13840808 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13840808 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13840808 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13840808 # number of overall hits -system.cpu.icache.overall_hits::total 13840808 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 989 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 989 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 989 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 989 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 989 # number of overall misses -system.cpu.icache.overall_misses::total 989 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 66791248 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 66791248 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 66791248 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 66791248 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 66791248 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 66791248 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13841797 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13841797 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13841797 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13841797 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13841797 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13841797 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67534.123357 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67534.123357 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67534.123357 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67534.123357 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67534.123357 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67534.123357 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 596 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 632.612747 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.308893 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.308893 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13844401 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13844401 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13844401 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13844401 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13844401 # number of overall hits +system.cpu.icache.overall_hits::total 13844401 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 991 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 991 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 991 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 991 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 991 # number of overall misses +system.cpu.icache.overall_misses::total 991 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 67770748 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 67770748 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 67770748 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 67770748 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 67770748 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 67770748 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13845392 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13845392 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13845392 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13845392 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13845392 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13845392 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000072 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000072 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000072 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000072 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000072 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000072 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68386.224016 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68386.224016 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68386.224016 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68386.224016 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68386.224016 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68386.224016 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 651 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 54.181818 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.181818 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 256 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 256 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 256 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 256 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 256 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 256 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 733 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 733 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 733 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 733 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50590750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 50590750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50590750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 50590750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50590750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 50590750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 254 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 254 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 254 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 254 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 254 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 737 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 737 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 737 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 737 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 737 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 737 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51712250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 51712250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51712250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 51712250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51712250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 51712250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69018.758527 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69018.758527 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69018.758527 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69018.758527 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69018.758527 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69018.758527 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70165.875170 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70165.875170 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70165.875170 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70165.875170 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70165.875170 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70165.875170 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10730.387703 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1831429 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15497 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 118.179583 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 10730.950237 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1831391 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15501 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 118.146636 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9881.039169 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 619.212620 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 230.135914 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.301545 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018897 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007023 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.327465 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 9880.493814 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 618.630242 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 231.826182 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.301529 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018879 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007075 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.327483 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 903638 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903662 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942911 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942911 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 903618 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 903642 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 942892 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 942892 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 29160 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 29160 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 29162 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 29162 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932798 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932822 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 932780 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 932804 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932798 # number of overall hits -system.cpu.l2cache.overall_hits::total 932822 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 708 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 279 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 987 # number of ReadReq misses +system.cpu.l2cache.overall_hits::cpu.data 932780 # number of overall hits +system.cpu.l2cache.overall_hits::total 932804 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 711 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 280 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 991 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 708 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14817 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15525 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 708 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 14817 # number of overall misses -system.cpu.l2cache.overall_misses::total 15525 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 49612500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21119250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 70731750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 962947000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 962947000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 49612500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 984066250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1033678750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 49612500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 984066250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1033678750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 732 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 903917 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 904649 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 942911 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 942911 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 43698 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 43698 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 732 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 947615 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 948347 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 732 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 947615 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 948347 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967213 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000309 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001091 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.332693 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.332693 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967213 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.015636 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016371 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967213 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.015636 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016371 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70074.152542 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75696.236559 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71663.373860 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66236.552483 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66236.552483 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70074.152542 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66414.675710 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66581.561997 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70074.152542 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66414.675710 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66581.561997 # average overall miss latency +system.cpu.l2cache.demand_misses::cpu.inst 711 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14818 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15529 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 711 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 14818 # number of overall misses +system.cpu.l2cache.overall_misses::total 15529 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50729000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21404500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 72133500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 962429750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 962429750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 50729000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 983834250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1034563250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 50729000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 983834250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1034563250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 735 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 903898 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 904633 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 942892 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 942892 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 43700 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 43700 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 735 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 947598 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 948333 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 735 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 947598 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 948333 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967347 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000310 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001095 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.332677 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.332677 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967347 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015637 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016375 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967347 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015637 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016375 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71348.804501 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76444.642857 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72788.597376 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66200.973311 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66200.973311 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71348.804501 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66394.537050 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66621.369695 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71348.804501 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66394.537050 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66621.369695 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -824,176 +831,184 @@ system.cpu.l2cache.demand_mshr_hits::total 11 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 707 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 269 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 976 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 710 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 270 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 980 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 707 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14807 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15514 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 707 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14807 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15514 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40706750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17150500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 57857250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 780571000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 780571000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40706750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 797721500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 838428250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40706750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 797721500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 838428250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965847 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000298 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001079 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332693 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332693 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965847 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015626 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016359 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965847 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015626 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016359 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57576.732673 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63756.505576 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59279.969262 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53691.773284 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53691.773284 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57576.732673 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53874.620112 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54043.331829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57576.732673 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53874.620112 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54043.331829 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 710 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14808 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15518 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 710 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14808 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15518 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41786750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17438000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 59224750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 780053750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 780053750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41786750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 797491750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 839278500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41786750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 797491750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 839278500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965986 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000299 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001083 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332677 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332677 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965986 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016363 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965986 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016363 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58854.577465 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64585.185185 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60433.418367 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53656.194112 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53656.194112 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58854.577465 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53855.466640 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54084.192551 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58854.577465 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53855.466640 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54084.192551 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 943519 # number of replacements -system.cpu.dcache.tags.tagsinuse 3671.753264 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28141899 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 947615 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.697608 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 8006034000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3671.753264 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.896424 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.896424 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23601231 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23601231 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4532867 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4532867 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3910 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3910 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 943502 # number of replacements +system.cpu.dcache.tags.tagsinuse 3671.733270 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28144425 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 947598 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.700807 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 8006035000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3671.733270 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.896419 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.896419 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23603772 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23603772 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4532846 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4532846 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3913 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3913 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28134098 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28134098 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28134098 # number of overall hits -system.cpu.dcache.overall_hits::total 28134098 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1173780 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1173780 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 202114 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 202114 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 28136618 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28136618 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28136618 # number of overall hits +system.cpu.dcache.overall_hits::total 28136618 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1173981 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1173981 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 202135 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 202135 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1375894 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1375894 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1375894 # number of overall misses -system.cpu.dcache.overall_misses::total 1375894 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13893621478 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13893621478 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8458573839 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8458573839 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1376116 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1376116 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1376116 # number of overall misses +system.cpu.dcache.overall_misses::total 1376116 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13894448479 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13894448479 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8458649331 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8458649331 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 251500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22352195317 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22352195317 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22352195317 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22352195317 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24775011 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24775011 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 22353097810 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22353097810 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22353097810 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22353097810 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24777753 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24777753 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3917 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3917 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3920 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3920 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29509992 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29509992 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29509992 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29509992 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047378 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047378 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042685 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.042685 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001787 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001787 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046625 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046625 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046625 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046625 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11836.648672 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11836.648672 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41850.509312 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41850.509312 # average WriteReq miss latency +system.cpu.dcache.demand_accesses::cpu.data 29512734 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29512734 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29512734 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29512734 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047380 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047380 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042690 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.042690 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001786 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001786 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046628 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046628 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046628 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046628 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.326533 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.326533 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41846.534895 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41846.534895 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16245.579468 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16245.579468 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16245.579468 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16245.579468 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 154256 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16243.614499 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16243.614499 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16243.614499 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16243.614499 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 154190 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23951 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23957 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.440483 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.436115 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942911 # number of writebacks -system.cpu.dcache.writebacks::total 942911 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269842 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 269842 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158436 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158436 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks +system.cpu.dcache.writebacks::total 942892 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 270066 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 270066 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158450 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158450 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 428278 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 428278 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 428278 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 428278 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903938 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903938 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43678 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43678 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947616 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947616 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947616 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947616 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994572760 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994572760 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1319332173 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1319332173 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11313904933 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11313904933 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11313904933 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11313904933 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036486 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036486 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009225 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009225 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032112 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032112 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032112 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032112 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.701632 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.701632 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30205.874193 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30205.874193 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11939.335061 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11939.335061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11939.335061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11939.335061 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 428516 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 428516 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 428516 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 428516 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903915 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903915 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43685 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43685 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947600 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947600 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947600 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947600 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994483010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994483010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1318924416 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1318924416 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11313407426 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11313407426 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11313407426 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11313407426 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036481 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036481 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009226 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009226 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032108 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032108 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032108 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032108 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.883678 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.883678 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30191.700034 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30191.700034 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11939.011636 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11939.011636 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11939.011636 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11939.011636 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index 11900168b..a7b21f16f 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -125,6 +131,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.branchPred] type=BranchPredictor @@ -133,6 +140,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -148,6 +156,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -170,18 +179,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[3] @@ -190,15 +202,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -207,16 +222,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -225,22 +243,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -249,22 +271,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -273,10 +299,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -285,124 +313,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -411,10 +460,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -423,16 +474,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -441,10 +495,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -455,6 +511,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -477,12 +534,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -493,16 +552,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[2] @@ -513,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -535,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -550,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -559,9 +625,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -573,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -597,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -608,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 1149689b6..999935db6 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.065614 # Nu sim_ticks 65613727000 # Number of ticks simulated final_tick 65613727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90206 # Simulator instruction rate (inst/s) -host_op_rate 158838 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37463203 # Simulator tick rate (ticks/s) -host_mem_usage 416624 # Number of bytes of host memory used -host_seconds 1751.42 # Real time elapsed on the host +host_inst_rate 72100 # Simulator instruction rate (inst/s) +host_op_rate 126957 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29943715 # Simulator tick rate (ticks/s) +host_mem_usage 436724 # Number of bytes of host memory used +host_seconds 2191.24 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory @@ -296,9 +296,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1957440 system.membus.tot_pkt_size::total 1957440 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 1957440 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 34950000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 34950500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 284208500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 284209000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) system.cpu.branchPred.lookups 33859770 # Number of BP lookups system.cpu.branchPred.condPredicted 33859770 # Number of conditional branches predicted @@ -373,24 +373,24 @@ system.cpu.memDep0.insertedLoads 101555761 # Nu system.cpu.memDep0.insertedStores 34778058 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 39627069 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 5861390 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 311484168 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 311484166 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 1638 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 300275526 # Number of instructions issued +system.cpu.iq.iqInstsIssued 300275524 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 89306 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32714420 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 46115213 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 32714418 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 46115217 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1193 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 131122211 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.290043 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.698539 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 24369701 18.59% 18.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23163236 17.67% 36.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23163237 17.67% 36.25% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 25526976 19.47% 55.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25864201 19.73% 75.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18882897 14.40% 89.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8250399 6.29% 96.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3948646 3.01% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25864200 19.73% 75.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18882898 14.40% 89.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8250397 6.29% 96.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3948647 3.01% 99.15% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 938964 0.72% 99.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 177191 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle @@ -427,12 +427,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1917678 93.05% 94.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1917677 93.05% 94.57% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 111849 5.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 31277 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 169841030 56.56% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 169841029 56.56% 56.57% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 11216 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 331 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 34 0.00% 56.58% # Type of FU issued @@ -461,27 +461,27 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.58% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97301452 32.40% 88.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97301451 32.40% 88.98% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 33090186 11.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 300275526 # Type of FU issued +system.cpu.iq.FU_type_0::total 300275524 # Type of FU issued system.cpu.iq.rate 2.288206 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2060963 # FU busy when requested +system.cpu.iq.fu_busy_cnt 2060962 # FU busy when requested system.cpu.iq.fu_busy_rate 0.006864 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 733823009 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344232042 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 298020707 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 733823004 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344232038 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 298020704 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 523 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 719 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 302304971 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 302304968 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 241 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 54149706 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 10776376 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 31264 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33345 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.ignoredResponses 31265 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33344 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 3338306 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding @@ -491,35 +491,35 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewSquashCycles 4544234 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 2798212 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 162335 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 311485806 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 311485804 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 196342 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 101555761 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 34778058 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 470 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2616 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 73755 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33345 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 33344 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 393170 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 428306 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 821476 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 298872687 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 96891555 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1402839 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 298872684 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 96891554 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1402840 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 129817499 # number of memory reference insts executed +system.cpu.iew.exec_refs 129817497 # number of memory reference insts executed system.cpu.iew.exec_branches 30820824 # Number of branches executed -system.cpu.iew.exec_stores 32925944 # Number of stores executed +system.cpu.iew.exec_stores 32925943 # Number of stores executed system.cpu.iew.exec_rate 2.277516 # Inst execution rate -system.cpu.iew.wb_sent 298390599 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 298020863 # cumulative count of insts written-back -system.cpu.iew.wb_producers 218260008 # num instructions producing a value -system.cpu.iew.wb_consumers 296755225 # num instructions consuming a value +system.cpu.iew.wb_sent 298390596 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 298020860 # cumulative count of insts written-back +system.cpu.iew.wb_producers 218260006 # num instructions producing a value +system.cpu.iew.wb_consumers 296755223 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.271025 # insts written-back per cycle system.cpu.iew.wb_fanout 0.735488 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 33306191 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 33306189 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 774954 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 126577977 # Number of insts commited each cycle @@ -551,8 +551,8 @@ system.cpu.commit.int_insts 278169481 # Nu system.cpu.commit.function_calls 4237596 # Number of function calls committed. system.cpu.commit.bw_lim_events 22125649 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 415950983 # The number of ROB reads -system.cpu.rob.rob_writes 627545403 # The number of ROB writes +system.cpu.rob.rob_reads 415950981 # The number of ROB reads +system.cpu.rob.rob_writes 627545399 # The number of ROB writes system.cpu.timesIdled 13719 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 105249 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated @@ -562,13 +562,13 @@ system.cpu.cpi 0.830614 # CP system.cpu.cpi_total 0.830614 # CPI: Total CPI of All Threads system.cpu.ipc 1.203929 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.203929 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 483744134 # number of integer regfile reads -system.cpu.int_regfile_writes 234595253 # number of integer regfile writes +system.cpu.int_regfile_reads 483744129 # number of integer regfile reads +system.cpu.int_regfile_writes 234595251 # number of integer regfile writes system.cpu.fp_regfile_reads 141 # number of floating regfile reads system.cpu.fp_regfile_writes 77 # number of floating regfile writes system.cpu.cc_regfile_reads 107058970 # number of cc regfile reads system.cpu.cc_regfile_writes 64002830 # number of cc regfile writes -system.cpu.misc_regfile_reads 191827911 # number of misc regfile reads +system.cpu.misc_regfile_reads 191827908 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.toL2Bus.throughput 4042576518 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 1995299 # Transaction distribution @@ -611,12 +611,12 @@ system.cpu.icache.demand_misses::cpu.inst 1305 # n system.cpu.icache.demand_misses::total 1305 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1305 # number of overall misses system.cpu.icache.overall_misses::total 1305 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 88661248 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 88661248 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 88661248 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 88661248 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 88661248 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 88661248 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 88661748 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 88661748 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 88661748 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 88661748 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 88661748 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 88661748 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 25575393 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 25575393 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 25575393 # number of demand (read+write) accesses @@ -629,12 +629,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67939.653640 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67939.653640 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67939.653640 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67939.653640 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67939.653640 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67940.036782 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67940.036782 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67940.036782 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67940.036782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67940.036782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67940.036782 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -655,24 +655,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1011 system.cpu.icache.demand_mshr_misses::total 1011 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1011 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1011 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69226001 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 69226001 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69226001 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 69226001 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69226001 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 69226001 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69226501 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 69226501 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69226501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 69226501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69226501 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 69226501 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68472.800198 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68472.800198 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68472.800198 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68472.800198 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68473.294758 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68473.294758 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68473.294758 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68473.294758 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68473.294758 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68473.294758 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 479 # number of replacements system.cpu.l2cache.tags.tagsinuse 20806.493932 # Cycle average of tags in use @@ -711,17 +711,17 @@ system.cpu.l2cache.demand_misses::total 30419 # nu system.cpu.l2cache.overall_misses::cpu.inst 994 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 29425 # number of overall misses system.cpu.l2cache.overall_misses::total 30419 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68040500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68041000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29989500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 98030000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 98030500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1876802500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1876802500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 68040500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 68041000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 1906792000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1974832500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 68040500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 1974833000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 68041000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 1906792000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1974832500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1974833000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1011 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1994288 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1995299 # number of ReadReq accesses(hits+misses) @@ -746,17 +746,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.014641 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983185 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.014170 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014641 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68451.207243 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68451.710262 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71065.165877 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69230.225989 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69230.579096 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64710.633383 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64710.633383 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68451.207243 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68451.710262 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64801.767205 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 64921.019757 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68451.207243 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 64921.036194 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68451.710262 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64801.767205 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 64921.019757 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 64921.036194 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -814,21 +814,21 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52339.146586 system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 2072514 # number of replacements system.cpu.dcache.tags.tagsinuse 4069.513707 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71413624 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 71413623 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2076610 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 34.389521 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 20690834250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 4069.513707 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993534 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993534 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 40071931 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40071931 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 40071930 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40071930 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31341693 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 31341693 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71413624 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71413624 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71413624 # number of overall hits -system.cpu.dcache.overall_hits::total 71413624 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 71413623 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71413623 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71413623 # number of overall hits +system.cpu.dcache.overall_hits::total 71413623 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2625746 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2625746 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 98059 # number of WriteReq misses @@ -845,14 +845,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 34178695748 system.cpu.dcache.demand_miss_latency::total 34178695748 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 34178695748 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 34178695748 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 42697677 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 42697677 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 42697676 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 42697676 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74137429 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74137429 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74137429 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74137429 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 74137428 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74137428 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74137428 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74137428 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061496 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.061496 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 01aecce27..34784c9a2 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,18 +173,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -202,16 +216,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -220,22 +237,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -244,22 +265,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -268,10 +293,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -280,124 +307,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -406,10 +454,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -418,16 +468,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -436,10 +489,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -450,6 +505,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -472,14 +528,17 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -498,12 +557,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -514,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -536,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -560,9 +625,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/parser +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -574,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -598,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -609,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 293b4caca..3188dad03 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202724 # Number of seconds simulated -sim_ticks 202723760000 # Number of ticks simulated -final_tick 202723760000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202742 # Number of seconds simulated +sim_ticks 202741893000 # Number of ticks simulated +final_tick 202741893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119496 # Simulator instruction rate (inst/s) -host_op_rate 134724 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47946894 # Simulator tick rate (ticks/s) -host_mem_usage 278932 # Number of bytes of host memory used -host_seconds 4228.09 # Real time elapsed on the host +host_inst_rate 95210 # Simulator instruction rate (inst/s) +host_op_rate 107343 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38205910 # Simulator tick rate (ticks/s) +host_mem_usage 298452 # Number of bytes of host memory used +host_seconds 5306.56 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 217216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9267712 # Number of bytes read from this memory -system.physmem.bytes_read::total 9484928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217216 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6251136 # Number of bytes written to this memory -system.physmem.bytes_written::total 6251136 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3394 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144808 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148202 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97674 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97674 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1071488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 45715963 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 46787451 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1071488 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1071488 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30835734 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30835734 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30835734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1071488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 45715963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77623185 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148203 # Number of read requests accepted -system.physmem.writeReqs 97674 # Number of write requests accepted -system.physmem.readBursts 148203 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97674 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9479680 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5312 # Total number of bytes read from write queue -system.physmem.bytesWritten 6250624 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9484992 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6251136 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 83 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 215232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9270080 # Number of bytes read from this memory +system.physmem.bytes_read::total 9485312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 215232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 215232 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6249920 # Number of bytes written to this memory +system.physmem.bytes_written::total 6249920 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3363 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144845 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148208 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97655 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97655 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1061606 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45723555 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 46785160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1061606 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1061606 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30826979 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30826979 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30826979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1061606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45723555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 77612139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148209 # Number of read requests accepted +system.physmem.writeReqs 97655 # Number of write requests accepted +system.physmem.readBursts 148209 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97655 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9479424 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue +system.physmem.bytesWritten 6249600 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9485376 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6249920 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 11 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9589 # Per bank write bursts -system.physmem.perBankRdBursts::1 9263 # Per bank write bursts -system.physmem.perBankRdBursts::2 9230 # Per bank write bursts -system.physmem.perBankRdBursts::3 8983 # Per bank write bursts -system.physmem.perBankRdBursts::4 9781 # Per bank write bursts -system.physmem.perBankRdBursts::5 9608 # Per bank write bursts -system.physmem.perBankRdBursts::6 9123 # Per bank write bursts -system.physmem.perBankRdBursts::7 8333 # Per bank write bursts -system.physmem.perBankRdBursts::8 8801 # Per bank write bursts -system.physmem.perBankRdBursts::9 8921 # Per bank write bursts -system.physmem.perBankRdBursts::10 8939 # Per bank write bursts -system.physmem.perBankRdBursts::11 9732 # Per bank write bursts -system.physmem.perBankRdBursts::12 9670 # Per bank write bursts -system.physmem.perBankRdBursts::13 9771 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 9 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9585 # Per bank write bursts +system.physmem.perBankRdBursts::1 9243 # Per bank write bursts +system.physmem.perBankRdBursts::2 9257 # Per bank write bursts +system.physmem.perBankRdBursts::3 8972 # Per bank write bursts +system.physmem.perBankRdBursts::4 9761 # Per bank write bursts +system.physmem.perBankRdBursts::5 9639 # Per bank write bursts +system.physmem.perBankRdBursts::6 9125 # Per bank write bursts +system.physmem.perBankRdBursts::7 8321 # Per bank write bursts +system.physmem.perBankRdBursts::8 8799 # Per bank write bursts +system.physmem.perBankRdBursts::9 8911 # Per bank write bursts +system.physmem.perBankRdBursts::10 8951 # Per bank write bursts +system.physmem.perBankRdBursts::11 9736 # Per bank write bursts +system.physmem.perBankRdBursts::12 9644 # Per bank write bursts +system.physmem.perBankRdBursts::13 9766 # Per bank write bursts system.physmem.perBankRdBursts::14 8945 # Per bank write bursts -system.physmem.perBankRdBursts::15 9431 # Per bank write bursts -system.physmem.perBankWrBursts::0 6268 # Per bank write bursts -system.physmem.perBankWrBursts::1 6168 # Per bank write bursts -system.physmem.perBankWrBursts::2 6085 # Per bank write bursts -system.physmem.perBankWrBursts::3 5885 # Per bank write bursts -system.physmem.perBankWrBursts::4 6259 # Per bank write bursts -system.physmem.perBankWrBursts::5 6263 # Per bank write bursts -system.physmem.perBankWrBursts::6 6041 # Per bank write bursts -system.physmem.perBankWrBursts::7 5560 # Per bank write bursts +system.physmem.perBankRdBursts::15 9461 # Per bank write bursts +system.physmem.perBankWrBursts::0 6262 # Per bank write bursts +system.physmem.perBankWrBursts::1 6160 # Per bank write bursts +system.physmem.perBankWrBursts::2 6087 # Per bank write bursts +system.physmem.perBankWrBursts::3 5881 # Per bank write bursts +system.physmem.perBankWrBursts::4 6253 # Per bank write bursts +system.physmem.perBankWrBursts::5 6276 # Per bank write bursts +system.physmem.perBankWrBursts::6 6048 # Per bank write bursts +system.physmem.perBankWrBursts::7 5555 # Per bank write bursts system.physmem.perBankWrBursts::8 5811 # Per bank write bursts -system.physmem.perBankWrBursts::9 5905 # Per bank write bursts -system.physmem.perBankWrBursts::10 5991 # Per bank write bursts -system.physmem.perBankWrBursts::11 6522 # Per bank write bursts -system.physmem.perBankWrBursts::12 6386 # Per bank write bursts -system.physmem.perBankWrBursts::13 6332 # Per bank write bursts -system.physmem.perBankWrBursts::14 6056 # Per bank write bursts -system.physmem.perBankWrBursts::15 6134 # Per bank write bursts +system.physmem.perBankWrBursts::9 5907 # Per bank write bursts +system.physmem.perBankWrBursts::10 5994 # Per bank write bursts +system.physmem.perBankWrBursts::11 6518 # Per bank write bursts +system.physmem.perBankWrBursts::12 6370 # Per bank write bursts +system.physmem.perBankWrBursts::13 6328 # Per bank write bursts +system.physmem.perBankWrBursts::14 6055 # Per bank write bursts +system.physmem.perBankWrBursts::15 6145 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 202723740000 # Total gap between requests +system.physmem.totGap 202741873000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 148203 # Read request sizes (log2) +system.physmem.readPktSize::6 148209 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97674 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 506 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97655 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 497 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -127,177 +127,175 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4474 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4429 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 4430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69255 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 227.128612 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 137.881961 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.200091 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 32064 46.30% 46.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 12862 18.57% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 5392 7.79% 72.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 3385 4.89% 77.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2324 3.36% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 2409 3.48% 84.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 3469 5.01% 89.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1945 2.81% 92.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 863 1.25% 93.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 531 0.77% 94.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 437 0.63% 94.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 323 0.47% 95.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 295 0.43% 95.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 249 0.36% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 196 0.28% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 174 0.25% 96.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 149 0.22% 96.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 143 0.21% 97.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 144 0.21% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 117 0.17% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 151 0.22% 97.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 829 1.20% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 98 0.14% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 133 0.19% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 72 0.10% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 116 0.17% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 42 0.06% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 50 0.07% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 21 0.03% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 33 0.05% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 14 0.02% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 14 0.02% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 13 0.02% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 19 0.03% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 5 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 13 0.02% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 5 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 10 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 5 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 12 0.02% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 4 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 4 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 10 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 6 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 4 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 2 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 4 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 4 0.01% 99.87% # Bytes accessed per row activation +system.physmem.wrQLenPdf::12 4433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 69195 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 227.306135 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.834913 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.898236 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 32130 46.43% 46.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 12720 18.38% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5417 7.83% 72.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 3376 4.88% 77.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2339 3.38% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2370 3.43% 84.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 3454 4.99% 89.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1959 2.83% 92.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 832 1.20% 93.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 575 0.83% 94.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 433 0.63% 94.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 375 0.54% 95.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 263 0.38% 95.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 260 0.38% 96.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 191 0.28% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 161 0.23% 96.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 162 0.23% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 137 0.20% 97.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 140 0.20% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 141 0.20% 97.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 135 0.20% 97.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 814 1.18% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 112 0.16% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 126 0.18% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 73 0.11% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 92 0.13% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 41 0.06% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 66 0.10% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 25 0.04% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 31 0.04% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 22 0.03% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 18 0.03% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 8 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 15 0.02% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 8 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 14 0.02% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 7 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 4 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 8 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 5 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 9 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 2 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 7 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 9 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 5 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 3 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 3 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 4 0.01% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::3136 2 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 5 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 1 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 3 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 5 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 2 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 4 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 6 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 3 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 4 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 3 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 4 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 2 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::3648 3 0.00% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::3712 3 0.00% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::3776 3 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840 1 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::3904 2 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::3968 1 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 2 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 1 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 2 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288 3 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 1 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416 2 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032 2 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 3 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 1 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288 1 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 1 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416 4 0.01% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::4480 3 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544 2 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544 3 0.00% 99.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::4608 1 0.00% 99.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::4672 2 0.00% 99.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::4736 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 4 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864 5 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928 6 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 7 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184 4 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69255 # Bytes accessed per row activation -system.physmem.totQLat 1733533250 # Total ticks spent queuing -system.physmem.totMemAccLat 4938490750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 740600000 # Total ticks spent in databus transfers -system.physmem.totBankLat 2464357500 # Total ticks spent accessing banks -system.physmem.avgQLat 11703.57 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 16637.57 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::4800 2 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864 4 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928 5 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 9 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 5 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 5 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69195 # Bytes accessed per row activation +system.physmem.totQLat 1735354000 # Total ticks spent queuing +system.physmem.totMemAccLat 4939796500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 740580000 # Total ticks spent in databus transfers +system.physmem.totBankLat 2463862500 # Total ticks spent accessing banks +system.physmem.avgQLat 11716.18 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16634.68 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33341.15 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 33350.86 # Average memory access latency per DRAM burst system.physmem.avgRdBW 46.76 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 30.83 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 46.79 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 30.84 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 30.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 8.34 # Average write queue length when enqueuing -system.physmem.readRowHits 118615 # Number of row buffer hits during reads -system.physmem.writeRowHits 57916 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.30 # Row buffer hit rate for writes -system.physmem.avgGap 824492.49 # Average gap between requests -system.physmem.pageHitRate 71.82 # Row buffer hit rate, read and write combined +system.physmem.avgWrQLen 7.69 # Average write queue length when enqueuing +system.physmem.readRowHits 118629 # Number of row buffer hits during reads +system.physmem.writeRowHits 57942 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.33 # Row buffer hit rate for writes +system.physmem.avgGap 824609.84 # Average gap between requests +system.physmem.pageHitRate 71.84 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 4.57 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 77623185 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46911 # Transaction distribution -system.membus.trans_dist::ReadResp 46910 # Transaction distribution -system.membus.trans_dist::Writeback 97674 # Transaction distribution -system.membus.trans_dist::UpgradeReq 11 # Transaction distribution -system.membus.trans_dist::UpgradeResp 11 # Transaction distribution -system.membus.trans_dist::ReadExReq 101292 # Transaction distribution -system.membus.trans_dist::ReadExResp 101292 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394101 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 394101 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15736064 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15736064 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15736064 # Total data (bytes) +system.membus.throughput 77612139 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46927 # Transaction distribution +system.membus.trans_dist::ReadResp 46926 # Transaction distribution +system.membus.trans_dist::Writeback 97655 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9 # Transaction distribution +system.membus.trans_dist::UpgradeResp 9 # Transaction distribution +system.membus.trans_dist::ReadExReq 101282 # Transaction distribution +system.membus.trans_dist::ReadExResp 101282 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394090 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 394090 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15735232 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15735232 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15735232 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1083877500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1083331500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1398233989 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1398080741 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.branchPred.lookups 182800422 # Number of BP lookups -system.cpu.branchPred.condPredicted 143125984 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7265649 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93161641 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87212337 # Number of BTB hits +system.cpu.branchPred.lookups 182821881 # Number of BP lookups +system.cpu.branchPred.condPredicted 143128941 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7267602 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 93256153 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87224937 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.613998 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12679601 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 116070 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.532635 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12680294 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 116110 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -341,99 +339,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 405447521 # number of cpu cycles simulated +system.cpu.numCycles 405483787 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119380246 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761599809 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182800422 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99891938 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170150193 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35686156 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 77536501 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 421 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 4 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114531553 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2441596 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 394683462 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.164182 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.986578 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 119392397 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761626089 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182821881 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99905231 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170161499 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35693540 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 77526610 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 504 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 114544332 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2440974 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 394703108 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.164266 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.986626 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 224545887 56.89% 56.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14186952 3.59% 60.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22897432 5.80% 66.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22746092 5.76% 72.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20901340 5.30% 77.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11597179 2.94% 80.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13058524 3.31% 83.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11996237 3.04% 86.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52753819 13.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 224554253 56.89% 56.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14186197 3.59% 60.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22894091 5.80% 66.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22752137 5.76% 72.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20903206 5.30% 77.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11599444 2.94% 80.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13055661 3.31% 83.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11997295 3.04% 86.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52760824 13.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 394683462 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.450861 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.878418 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129072579 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 73027799 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158814938 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6226113 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27542033 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26114312 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76721 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825530013 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 296611 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27542033 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135666789 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10114135 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 47882735 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158263751 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15214019 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800585655 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1326 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3054919 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8955576 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 319 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954278962 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3500427685 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3241978538 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 394703108 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.450873 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.878315 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129083805 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 73018474 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158832056 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6220794 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27547979 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26129340 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76785 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825608835 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 295228 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27547979 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135679690 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10121289 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 47881687 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158273998 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15198465 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800668964 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1330 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3052101 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8945812 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 362 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954340537 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3500811550 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3242323485 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 408 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288026671 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2292807 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2292805 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41836607 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170271933 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73467321 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28611863 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15824348 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755053032 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775163 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665355613 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1381173 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187369401 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479711265 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797531 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 394683462 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.685796 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.734889 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 288088246 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2292986 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2292983 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41809416 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170279668 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73490979 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28628515 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15917734 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 755112059 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775370 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665341342 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1376386 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187422324 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 480057823 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797738 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 394703108 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.685675 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.734980 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 139155313 35.26% 35.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69944135 17.72% 52.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71513404 18.12% 71.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53413889 13.53% 84.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31153204 7.89% 92.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16018566 4.06% 96.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8773221 2.22% 98.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2895809 0.73% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1815921 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 139172579 35.26% 35.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69945530 17.72% 52.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71553354 18.13% 71.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53346113 13.52% 84.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31223827 7.91% 92.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15970746 4.05% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8755651 2.22% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2914643 0.74% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1820665 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 394683462 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 394703108 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 480741 5.03% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 482503 5.03% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available @@ -462,15 +460,15 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6525777 68.24% 73.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2556117 26.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6534303 68.16% 73.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2570451 26.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447788521 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383312 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447795067 67.30% 67.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383509 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 92 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued @@ -496,84 +494,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153398604 23.06% 90.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63785079 9.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153388869 23.05% 90.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63773802 9.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665355613 # Type of FU issued -system.cpu.iq.rate 1.641040 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9562635 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014372 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1736338273 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 947004281 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646070374 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 665341342 # Type of FU issued +system.cpu.iq.rate 1.640858 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9587257 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014410 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1736349214 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 947116147 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 646066392 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 674918135 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8557309 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 674928488 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 111 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8549509 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44242378 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 41636 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810625 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16606844 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44250113 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 41242 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810436 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16630502 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19503 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8485 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19512 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8119 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27542033 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5268504 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 386055 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760387350 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1120402 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170271933 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73467321 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286621 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 219781 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12300 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810625 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4335480 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4005038 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8340518 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655927300 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150116406 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9428313 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27547979 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5274488 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 385382 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760446348 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1122317 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170279668 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73490979 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286828 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 220043 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12119 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810436 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4337792 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4003940 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8341732 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655918178 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150108041 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9423164 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1559155 # number of nop insts executed -system.cpu.iew.exec_refs 212603914 # number of memory reference insts executed -system.cpu.iew.exec_branches 138495848 # Number of branches executed -system.cpu.iew.exec_stores 62487508 # Number of stores executed -system.cpu.iew.exec_rate 1.617786 # Inst execution rate -system.cpu.iew.wb_sent 651044212 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646070390 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374730881 # num instructions producing a value -system.cpu.iew.wb_consumers 646348309 # num instructions consuming a value +system.cpu.iew.exec_nop 1558919 # number of nop insts executed +system.cpu.iew.exec_refs 212583502 # number of memory reference insts executed +system.cpu.iew.exec_branches 138505177 # Number of branches executed +system.cpu.iew.exec_stores 62475461 # Number of stores executed +system.cpu.iew.exec_rate 1.617619 # Inst execution rate +system.cpu.iew.wb_sent 651039816 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 646066408 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374710129 # num instructions producing a value +system.cpu.iew.wb_consumers 646296052 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.593475 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579766 # average fanout of values written-back +system.cpu.iew.wb_rate 1.593322 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579781 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189447861 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189507119 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7191623 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 367141429 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.555172 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.229944 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7193544 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 367155129 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.555114 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.230192 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 159432399 43.43% 43.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98512068 26.83% 70.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33823975 9.21% 79.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18780022 5.12% 84.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16190351 4.41% 89.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7453107 2.03% 91.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6987048 1.90% 92.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3180816 0.87% 93.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22781643 6.21% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 159449671 43.43% 43.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98535661 26.84% 70.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33805643 9.21% 79.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18779260 5.11% 84.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16179301 4.41% 88.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7452481 2.03% 91.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6962529 1.90% 92.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3196007 0.87% 93.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22794576 6.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 367141429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 367155129 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -584,225 +582,221 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22781643 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22794576 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1104768676 # The number of ROB reads -system.cpu.rob.rob_writes 1548495185 # The number of ROB writes -system.cpu.timesIdled 328850 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10764059 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1104828701 # The number of ROB reads +system.cpu.rob.rob_writes 1548619548 # The number of ROB writes +system.cpu.timesIdled 328708 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10780679 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.802489 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.802489 # CPI: Total CPI of All Threads -system.cpu.ipc 1.246124 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.246124 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3058844384 # number of integer regfile reads -system.cpu.int_regfile_writes 752016829 # number of integer regfile writes +system.cpu.cpi 0.802560 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.802560 # CPI: Total CPI of All Threads +system.cpu.ipc 1.246012 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.246012 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3058777476 # number of integer regfile reads +system.cpu.int_regfile_writes 752019512 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 210849022 # number of misc regfile reads +system.cpu.misc_regfile_reads 210833742 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.throughput 734005013 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 865051 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 865050 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1111085 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 84 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 84 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 348869 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 348869 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33932 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3505059 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3538991 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1082560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147711232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148793792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148793792 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 6464 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2273629999 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 733860762 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 864901 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 864900 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1110997 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 65 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 65 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 348858 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 348858 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33792 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504779 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3538571 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1078976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147700672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148779648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148779648 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 4672 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2273407999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 26093735 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 25965233 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1824375488 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1824278730 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 15073 # number of replacements -system.cpu.icache.tags.tagsinuse 1099.985685 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 114510320 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16932 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6762.952988 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 15017 # number of replacements +system.cpu.icache.tags.tagsinuse 1095.413038 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 114523215 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16866 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6790.182319 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1099.985685 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.537102 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.537102 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114510320 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114510320 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114510320 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114510320 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114510320 # number of overall hits -system.cpu.icache.overall_hits::total 114510320 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21232 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21232 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21232 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21232 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21232 # number of overall misses -system.cpu.icache.overall_misses::total 21232 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 575292732 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 575292732 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 575292732 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 575292732 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 575292732 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 575292732 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114531552 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114531552 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114531552 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114531552 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114531552 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114531552 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000185 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000185 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000185 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000185 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000185 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000185 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27095.550678 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27095.550678 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27095.550678 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27095.550678 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27095.550678 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27095.550678 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 860 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1095.413038 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.534870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.534870 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114523215 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114523215 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114523215 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114523215 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114523215 # number of overall hits +system.cpu.icache.overall_hits::total 114523215 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21116 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21116 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21116 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21116 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21116 # number of overall misses +system.cpu.icache.overall_misses::total 21116 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 569003980 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 569003980 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 569003980 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 569003980 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 569003980 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 569003980 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114544331 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114544331 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114544331 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114544331 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114544331 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114544331 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26946.579845 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 26946.579845 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 26946.579845 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 26946.579845 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 26946.579845 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 26946.579845 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1001 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 71.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 91 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4215 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4215 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4215 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4215 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4215 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4215 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17017 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 17017 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 17017 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 17017 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 17017 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 17017 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 416333765 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 416333765 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 416333765 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 416333765 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 416333765 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 416333765 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000149 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000149 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000149 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24465.755715 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24465.755715 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24465.755715 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24465.755715 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24465.755715 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24465.755715 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4183 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4183 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4183 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4183 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4183 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4183 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16933 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16933 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16933 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16933 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16933 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16933 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 412315016 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 412315016 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 412315016 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 412315016 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 412315016 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 412315016 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24349.791295 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24349.791295 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24349.791295 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24349.791295 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24349.791295 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24349.791295 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 115458 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27089.677773 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1781255 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 146702 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.141995 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 102544951000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23009.492156 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 363.276336 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3716.909282 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.702194 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011086 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.113431 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.826711 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 13516 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 804499 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 818015 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1111085 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1111085 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 74 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 74 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 247576 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 247576 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 13516 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1052075 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1065591 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 13516 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1052075 # number of overall hits -system.cpu.l2cache.overall_hits::total 1065591 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3400 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 43535 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 46935 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 101293 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 101293 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3400 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 144828 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 148228 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3400 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 144828 # number of overall misses -system.cpu.l2cache.overall_misses::total 148228 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 263796250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3483365500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3747161750 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22999 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 22999 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7556144249 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7556144249 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 263796250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11039509749 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11303305999 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 263796250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11039509749 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11303305999 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 16916 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 848034 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 864950 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1111085 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1111085 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 84 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 84 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 348869 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 348869 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 16916 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1196903 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1213819 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 16916 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1196903 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1213819 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200993 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051336 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.054263 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.119048 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.119048 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290347 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.290347 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200993 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.121002 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.122117 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200993 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.121002 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.122117 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77587.132353 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80012.989549 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79837.258975 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2299.900000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2299.900000 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74596.904515 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74596.904515 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77587.132353 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76224.968577 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76256.213394 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77587.132353 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76224.968577 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76256.213394 # average overall miss latency +system.cpu.l2cache.tags.replacements 115463 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27089.747444 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1781862 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 146718 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.144808 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 102535173000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23009.564484 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 360.930795 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3719.252164 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.702196 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011015 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.113503 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.826713 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 13491 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 804384 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 817875 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1110997 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1110997 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 57 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 57 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 247575 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 247575 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 13491 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1051959 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1065450 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 13491 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1051959 # number of overall hits +system.cpu.l2cache.overall_hits::total 1065450 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3369 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 43584 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 46953 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 8 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 8 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 101283 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 101283 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3369 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 144867 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 148236 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3369 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 144867 # number of overall misses +system.cpu.l2cache.overall_misses::total 148236 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 260130750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3496707000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3756837750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7547454999 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7547454999 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 260130750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11044161999 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11304292749 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 260130750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11044161999 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11304292749 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 16860 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 847968 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 864828 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1110997 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1110997 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 65 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 65 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 348858 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 348858 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 16860 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1196826 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1213686 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 16860 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1196826 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1213686 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.199822 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051398 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.054292 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.123077 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.123077 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290327 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.290327 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199822 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.121043 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.122137 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199822 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.121043 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.122137 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77213.045414 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80229.143722 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80012.730816 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74518.477918 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74518.477918 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77213.045414 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76236.561805 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76258.754614 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77213.045414 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76236.561805 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76258.754614 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -811,195 +805,195 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 97674 # number of writebacks -system.cpu.l2cache.writebacks::total 97674 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 97655 # number of writebacks +system.cpu.l2cache.writebacks::total 97655 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 19 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 19 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 19 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3395 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43516 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 46911 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101293 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 101293 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3395 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 144809 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 148204 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3395 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 144809 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 148204 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 220586000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2937177750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3157763750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 100010 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 100010 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6271255251 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6271255251 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 220586000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9208433001 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9429019001 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 220586000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9208433001 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9429019001 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051314 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054236 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.119048 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.119048 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290347 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290347 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120986 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.122097 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120986 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.122097 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64973.784978 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67496.501287 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67313.929569 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3364 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43563 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 46927 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101283 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101283 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3364 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 144846 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 148210 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3364 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 144846 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 148210 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 217499500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2949813250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3167312750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 80008 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 80008 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6262853501 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6262853501 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 217499500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9212666751 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9430166251 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 217499500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9212666751 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9430166251 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.199526 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051373 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054262 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.123077 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.123077 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290327 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290327 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199526 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121025 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.122116 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199526 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121025 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.122116 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64655.023781 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67713.730689 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67494.464807 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61912.029963 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61912.029963 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64973.784978 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63590.198130 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63621.892803 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64973.784978 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63590.198130 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63621.892803 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61835.189528 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61835.189528 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64655.023781 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63603.183733 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63627.057898 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64655.023781 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63603.183733 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63627.057898 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1192807 # number of replacements -system.cpu.dcache.tags.tagsinuse 4057.511512 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 190198729 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1196903 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 158.909059 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1192730 # number of replacements +system.cpu.dcache.tags.tagsinuse 4057.514955 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 190201285 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1196826 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 158.921418 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4256684250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4057.511512 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.990603 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.990603 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 136233368 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136233368 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50987745 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50987745 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488823 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488823 # number of LoadLockedReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 4057.514955 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.990604 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.990604 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 136235473 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136235473 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50988251 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50988251 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488825 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488825 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187221113 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187221113 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187221113 # number of overall hits -system.cpu.dcache.overall_hits::total 187221113 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1703411 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1703411 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3251561 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3251561 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 36 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 36 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4954972 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4954972 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4954972 # number of overall misses -system.cpu.dcache.overall_misses::total 4954972 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29743018227 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29743018227 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 72512845225 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 72512845225 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 596500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 596500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102255863452 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102255863452 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102255863452 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102255863452 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137936779 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137936779 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 187223724 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187223724 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187223724 # number of overall hits +system.cpu.dcache.overall_hits::total 187223724 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1700874 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1700874 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3251055 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3251055 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 37 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 37 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 4951929 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4951929 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4951929 # number of overall misses +system.cpu.dcache.overall_misses::total 4951929 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29724371713 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29724371713 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 72455016224 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 72455016224 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 609500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 609500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102179387937 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102179387937 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102179387937 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102179387937 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137936347 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137936347 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488859 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488859 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488862 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488862 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192176085 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192176085 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192176085 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192176085 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012349 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012349 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059948 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059948 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025783 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025783 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025783 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025783 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17460.858376 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17460.858376 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22300.933375 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 22300.933375 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16569.444444 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16569.444444 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20637.021451 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20637.021451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20637.021451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20637.021451 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 18554 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 53547 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1675 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 192175653 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192175653 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192175653 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192175653 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012331 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012331 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059939 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059939 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000025 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000025 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025768 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025768 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025768 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025768 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17475.939848 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17475.939848 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22286.616567 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 22286.616567 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16472.972973 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16472.972973 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20634.259485 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20634.259485 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20634.259485 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20634.259485 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 16723 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 52602 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1619 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.077015 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 81.009077 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.329216 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 79.579425 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1111085 # number of writebacks -system.cpu.dcache.writebacks::total 1111085 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 854833 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 854833 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2903152 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2903152 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 36 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 36 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3757985 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3757985 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3757985 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3757985 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848578 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848578 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348409 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348409 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196987 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196987 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196987 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196987 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12415172523 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12415172523 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10430126485 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10430126485 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22845299008 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22845299008 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22845299008 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22845299008 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1110997 # number of writebacks +system.cpu.dcache.writebacks::total 1110997 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 852356 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 852356 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902682 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2902682 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3755038 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3755038 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3755038 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3755038 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848518 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848518 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348373 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348373 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196891 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196891 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196891 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196891 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12427221029 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12427221029 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10421112237 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10421112237 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22848333266 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22848333266 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22848333266 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22848333266 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006424 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14630.561390 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14630.561390 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29936.443906 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29936.443906 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19085.670110 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19085.670110 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19085.670110 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19085.670110 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14645.795409 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14645.795409 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29913.662187 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29913.662187 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19089.736046 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19089.736046 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19089.736046 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19089.736046 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 60a82514d..6c434f44b 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -125,6 +131,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.branchPred] type=BranchPredictor @@ -133,6 +140,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -148,6 +156,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -170,18 +179,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[3] @@ -190,15 +202,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -207,16 +222,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -225,22 +243,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -249,22 +271,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -273,10 +299,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -285,124 +313,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -411,10 +460,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -423,16 +474,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -441,10 +495,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -455,6 +511,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -477,12 +534,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -493,16 +552,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[2] @@ -513,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -535,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -550,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -559,9 +625,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -573,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -597,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -608,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 09ddfe08f..d5a6aea3b 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.459344 # Number of seconds simulated -sim_ticks 459344378000 # Number of ticks simulated -final_tick 459344378000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.459341 # Number of seconds simulated +sim_ticks 459340600000 # Number of ticks simulated +final_tick 459340600000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 78845 # Simulator instruction rate (inst/s) -host_op_rate 145792 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43799497 # Simulator tick rate (ticks/s) -host_mem_usage 371908 # Number of bytes of host memory used -host_seconds 10487.44 # Real time elapsed on the host +host_inst_rate 64463 # Simulator instruction rate (inst/s) +host_op_rate 119200 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35810129 # Simulator tick rate (ticks/s) +host_mem_usage 391936 # Number of bytes of host memory used +host_seconds 12827.11 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 201792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24475712 # Number of bytes read from this memory -system.physmem.bytes_read::total 24677504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 201792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 201792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18789056 # Number of bytes written to this memory -system.physmem.bytes_written::total 18789056 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3153 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382433 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385586 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293579 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293579 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 439304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53284013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53723318 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 439304 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 439304 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 40904073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 40904073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 40904073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 439304 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53284013 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 94627391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385586 # Number of read requests accepted -system.physmem.writeReqs 293579 # Number of write requests accepted -system.physmem.readBursts 385586 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 293579 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24668096 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue -system.physmem.bytesWritten 18787968 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24677504 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18789056 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 203008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24478016 # Number of bytes read from this memory +system.physmem.bytes_read::total 24681024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 203008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 203008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18788608 # Number of bytes written to this memory +system.physmem.bytes_written::total 18788608 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3172 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382469 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385641 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293572 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293572 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 441955 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53289468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53731423 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 441955 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 441955 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 40903434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 40903434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 40903434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 441955 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53289468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 94634857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385641 # Number of read requests accepted +system.physmem.writeReqs 293572 # Number of write requests accepted +system.physmem.readBursts 385641 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 293572 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24669632 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11392 # Total number of bytes read from write queue +system.physmem.bytesWritten 18788480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24681024 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18788608 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 178 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 137816 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24063 # Per bank write bursts -system.physmem.perBankRdBursts::1 26414 # Per bank write bursts -system.physmem.perBankRdBursts::2 24662 # Per bank write bursts -system.physmem.perBankRdBursts::3 24515 # Per bank write bursts -system.physmem.perBankRdBursts::4 23241 # Per bank write bursts -system.physmem.perBankRdBursts::5 23653 # Per bank write bursts -system.physmem.perBankRdBursts::6 24406 # Per bank write bursts -system.physmem.perBankRdBursts::7 24209 # Per bank write bursts -system.physmem.perBankRdBursts::8 23620 # Per bank write bursts -system.physmem.perBankRdBursts::9 23822 # Per bank write bursts -system.physmem.perBankRdBursts::10 24803 # Per bank write bursts -system.physmem.perBankRdBursts::11 24074 # Per bank write bursts -system.physmem.perBankRdBursts::12 23251 # Per bank write bursts -system.physmem.perBankRdBursts::13 22944 # Per bank write bursts -system.physmem.perBankRdBursts::14 23767 # Per bank write bursts -system.physmem.perBankRdBursts::15 23995 # Per bank write bursts -system.physmem.perBankWrBursts::0 18528 # Per bank write bursts -system.physmem.perBankWrBursts::1 19811 # Per bank write bursts -system.physmem.perBankWrBursts::2 18936 # Per bank write bursts -system.physmem.perBankWrBursts::3 18914 # Per bank write bursts -system.physmem.perBankWrBursts::4 18031 # Per bank write bursts -system.physmem.perBankWrBursts::5 18401 # Per bank write bursts -system.physmem.perBankWrBursts::6 18972 # Per bank write bursts -system.physmem.perBankWrBursts::7 18946 # Per bank write bursts -system.physmem.perBankWrBursts::8 18539 # Per bank write bursts -system.physmem.perBankWrBursts::9 18111 # Per bank write bursts -system.physmem.perBankWrBursts::10 18827 # Per bank write bursts -system.physmem.perBankWrBursts::11 17725 # Per bank write bursts -system.physmem.perBankWrBursts::12 17351 # Per bank write bursts -system.physmem.perBankWrBursts::13 16948 # Per bank write bursts -system.physmem.perBankWrBursts::14 17708 # Per bank write bursts -system.physmem.perBankWrBursts::15 17814 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 135253 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24057 # Per bank write bursts +system.physmem.perBankRdBursts::1 26446 # Per bank write bursts +system.physmem.perBankRdBursts::2 24658 # Per bank write bursts +system.physmem.perBankRdBursts::3 24494 # Per bank write bursts +system.physmem.perBankRdBursts::4 23239 # Per bank write bursts +system.physmem.perBankRdBursts::5 23672 # Per bank write bursts +system.physmem.perBankRdBursts::6 24412 # Per bank write bursts +system.physmem.perBankRdBursts::7 24201 # Per bank write bursts +system.physmem.perBankRdBursts::8 23613 # Per bank write bursts +system.physmem.perBankRdBursts::9 23828 # Per bank write bursts +system.physmem.perBankRdBursts::10 24822 # Per bank write bursts +system.physmem.perBankRdBursts::11 24051 # Per bank write bursts +system.physmem.perBankRdBursts::12 23218 # Per bank write bursts +system.physmem.perBankRdBursts::13 22963 # Per bank write bursts +system.physmem.perBankRdBursts::14 23780 # Per bank write bursts +system.physmem.perBankRdBursts::15 24009 # Per bank write bursts +system.physmem.perBankWrBursts::0 18526 # Per bank write bursts +system.physmem.perBankWrBursts::1 19824 # Per bank write bursts +system.physmem.perBankWrBursts::2 18930 # Per bank write bursts +system.physmem.perBankWrBursts::3 18895 # Per bank write bursts +system.physmem.perBankWrBursts::4 18030 # Per bank write bursts +system.physmem.perBankWrBursts::5 18409 # Per bank write bursts +system.physmem.perBankWrBursts::6 18982 # Per bank write bursts +system.physmem.perBankWrBursts::7 18942 # Per bank write bursts +system.physmem.perBankWrBursts::8 18537 # Per bank write bursts +system.physmem.perBankWrBursts::9 18120 # Per bank write bursts +system.physmem.perBankWrBursts::10 18829 # Per bank write bursts +system.physmem.perBankWrBursts::11 17702 # Per bank write bursts +system.physmem.perBankWrBursts::12 17342 # Per bank write bursts +system.physmem.perBankWrBursts::13 16954 # Per bank write bursts +system.physmem.perBankWrBursts::14 17718 # Per bank write bursts +system.physmem.perBankWrBursts::15 17830 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 459344352000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 459340574000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 385586 # Read request sizes (log2) +system.physmem.readPktSize::6 385641 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 293579 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380798 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4331 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293572 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 380895 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -128,323 +128,323 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 13203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 13287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 13314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 13327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 13328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 13289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 13319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 13330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 13323 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 13318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 13383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 13355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 13385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 13360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 13377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 13325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 13360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 13383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 13353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 13317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 13304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 13319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 13344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 13297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 13513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 13303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 13380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 13367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 13383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 13400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 13420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 13351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 13361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 13365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 13348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 13319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 13314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 13314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 13324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 13314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 13479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 13297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 25 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147608 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 294.394450 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 155.776614 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 442.926634 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 63757 43.19% 43.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 27975 18.95% 62.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 12431 8.42% 70.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 7117 4.82% 75.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 4833 3.27% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3554 2.41% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 2743 1.86% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2234 1.51% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 1986 1.35% 85.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 1585 1.07% 86.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1916 1.30% 88.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1217 0.82% 88.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 1133 0.77% 89.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 1065 0.72% 90.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 945 0.64% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 876 0.59% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 1005 0.68% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1152 0.78% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 1143 0.77% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 849 0.58% 94.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 811 0.55% 95.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 5222 3.54% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 320 0.22% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 205 0.14% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 175 0.12% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 129 0.09% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 96 0.07% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 103 0.07% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 90 0.06% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 59 0.04% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 49 0.03% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 46 0.03% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 39 0.03% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 37 0.03% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 41 0.03% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 25 0.02% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 33 0.02% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 21 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 11 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 24 0.02% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 23 0.02% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 26 0.02% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 13 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 15 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 22 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 19 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 16 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 16 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136 15 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 11 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 21 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 9 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 16 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 10 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 11 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 14 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648 17 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712 17 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776 11 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840 7 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904 10 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968 9 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032 7 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 6 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 12 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 24 0.02% 99.88% # Bytes accessed per row activation +system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 147621 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 294.388468 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 155.710774 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 443.499186 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 63823 43.23% 43.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 27954 18.94% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 12395 8.40% 70.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 7134 4.83% 75.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 4845 3.28% 78.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3604 2.44% 81.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2701 1.83% 82.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2191 1.48% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1897 1.29% 85.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1561 1.06% 86.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2008 1.36% 88.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1215 0.82% 88.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1176 0.80% 89.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1069 0.72% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 885 0.60% 91.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 912 0.62% 91.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 1043 0.71% 92.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1161 0.79% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1134 0.77% 93.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 871 0.59% 94.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 771 0.52% 95.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 5235 3.55% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 297 0.20% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 223 0.15% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 174 0.12% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 140 0.09% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 99 0.07% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 107 0.07% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 67 0.05% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 49 0.03% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 50 0.03% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 49 0.03% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 40 0.03% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 28 0.02% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 31 0.02% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 21 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 22 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 31 0.02% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 30 0.02% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 18 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 24 0.02% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 16 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 18 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 20 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 17 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 18 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 17 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 21 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136 13 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 13 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 16 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 15 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 9 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 14 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 12 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 17 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648 16 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712 8 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776 10 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840 9 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904 11 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968 6 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032 17 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 7 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 17 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 18 0.01% 99.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::4288 37 0.03% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 2 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544 1 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608 9 0.01% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672 5 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736 3 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 3 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864 4 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544 5 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608 4 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672 3 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736 4 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800 1 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864 3 0.00% 99.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::4928 5 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 3 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 3 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 3 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 2 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 8 0.01% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 4 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::5184 3 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248 6 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312 5 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376 4 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440 3 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504 8 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248 3 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312 6 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376 3 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440 5 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504 5 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::5568 4 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632 3 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696 2 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888 3 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952 8 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016 10 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696 4 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824 2 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888 6 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952 3 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016 14 0.01% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::6080 3 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144 3 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272 18 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::6336 3 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::6528 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147608 # Bytes accessed per row activation -system.physmem.totQLat 3829490000 # Total ticks spent queuing -system.physmem.totMemAccLat 12088876250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1927195000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6332191250 # Total ticks spent accessing banks -system.physmem.avgQLat 9935.40 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 16428.52 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::7552 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147621 # Bytes accessed per row activation +system.physmem.totQLat 3824316500 # Total ticks spent queuing +system.physmem.totMemAccLat 12085472750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1927315000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6333841250 # Total ticks spent accessing banks +system.physmem.avgQLat 9921.36 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16431.77 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31363.92 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 53.70 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31353.13 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 53.71 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 40.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 53.72 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 53.73 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 40.90 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.74 # Data bus utilization in percentage system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.32 # Average write queue length when enqueuing -system.physmem.readRowHits 326974 # Number of row buffer hits during reads +system.physmem.avgWrQLen 9.23 # Average write queue length when enqueuing +system.physmem.readRowHits 326993 # Number of row buffer hits during reads system.physmem.writeRowHits 204419 # Number of row buffer hits during writes system.physmem.readRowHitRate 84.83 # Row buffer hit rate for reads system.physmem.writeRowHitRate 69.63 # Row buffer hit rate for writes -system.physmem.avgGap 676336.90 # Average gap between requests +system.physmem.avgGap 676283.54 # Average gap between requests system.physmem.pageHitRate 78.26 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 5.85 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 94627391 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 178768 # Transaction distribution -system.membus.trans_dist::ReadResp 178768 # Transaction distribution -system.membus.trans_dist::Writeback 293579 # Transaction distribution -system.membus.trans_dist::UpgradeReq 137816 # Transaction distribution -system.membus.trans_dist::UpgradeResp 137816 # Transaction distribution -system.membus.trans_dist::ReadExReq 206818 # Transaction distribution -system.membus.trans_dist::ReadExResp 206818 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1340383 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1340383 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1340383 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43466560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43466560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43466560 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43466560 # Total data (bytes) +system.membus.throughput 94634857 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 178796 # Transaction distribution +system.membus.trans_dist::ReadResp 178796 # Transaction distribution +system.membus.trans_dist::Writeback 293572 # Transaction distribution +system.membus.trans_dist::UpgradeReq 135253 # Transaction distribution +system.membus.trans_dist::UpgradeResp 135253 # Transaction distribution +system.membus.trans_dist::ReadExReq 206845 # Transaction distribution +system.membus.trans_dist::ReadExResp 206845 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1335360 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1335360 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1335360 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43469632 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43469632 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43469632 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43469632 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3394511250 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3391724500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3904983950 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.branchPred.lookups 205617659 # Number of BP lookups -system.cpu.branchPred.condPredicted 205617659 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9903777 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 117094014 # Number of BTB lookups -system.cpu.branchPred.BTBHits 114674529 # Number of BTB hits +system.membus.respLayer1.occupancy 3901051256 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.8 # Layer utilization (%) +system.cpu.branchPred.lookups 205617807 # Number of BP lookups +system.cpu.branchPred.condPredicted 205617807 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9908418 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 117215133 # Number of BTB lookups +system.cpu.branchPred.BTBHits 114724662 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.933724 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25071350 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1805580 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.875299 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25059559 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1805276 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 918847215 # number of cpu cycles simulated +system.cpu.numCycles 918840117 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 167424119 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1131762166 # Number of instructions fetch has processed -system.cpu.fetch.Branches 205617659 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 139745879 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 352279607 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 71096448 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 305445808 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 47309 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 248301 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 162018331 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2527029 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 886385524 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.375664 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.323603 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 167454161 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1131890109 # Number of instructions fetch has processed +system.cpu.fetch.Branches 205617807 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 139784221 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 352321921 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 71123589 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 305412308 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 47848 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 248697 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 162055223 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2523762 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 886447009 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.375660 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.323512 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 538173800 60.72% 60.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23402088 2.64% 63.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25255439 2.85% 66.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27875375 3.14% 69.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 17753006 2.00% 71.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 22920695 2.59% 73.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 29402684 3.32% 77.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 26636320 3.01% 80.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174966117 19.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 538196407 60.71% 60.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23398337 2.64% 63.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25267875 2.85% 66.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27893164 3.15% 69.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 17745237 2.00% 71.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 22915160 2.59% 73.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 29437572 3.32% 77.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 26645476 3.01% 80.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174947781 19.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 886385524 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.223778 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.231720 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 222535838 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 260614631 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 295382827 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 46911879 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 60940349 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2071401768 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 60940349 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 256088737 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 115827091 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17786 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 306634612 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 146876949 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2035245404 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 18048 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25034239 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 106622478 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2138089384 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5150744592 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3273505517 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 42043 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 886447009 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.223780 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.231868 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 222604172 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 260544811 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 295377211 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 46958792 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 60962023 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2071584997 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 60962023 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 256124443 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 115849529 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 18111 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 306710232 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 146782671 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2035392094 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19900 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 24933273 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 106586441 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2138335278 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5151319538 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3273897775 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 39701 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 524048530 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1277 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1209 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 346982000 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 495887036 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194435860 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 195573190 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 54925274 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1975493038 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13839 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1772240867 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 484864 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 441634059 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 734815554 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13287 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 886385524 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.999402 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.882776 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 524294424 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1242 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1171 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 346564705 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 495938130 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 194456766 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 195343621 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 54992684 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1975627132 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 13244 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1772183771 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 484863 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 441729805 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 735457697 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 12692 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 886447009 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.999199 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.882883 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 269512858 30.41% 30.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151842775 17.13% 47.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 137668751 15.53% 63.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131788792 14.87% 77.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91572274 10.33% 88.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 55974345 6.31% 94.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34415050 3.88% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11842339 1.34% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1768340 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 269548828 30.41% 30.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 152175288 17.17% 47.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 137113127 15.47% 63.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 132050060 14.90% 77.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91550725 10.33% 88.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 55998430 6.32% 94.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34403840 3.88% 98.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11839729 1.34% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1766982 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 886385524 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 886447009 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4916629 32.41% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7656958 50.48% 82.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2596197 17.11% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4936288 32.45% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7665302 50.39% 82.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2609145 17.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2627446 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1165802431 65.78% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 352933 0.02% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880848 0.22% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2622898 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1165798232 65.78% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 353842 0.02% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880856 0.22% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued @@ -471,84 +471,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 429321200 24.22% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170256004 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 429305841 24.22% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170222097 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1772240867 # Type of FU issued -system.cpu.iq.rate 1.928766 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15169784 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008560 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4446506063 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2417344315 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1744979494 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15843 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 54000 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3681 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1784775700 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7505 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 172548732 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1772183771 # Type of FU issued +system.cpu.iq.rate 1.928718 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15210735 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008583 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4446495646 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2417577635 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1744952561 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 14503 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 50594 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3428 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1784764794 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 6814 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 172654482 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 111785908 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 387968 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 329381 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45275674 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 111836934 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 389891 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 330016 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45296580 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 14622 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 560 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 14646 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 570 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 60940349 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 68092505 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7152437 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1975506877 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 797637 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 495888065 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 194435860 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3411 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4450354 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 83339 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 329381 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5904947 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4426658 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10331605 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1753082670 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 424162697 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19158197 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 60962023 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 68066484 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7196875 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1975640376 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 789853 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 495939091 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 194456766 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3282 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4474777 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 82775 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 330016 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5907886 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4422310 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10330196 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1753064930 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 424170565 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19118841 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590975772 # number of memory reference insts executed -system.cpu.iew.exec_branches 167493044 # Number of branches executed -system.cpu.iew.exec_stores 166813075 # Number of stores executed -system.cpu.iew.exec_rate 1.907915 # Inst execution rate -system.cpu.iew.wb_sent 1749835931 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1744983175 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1325071563 # num instructions producing a value -system.cpu.iew.wb_consumers 1945952606 # num instructions consuming a value +system.cpu.iew.exec_refs 590955910 # number of memory reference insts executed +system.cpu.iew.exec_branches 167475793 # Number of branches executed +system.cpu.iew.exec_stores 166785345 # Number of stores executed +system.cpu.iew.exec_rate 1.907911 # Inst execution rate +system.cpu.iew.wb_sent 1749812928 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1744955989 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1325071537 # num instructions producing a value +system.cpu.iew.wb_consumers 1945900521 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.899100 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.680937 # average fanout of values written-back +system.cpu.iew.wb_rate 1.899086 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.680955 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 446546244 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 446680078 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9931583 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 825445175 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.852320 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.435275 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9936737 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 825484986 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.852231 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.435254 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 333247555 40.37% 40.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193457802 23.44% 63.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 63161135 7.65% 71.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92621225 11.22% 82.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24986952 3.03% 85.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27475927 3.33% 89.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9292263 1.13% 90.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11354595 1.38% 91.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69847721 8.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 333347760 40.38% 40.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193315332 23.42% 63.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 63291763 7.67% 71.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92551196 11.21% 82.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24974559 3.03% 85.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27516320 3.33% 89.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9293108 1.13% 90.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11361813 1.38% 91.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69833135 8.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 825445175 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 825484986 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -559,228 +559,228 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions. system.cpu.commit.function_calls 17673145 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69847721 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69833135 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2731132399 # The number of ROB reads -system.cpu.rob.rob_writes 4012169962 # The number of ROB writes -system.cpu.timesIdled 3361848 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32461691 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2731320630 # The number of ROB reads +system.cpu.rob.rob_writes 4012461124 # The number of ROB writes +system.cpu.timesIdled 3340699 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 32393108 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.111226 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.111226 # CPI: Total CPI of All Threads -system.cpu.ipc 0.899907 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.899907 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2716502748 # number of integer regfile reads -system.cpu.int_regfile_writes 1420506154 # number of integer regfile writes -system.cpu.fp_regfile_reads 3672 # number of floating regfile reads -system.cpu.fp_regfile_writes 20 # number of floating regfile writes -system.cpu.cc_regfile_reads 597266892 # number of cc regfile reads -system.cpu.cc_regfile_writes 405440972 # number of cc regfile writes -system.cpu.misc_regfile_reads 964759802 # number of misc regfile reads +system.cpu.cpi 1.111217 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.111217 # CPI: Total CPI of All Threads +system.cpu.ipc 0.899914 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.899914 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2716389897 # number of integer regfile reads +system.cpu.int_regfile_writes 1420532102 # number of integer regfile writes +system.cpu.fp_regfile_reads 3421 # number of floating regfile reads +system.cpu.fp_regfile_writes 19 # number of floating regfile writes +system.cpu.cc_regfile_reads 597244921 # number of cc regfile reads +system.cpu.cc_regfile_writes 405448259 # number of cc regfile writes +system.cpu.misc_regfile_reads 964724023 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 698195949 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1908531 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1908530 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2330856 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 139237 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 139237 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771745 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152897 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7677656 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7830553 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 434176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311361216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 311795392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 311795392 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 8916992 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4909747073 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 697845146 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1906044 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1906043 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2330771 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 136656 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 136656 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771758 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771758 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 150484 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7672451 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7822935 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 439424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311357120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 311796544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 311796544 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 8752064 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4906973310 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 219630492 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 215891495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3954804981 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3953569925 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 5269 # number of replacements -system.cpu.icache.tags.tagsinuse 1036.495304 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 161868325 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6841 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23661.500512 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5335 # number of replacements +system.cpu.icache.tags.tagsinuse 1037.583647 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 161907582 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6916 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 23410.581550 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1036.495304 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.506101 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.506101 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161870260 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161870260 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161870260 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161870260 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161870260 # number of overall hits -system.cpu.icache.overall_hits::total 161870260 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 148071 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 148071 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 148071 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 148071 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 148071 # number of overall misses -system.cpu.icache.overall_misses::total 148071 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 946797737 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 946797737 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 946797737 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 946797737 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 946797737 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 946797737 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162018331 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162018331 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162018331 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162018331 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162018331 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162018331 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000914 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000914 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000914 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000914 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000914 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000914 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6394.214512 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6394.214512 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6394.214512 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6394.214512 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6394.214512 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6394.214512 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 466 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1037.583647 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506633 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506633 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161909622 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161909622 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161909622 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161909622 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161909622 # number of overall hits +system.cpu.icache.overall_hits::total 161909622 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 145600 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 145600 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 145600 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 145600 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 145600 # number of overall misses +system.cpu.icache.overall_misses::total 145600 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 941474740 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 941474740 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 941474740 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 941474740 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 941474740 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 941474740 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162055222 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162055222 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162055222 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162055222 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162055222 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162055222 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000898 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000898 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000898 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000898 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000898 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000898 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6466.172665 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6466.172665 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6466.172665 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6466.172665 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6466.172665 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6466.172665 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 250 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 170 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 77.666667 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 41.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 170 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1958 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1958 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1958 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1958 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1958 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1958 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 146113 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 146113 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 146113 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 146113 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 146113 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 146113 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 564906008 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 564906008 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 564906008 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 564906008 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 564906008 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 564906008 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000902 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000902 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000902 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000902 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000902 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000902 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3866.226879 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3866.226879 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3866.226879 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 3866.226879 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3866.226879 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 3866.226879 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1982 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1982 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1982 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1982 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1982 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1982 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 143618 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 143618 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 143618 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 143618 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 143618 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 143618 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 562974254 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 562974254 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 562974254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 562974254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 562974254 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 562974254 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000886 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000886 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000886 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000886 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000886 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000886 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3919.942166 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3919.942166 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3919.942166 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 3919.942166 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3919.942166 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 3919.942166 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 352904 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29669.825336 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3696987 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 385265 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.595959 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 199212130000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21123.439325 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 223.720045 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8322.665965 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.644636 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006827 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.253988 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.905451 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3631 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1586803 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1590434 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2330856 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2330856 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1444 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1444 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 564904 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 564904 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3631 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2151707 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2155338 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3631 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2151707 # number of overall hits -system.cpu.l2cache.overall_hits::total 2155338 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3154 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 175615 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 178769 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 137793 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 137793 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206841 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206841 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3154 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 382456 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 385610 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3154 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 382456 # number of overall misses -system.cpu.l2cache.overall_misses::total 385610 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239723500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13195248212 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13434971712 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6538219 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 6538219 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15149801477 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 15149801477 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 239723500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 28345049689 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28584773189 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 239723500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 28345049689 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28584773189 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 6785 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1762418 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1769203 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2330856 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2330856 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 139237 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 139237 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 771745 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 771745 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6785 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2534163 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2540948 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6785 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2534163 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2540948 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.464849 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099644 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.101045 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989629 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989629 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268017 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.268017 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.464849 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150920 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151758 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.464849 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150920 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151758 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76006.182625 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75137.364189 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75152.692648 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.449573 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 47.449573 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73243.706407 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73243.706407 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76006.182625 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74113.230513 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74128.713438 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76006.182625 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74113.230513 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74128.713438 # average overall miss latency +system.cpu.l2cache.tags.replacements 352959 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29669.713018 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3697218 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 385325 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.595064 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 199249645000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21121.996968 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 224.213504 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8323.502546 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.644592 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006842 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.254013 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.905448 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3694 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1586802 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1590496 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2330771 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2330771 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1427 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1427 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 564889 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 564889 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3694 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2151691 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2155385 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3694 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2151691 # number of overall hits +system.cpu.l2cache.overall_hits::total 2155385 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3173 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 175624 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 178797 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 135229 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 135229 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206869 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206869 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3173 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 382493 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 385666 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3173 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 382493 # number of overall misses +system.cpu.l2cache.overall_misses::total 385666 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 242389500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13196439955 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13438829455 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6577717 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 6577717 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15144418976 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 15144418976 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 242389500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 28340858931 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28583248431 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 242389500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 28340858931 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28583248431 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 6867 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1762426 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1769293 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2330771 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2330771 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 136656 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 136656 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 771758 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 771758 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6867 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2534184 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2541051 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6867 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2534184 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2541051 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.462065 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099649 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.101056 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989558 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989558 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268049 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.268049 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.462065 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150933 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151774 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.462065 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150933 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151774 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76391.270091 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75140.299475 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75162.499678 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 48.641320 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 48.641320 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73207.773886 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73207.773886 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76391.270091 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74095.104828 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74113.996129 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76391.270091 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74095.104828 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74113.996129 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -789,168 +789,168 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 293579 # number of writebacks -system.cpu.l2cache.writebacks::total 293579 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3154 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175615 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 178769 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 137793 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 137793 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206841 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206841 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3154 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 382456 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 385610 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3154 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 382456 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 385610 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 200295500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10955219212 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11155514712 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1381780092 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1381780092 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12524720523 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12524720523 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 200295500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23479939735 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23680235235 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 200295500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23479939735 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23680235235 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.464849 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099644 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101045 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989629 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989629 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268017 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268017 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.464849 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150920 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151758 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.464849 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150920 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151758 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63505.231452 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62382.024383 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62401.840990 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.941129 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.941129 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60552.407516 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60552.407516 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63505.231452 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61392.525506 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61409.805853 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63505.231452 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61392.525506 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61409.805853 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 293572 # number of writebacks +system.cpu.l2cache.writebacks::total 293572 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3173 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175624 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 178797 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 135229 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 135229 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206869 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206869 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3173 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 382493 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 385666 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3173 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 382493 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 385666 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 202707000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10956266955 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11158973955 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1356015260 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1356015260 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12518797024 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12518797024 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 202707000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23475063979 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23677770979 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 202707000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23475063979 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23677770979 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.462065 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099649 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101056 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989558 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989558 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268049 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268049 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.462065 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150933 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151774 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.462065 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150933 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151774 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63884.966908 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62384.793394 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62411.416047 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.547789 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.547789 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60515.577607 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60515.577607 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63884.966908 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61373.839466 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61394.499331 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63884.966908 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61373.839466 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61394.499331 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2530067 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.247344 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 396095422 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2534163 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 156.302267 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2530088 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.247279 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 395994774 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2534184 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 156.261256 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1794365000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.247344 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.247279 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998107 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998107 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 247349433 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 247349433 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148232494 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148232494 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 395581927 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 395581927 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 395581927 # number of overall hits -system.cpu.dcache.overall_hits::total 395581927 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2875523 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2875523 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 927708 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 927708 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3803231 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3803231 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3803231 # number of overall misses -system.cpu.dcache.overall_misses::total 3803231 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57896671055 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57896671055 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26926543731 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26926543731 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 84823214786 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 84823214786 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 84823214786 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 84823214786 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250224956 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250224956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 247245006 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 247245006 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148235012 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148235012 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 395480018 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 395480018 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 395480018 # number of overall hits +system.cpu.dcache.overall_hits::total 395480018 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2882280 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2882280 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 925190 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 925190 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3807470 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3807470 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3807470 # number of overall misses +system.cpu.dcache.overall_misses::total 3807470 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58083545125 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58083545125 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26852968678 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26852968678 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 84936513803 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 84936513803 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 84936513803 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 84936513803 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250127286 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250127286 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 399385158 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 399385158 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 399385158 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 399385158 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011492 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011492 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006220 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006220 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009523 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009523 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009523 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009523 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20134.309847 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20134.309847 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29024.804929 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29024.804929 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22302.935264 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22302.935264 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22302.935264 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22302.935264 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6209 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 399287488 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 399287488 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 399287488 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 399287488 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011523 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011523 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006203 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006203 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009536 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009536 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009536 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009536 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20151.943991 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20151.943991 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29024.274666 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29024.274666 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22307.861599 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22307.861599 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22307.861599 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22307.861599 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5821 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 638 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 669 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.731975 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.701046 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330856 # number of writebacks -system.cpu.dcache.writebacks::total 2330856 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1112832 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1112832 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17000 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 17000 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1129832 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1129832 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1129832 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1129832 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762691 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762691 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 910708 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 910708 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2673399 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2673399 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2673399 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2673399 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30862506500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30862506500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24793543019 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 24793543019 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55656049519 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 55656049519 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55656049519 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 55656049519 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007044 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007044 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006106 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006106 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006694 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006694 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006694 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006694 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17508.744584 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17508.744584 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27224.470433 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27224.470433 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20818.459766 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20818.459766 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20818.459766 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20818.459766 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2330771 # number of writebacks +system.cpu.dcache.writebacks::total 2330771 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1119584 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1119584 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17046 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 17046 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1136630 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1136630 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1136630 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1136630 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762696 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762696 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 908144 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 908144 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2670840 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2670840 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2670840 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2670840 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30862153254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30862153254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24727931821 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 24727931821 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55590085075 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 55590085075 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55590085075 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 55590085075 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007047 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007047 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006689 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006689 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006689 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006689 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17508.494519 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17508.494519 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27229.086820 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27229.086820 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20813.708449 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20813.708449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20813.708449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20813.708449 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index 14dada76e..427d7de3e 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,17 +518,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -482,6 +541,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -504,12 +564,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -528,7 +591,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 @@ -542,11 +606,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -566,6 +632,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -577,17 +644,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index c079ee28b..68636d517 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.077516 # Nu sim_ticks 77516381000 # Number of ticks simulated final_tick 77516381000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185827 # Simulator instruction rate (inst/s) -host_op_rate 185827 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38353496 # Simulator tick rate (ticks/s) -host_mem_usage 262456 # Number of bytes of host memory used -host_seconds 2021.10 # Real time elapsed on the host +host_inst_rate 154118 # Simulator instruction rate (inst/s) +host_op_rate 154118 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31808931 # Simulator tick rate (ticks/s) +host_mem_usage 282024 # Number of bytes of host memory used +host_seconds 2436.94 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 221184 # Number of bytes read from this memory @@ -210,14 +210,14 @@ system.physmem.bytesPerActivate::7232-7233 1 0.09% 99.66% # system.physmem.bytesPerActivate::8000-8001 1 0.09% 99.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 3 0.26% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1164 # Bytes accessed per row activation -system.physmem.totQLat 59913750 # Total ticks spent queuing -system.physmem.totMemAccLat 199861250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 59914250 # Total ticks spent queuing +system.physmem.totMemAccLat 199861750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37235000 # Total ticks spent in databus transfers system.physmem.totBankLat 102712500 # Total ticks spent accessing banks -system.physmem.avgQLat 8045.35 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8045.42 # Average queueing delay per DRAM burst system.physmem.avgBankLat 13792.47 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26837.82 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26837.89 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.15 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.15 # Average system read bandwidth in MiByte/s @@ -248,15 +248,15 @@ system.membus.data_through_bus 476608 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 9290500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69563000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 69562000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 50307165 # Number of BP lookups +system.cpu.branchPred.lookups 50307155 # Number of BP lookups system.cpu.branchPred.condPredicted 29267262 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1212205 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26317362 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 26317352 # Number of BTB lookups system.cpu.branchPred.BTBHits 23268236 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.414014 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 88.414047 # BTB Hit Percentage system.cpu.branchPred.usedRAS 9019862 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1049 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits @@ -295,23 +295,23 @@ system.cpu.workload.num_syscalls 215 # Nu system.cpu.numCycles 155032764 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 51194246 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 449183514 # Number of instructions fetch has processed -system.cpu.fetch.Branches 50307165 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 51194259 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 449183474 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50307155 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 32288098 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 78871438 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6172162 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19742012 # Number of cycles fetch has spent blocked +system.cpu.fetch.Cycles 78871433 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6172161 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19742008 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 181 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 10560 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 50297233 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 412893 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 154739148 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 412894 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 154739151 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.902843 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.324835 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75867710 49.03% 49.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75867718 49.03% 49.03% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 4287409 2.77% 51.80% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 6889018 4.45% 56.25% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 5374428 3.47% 59.73% # Number of instructions fetched each cycle (Total) @@ -319,24 +319,24 @@ system.cpu.fetch.rateDist::4 11763624 7.60% 67.33% # Nu system.cpu.fetch.rateDist::5 7816659 5.05% 72.38% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 5616009 3.63% 76.01% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 1833388 1.18% 77.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35290903 22.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35290898 22.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154739148 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 154739151 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.324494 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.897346 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 56553427 # Number of cycles decode is idle +system.cpu.fetch.rate 2.897345 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 56553436 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 15088868 # Number of cycles decode is blocked system.cpu.decode.RunCycles 74238964 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3941388 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4916501 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9487391 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4280 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 445247205 # Number of instructions handled by decode +system.cpu.decode.UnblockCycles 3941383 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4916500 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9487386 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4275 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 445247195 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 12161 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4916501 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 59699524 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 4916500 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 59699528 # Number of cycles rename is idle system.cpu.rename.BlockCycles 4890372 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 419538 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 75126102 # Number of cycles rename is running @@ -360,28 +360,28 @@ system.cpu.memDep0.conflictingLoads 8938676 # Nu system.cpu.memDep0.conflictingStores 6410471 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 408405086 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 279 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 401961013 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 974296 # Number of squashed instructions issued +system.cpu.iq.iqInstsIssued 401961016 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 974295 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 32695397 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15321619 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 15321612 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154739148 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.597669 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 154739151 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.597668 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.996651 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28425453 18.37% 18.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28425455 18.37% 18.37% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 25900888 16.74% 35.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25580332 16.53% 51.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25580333 16.53% 51.64% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 24228882 15.66% 67.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21279906 13.75% 81.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15505584 10.02% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21279905 13.75% 81.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15505585 10.02% 91.07% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 8490760 5.49% 96.56% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 3998033 2.58% 99.14% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 1329310 0.86% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154739148 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154739151 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 33873 0.29% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available @@ -412,12 +412,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.09% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5077907 42.90% 74.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5077908 42.90% 74.99% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 2960216 25.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 155836210 38.77% 38.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 155836212 38.77% 38.78% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 2126206 0.53% 39.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 32826139 8.17% 47.47% # Type of FU issued @@ -446,21 +446,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103415840 25.73% 80.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103415841 25.73% 80.27% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 79289575 19.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 401961013 # Type of FU issued +system.cpu.iq.FU_type_0::total 401961016 # Type of FU issued system.cpu.iq.rate 2.592749 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11837270 # FU busy when requested +system.cpu.iq.fu_busy_cnt 11837271 # FU busy when requested system.cpu.iq.fu_busy_rate 0.029449 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 634505765 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 634505774 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 260497209 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 234812476 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 234812479 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 336966975 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 180652533 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 161419314 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 241576218 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 241576222 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 172188484 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 15052407 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -473,11 +473,11 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 260897 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3921 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4916501 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 4916500 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 2514816 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 370985 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 433209224 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 130314 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 130318 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 104720393 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 80633883 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 279 # Number of dispatched non-speculative instructions @@ -489,17 +489,17 @@ system.cpu.iew.predictedNotTakenIncorrect 408580 # N system.cpu.iew.branchMispredicts 1365211 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 398393230 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 101955347 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3567783 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 3567786 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 24803859 # number of nop insts executed system.cpu.iew.exec_refs 180422830 # number of memory reference insts executed system.cpu.iew.exec_branches 46575028 # Number of branches executed system.cpu.iew.exec_stores 78467483 # Number of stores executed system.cpu.iew.exec_rate 2.569736 # Inst execution rate -system.cpu.iew.wb_sent 396861812 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 396231790 # cumulative count of insts written-back -system.cpu.iew.wb_producers 193564450 # num instructions producing a value -system.cpu.iew.wb_consumers 271143007 # num instructions consuming a value +system.cpu.iew.wb_sent 396861814 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396231793 # cumulative count of insts written-back +system.cpu.iew.wb_producers 193564452 # num instructions producing a value +system.cpu.iew.wb_consumers 271143010 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.555794 # insts written-back per cycle system.cpu.iew.wb_fanout 0.713883 # average fanout of values written-back @@ -507,13 +507,13 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 34575269 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1208013 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149822647 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 149822651 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.660910 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.995203 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 55444792 37.01% 37.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22572343 15.07% 52.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13039784 8.70% 60.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 55444795 37.01% 37.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22572345 15.07% 52.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13039783 8.70% 60.78% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 11474023 7.66% 68.43% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 8200661 5.47% 73.91% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 5438800 3.63% 77.54% # Number of insts commited each cycle @@ -523,7 +523,7 @@ system.cpu.commit.committed_per_cycle::8 25200113 16.82% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149822647 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149822651 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -536,10 +536,10 @@ system.cpu.commit.int_insts 316365839 # Nu system.cpu.commit.function_calls 8007752 # Number of function calls committed. system.cpu.commit.bw_lim_events 25200113 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 557859409 # The number of ROB reads +system.cpu.rob.rob_reads 557859413 # The number of ROB reads system.cpu.rob.rob_writes 871404727 # The number of ROB writes system.cpu.timesIdled 3579 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 293616 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 293613 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated @@ -548,7 +548,7 @@ system.cpu.cpi_total 0.412788 # CP system.cpu.ipc 2.422551 # IPC: Instructions Per Cycle system.cpu.ipc_total 2.422551 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 398219851 # number of integer regfile reads -system.cpu.int_regfile_writes 170183529 # number of integer regfile writes +system.cpu.int_regfile_writes 170183531 # number of integer regfile writes system.cpu.fp_regfile_reads 156589680 # number of floating regfile reads system.cpu.fp_regfile_writes 104065109 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads @@ -575,31 +575,31 @@ system.cpu.toL2Bus.respLayer1.occupancy 6675000 # La system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.icache.tags.replacements 2141 # number of replacements system.cpu.icache.tags.tagsinuse 1831.580097 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 50291613 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 50291612 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4069 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12359.698452 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 12359.698206 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1831.580097 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.894326 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.894326 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 50291613 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 50291613 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 50291613 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 50291613 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 50291613 # number of overall hits -system.cpu.icache.overall_hits::total 50291613 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5620 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5620 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5620 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5620 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5620 # number of overall misses -system.cpu.icache.overall_misses::total 5620 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 330576500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 330576500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 330576500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 330576500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 330576500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 330576500 # number of overall miss cycles +system.cpu.icache.ReadReq_hits::cpu.inst 50291612 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 50291612 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 50291612 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 50291612 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 50291612 # number of overall hits +system.cpu.icache.overall_hits::total 50291612 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5621 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5621 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5621 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5621 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5621 # number of overall misses +system.cpu.icache.overall_misses::total 5621 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 330634250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 330634250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 330634250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 330634250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 330634250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 330634250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 50297233 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 50297233 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 50297233 # number of demand (read+write) accesses @@ -612,12 +612,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000112 system.cpu.icache.demand_miss_rate::total 0.000112 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000112 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000112 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58821.441281 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 58821.441281 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 58821.441281 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 58821.441281 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 58821.441281 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 58821.441281 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58821.250667 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 58821.250667 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 58821.250667 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 58821.250667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 58821.250667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 58821.250667 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 892 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked @@ -626,36 +626,36 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 148.666667 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1551 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1551 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1551 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1551 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1551 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1551 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1552 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1552 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1552 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1552 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1552 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1552 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4069 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 4069 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 4069 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 4069 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4069 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4069 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249127500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 249127500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249127500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 249127500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249127500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 249127500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249126500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 249126500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249126500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 249126500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249126500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 249126500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61225.731138 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61225.731138 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61225.731138 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61225.731138 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61225.731138 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61225.731138 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61225.485377 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61225.485377 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61225.485377 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61225.485377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61225.485377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61225.485377 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 4006.698259 # Cycle average of tags in use @@ -694,17 +694,17 @@ system.cpu.l2cache.demand_misses::total 7447 # nu system.cpu.l2cache.overall_misses::cpu.inst 3456 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3991 # number of overall misses system.cpu.l2cache.overall_misses::total 7447 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 238916500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 238915500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 66414500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 305331000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 305330000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 225828500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 225828500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 238916500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 238915500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 292243000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 531159500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 238916500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 531158500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 238915500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 292243000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 531159500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 531158500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4069 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5061 # number of ReadReq accesses(hits+misses) @@ -729,17 +729,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.902557 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.849349 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.954328 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.902557 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69130.931713 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69130.642361 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77136.469222 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70727.588603 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70727.356961 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72149.680511 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72149.680511 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69130.931713 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69130.642361 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73225.507392 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71325.298778 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69130.931713 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71325.164496 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69130.642361 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73225.507392 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71325.298778 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71325.164496 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index dd0636ebe..8cc45b24c 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,18 +173,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -202,16 +216,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -220,22 +237,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -244,22 +265,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -268,10 +293,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -280,124 +307,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -406,10 +454,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -418,16 +468,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -436,10 +489,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -450,6 +505,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -472,14 +528,17 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -498,12 +557,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -514,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -536,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -560,7 +625,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 @@ -574,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -598,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -609,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 93aa60ef6..356503ef7 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068515 # Number of seconds simulated -sim_ticks 68515366500 # Number of ticks simulated -final_tick 68515366500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068510 # Number of seconds simulated +sim_ticks 68509635500 # Number of ticks simulated +final_tick 68509635500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128186 # Simulator instruction rate (inst/s) -host_op_rate 163879 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32166693 # Simulator tick rate (ticks/s) -host_mem_usage 283052 # Number of bytes of host memory used -host_seconds 2130.01 # Real time elapsed on the host +host_inst_rate 105106 # Simulator instruction rate (inst/s) +host_op_rate 134373 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26372946 # Simulator tick rate (ticks/s) +host_mem_usage 303620 # Number of bytes of host memory used +host_seconds 2597.72 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 194304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272128 # Number of bytes read from this memory -system.physmem.bytes_read::total 466432 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 194304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 194304 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3036 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4252 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7288 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2835919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3971781 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6807699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2835919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2835919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2835919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3971781 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6807699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7289 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 194560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272384 # Number of bytes read from this memory +system.physmem.bytes_read::total 466944 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 194560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 194560 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3040 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4256 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7296 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2839892 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3975849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6815742 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2839892 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2839892 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2839892 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3975849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6815742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7296 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7289 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7296 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 466496 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 466944 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 466496 # Total read bytes from the system interface side +system.physmem.bytesReadSys 466944 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -43,13 +43,13 @@ system.physmem.perBankRdBursts::0 607 # Pe system.physmem.perBankRdBursts::1 801 # Per bank write bursts system.physmem.perBankRdBursts::2 608 # Per bank write bursts system.physmem.perBankRdBursts::3 526 # Per bank write bursts -system.physmem.perBankRdBursts::4 443 # Per bank write bursts -system.physmem.perBankRdBursts::5 353 # Per bank write bursts -system.physmem.perBankRdBursts::6 161 # Per bank write bursts -system.physmem.perBankRdBursts::7 217 # Per bank write bursts +system.physmem.perBankRdBursts::4 444 # Per bank write bursts +system.physmem.perBankRdBursts::5 356 # Per bank write bursts +system.physmem.perBankRdBursts::6 162 # Per bank write bursts +system.physmem.perBankRdBursts::7 220 # Per bank write bursts system.physmem.perBankRdBursts::8 207 # Per bank write bursts system.physmem.perBankRdBursts::9 294 # Per bank write bursts -system.physmem.perBankRdBursts::10 325 # Per bank write bursts +system.physmem.perBankRdBursts::10 324 # Per bank write bursts system.physmem.perBankRdBursts::11 416 # Per bank write bursts system.physmem.perBankRdBursts::12 529 # Per bank write bursts system.physmem.perBankRdBursts::13 687 # Per bank write bursts @@ -73,14 +73,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 68515346000 # Total gap between requests +system.physmem.totGap 68509447000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7289 # Read request sizes (log2) +system.physmem.readPktSize::6 7296 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -88,9 +88,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 570 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 177 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -152,80 +152,80 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1271 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 365.973249 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 166.155512 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 760.469459 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 520 40.91% 40.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 218 17.15% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 133 10.46% 68.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 73 5.74% 74.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 41 3.23% 77.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 37 2.91% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 29 2.28% 82.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 36 2.83% 85.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 15 1.18% 86.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 25 1.97% 88.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 5 0.39% 89.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 14 1.10% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 4 0.31% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 8 0.63% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 0.39% 91.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 8 0.63% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 8 0.63% 92.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 6 0.47% 93.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 5 0.39% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 7 0.55% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.16% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 5 0.39% 94.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 5 0.39% 95.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 2 0.16% 95.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.24% 95.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 3 0.24% 95.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 3 0.24% 95.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.16% 96.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 2 0.16% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 4 0.31% 96.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 4 0.31% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 3 0.24% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.08% 97.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.16% 97.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 2 0.16% 97.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.08% 97.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.08% 97.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.08% 97.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 2 0.16% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.08% 98.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 2 0.16% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 2 0.16% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.08% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 2 0.16% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.08% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.16% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.08% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.08% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 3 0.24% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1278 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 364.419405 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 165.521659 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 755.556461 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 528 41.31% 41.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 217 16.98% 58.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 132 10.33% 68.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 73 5.71% 74.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 38 2.97% 77.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 36 2.82% 80.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 30 2.35% 82.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 40 3.13% 85.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 15 1.17% 86.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 24 1.88% 88.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 7 0.55% 89.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 13 1.02% 90.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 4 0.31% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 10 0.78% 91.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 5 0.39% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 6 0.47% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 7 0.55% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 7 0.55% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 3 0.23% 93.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 4 0.31% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 3 0.23% 94.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 6 0.47% 94.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 5 0.39% 94.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 5 0.39% 95.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 2 0.16% 95.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 5 0.39% 95.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 4 0.31% 96.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.16% 96.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 2 0.16% 96.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 3 0.23% 96.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 4 0.31% 97.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 2 0.16% 97.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.08% 97.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 2 0.16% 97.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 2 0.16% 97.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.08% 97.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.08% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.08% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 2 0.16% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.08% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 2 0.16% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 2 0.16% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 2 0.16% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.08% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 2 0.16% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.08% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.08% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.08% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 3 0.23% 99.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::4736-4737 1 0.08% 99.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::6464-6465 1 0.08% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.08% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.08% 99.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::7552-7553 1 0.08% 99.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 2 0.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1271 # Bytes accessed per row activation -system.physmem.totQLat 60705750 # Total ticks spent queuing -system.physmem.totMemAccLat 196384500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36445000 # Total ticks spent in databus transfers -system.physmem.totBankLat 99233750 # Total ticks spent accessing banks -system.physmem.avgQLat 8328.41 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13614.18 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::total 1278 # Bytes accessed per row activation +system.physmem.totQLat 61296000 # Total ticks spent queuing +system.physmem.totMemAccLat 197202250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36480000 # Total ticks spent in databus transfers +system.physmem.totBankLat 99426250 # Total ticks spent accessing banks +system.physmem.avgQLat 8401.32 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13627.50 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26942.58 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27028.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.82 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.81 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.82 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage @@ -235,37 +235,37 @@ system.physmem.avgRdQLen 0.00 # Av system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 6018 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9399827.96 # Average gap between requests -system.physmem.pageHitRate 82.56 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.15 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 6807699 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4464 # Transaction distribution -system.membus.trans_dist::ReadResp 4463 # Transaction distribution +system.physmem.avgGap 9390000.96 # Average gap between requests +system.physmem.pageHitRate 82.48 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.14 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6815742 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4471 # Transaction distribution +system.membus.trans_dist::ReadResp 4471 # Transaction distribution system.membus.trans_dist::UpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 2825 # Transaction distribution system.membus.trans_dist::ReadExResp 2825 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14581 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14581 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 466432 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 466432 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14596 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14596 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466944 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 466944 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 466944 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8930000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8937500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 67824498 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 67899498 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 35429100 # Number of BP lookups -system.cpu.branchPred.condPredicted 21225812 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1661684 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19625450 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16825398 # Number of BTB hits +system.cpu.branchPred.lookups 35425567 # Number of BP lookups +system.cpu.branchPred.condPredicted 21222314 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1660593 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19605313 # Number of BTB lookups +system.cpu.branchPred.BTBHits 16823422 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 85.732546 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6780528 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 8438 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 85.810525 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6781780 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 8434 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -309,100 +309,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 137030734 # number of cpu cycles simulated +system.cpu.numCycles 137019272 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39012994 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 318080298 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35429100 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23605926 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70957862 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6891670 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21493708 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1614 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 39008530 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 318058207 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35425567 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23605202 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70950828 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6887573 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21494775 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 105 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1573 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37614130 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 516506 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136684696 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.983709 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454255 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 37609299 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 515132 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136671204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.983776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454359 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66359879 48.55% 48.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6789497 4.97% 53.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5708838 4.18% 57.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6107274 4.47% 62.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4922167 3.60% 65.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4085695 2.99% 68.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3186230 2.33% 71.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4137086 3.03% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35388030 25.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66353464 48.55% 48.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6794042 4.97% 53.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5704725 4.17% 57.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6102503 4.47% 62.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4920388 3.60% 65.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4084365 2.99% 68.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3186134 2.33% 71.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4139625 3.03% 74.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35385958 25.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136684696 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258549 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.321233 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45532866 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16645865 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66825856 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2530463 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5149646 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7344267 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69062 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401846627 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 213953 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5149646 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 51082336 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1907734 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 332489 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63745566 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14466925 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 394259426 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 53 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1660076 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10182958 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1156 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 432806895 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2333828888 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1575589736 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 200458039 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 136671204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258544 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.321266 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45524127 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16648036 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66820925 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2531461 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5146655 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7342433 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69027 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401839978 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 214083 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5146655 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 51074305 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1910036 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 332499 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63741314 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14466395 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 394244633 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 55 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1658642 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10186296 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1132 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 432779208 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2333721873 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1575557795 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 200430073 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 48240702 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 48213015 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 11816 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 11815 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36507596 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103616420 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91395607 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4296163 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5310753 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 384620101 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22788 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 374263749 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1212133 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34826495 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 87778881 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136684696 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.738154 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.024883 # Number of insts issued each cycle +system.cpu.rename.skidInsts 36510705 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103606610 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91402094 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4304684 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5331956 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 384603029 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22794 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 374241110 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1211414 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34812310 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 87759919 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 674 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136671204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.738259 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.024772 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 25139035 18.39% 18.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19926957 14.58% 32.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20565636 15.05% 48.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18170176 13.29% 61.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24039516 17.59% 78.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15735356 11.51% 90.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8814568 6.45% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3374876 2.47% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 918576 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 25129949 18.39% 18.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19927179 14.58% 32.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20562891 15.05% 48.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18173263 13.30% 61.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24036101 17.59% 78.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15736190 11.51% 90.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8814920 6.45% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3372202 2.47% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 918509 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136684696 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136671204 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8700 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4687 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8708 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4694 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -421,22 +421,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46352 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46360 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7624 0.04% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 437 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7648 0.04% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 433 0.00% 0.38% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 190912 1.08% 1.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4399 0.02% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241386 1.36% 2.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 190801 1.08% 1.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 4328 0.02% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241338 1.36% 2.85% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9273710 52.31% 55.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7950548 44.85% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9265240 52.28% 55.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7952555 44.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126477598 33.79% 33.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2175809 0.58% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126474576 33.79% 33.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2175710 0.58% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.38% # Type of FU issued @@ -455,93 +455,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.38% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6782032 1.81% 36.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6781686 1.81% 36.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8476848 2.26% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3430270 0.92% 39.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1595622 0.43% 39.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20869694 5.58% 45.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7174273 1.92% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7130259 1.91% 49.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8476200 2.26% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3430464 0.92% 39.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1596092 0.43% 39.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20867035 5.58% 45.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7174148 1.92% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7130628 1.91% 49.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101673859 27.17% 76.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88302195 23.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101661693 27.16% 76.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88297588 23.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 374263749 # Type of FU issued -system.cpu.iq.rate 2.731239 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17728757 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047370 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654715892 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 289089659 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 250133425 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249437192 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130393861 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118075733 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 263363212 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128629294 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11082647 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 374241110 # Type of FU issued +system.cpu.iq.rate 2.731303 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17722107 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047355 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654665747 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 289075917 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 250124446 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249421198 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130376340 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118073548 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 263342959 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128620258 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11085750 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8967672 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 108753 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14263 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9020024 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8957862 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 109225 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14255 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9026511 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 174668 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1902 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 173986 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1905 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5149646 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 272927 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 35696 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 384644450 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 871710 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103616420 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91395607 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11754 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 342 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 5146655 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 274797 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 35672 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 384627381 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 873173 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103606610 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91402094 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11760 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 340 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 365 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14263 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1301323 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 370771 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1672094 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 370296137 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100380791 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3967612 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 14255 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1300817 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 370830 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1671647 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 370280641 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100372061 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3960469 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1561 # number of nop insts executed -system.cpu.iew.exec_refs 187597519 # number of memory reference insts executed -system.cpu.iew.exec_branches 32011770 # Number of branches executed -system.cpu.iew.exec_stores 87216728 # Number of stores executed -system.cpu.iew.exec_rate 2.702285 # Inst execution rate -system.cpu.iew.wb_sent 368879898 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 368209158 # cumulative count of insts written-back -system.cpu.iew.wb_producers 183085663 # num instructions producing a value -system.cpu.iew.wb_consumers 363859128 # num instructions consuming a value +system.cpu.iew.exec_nop 1558 # number of nop insts executed +system.cpu.iew.exec_refs 187586293 # number of memory reference insts executed +system.cpu.iew.exec_branches 32011507 # Number of branches executed +system.cpu.iew.exec_stores 87214232 # Number of stores executed +system.cpu.iew.exec_rate 2.702398 # Inst execution rate +system.cpu.iew.wb_sent 368867964 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 368197994 # cumulative count of insts written-back +system.cpu.iew.wb_producers 183086265 # num instructions producing a value +system.cpu.iew.wb_consumers 363871713 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.687055 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.503177 # average fanout of values written-back +system.cpu.iew.wb_rate 2.687199 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.503162 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 35579507 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 35562440 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1592984 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131535050 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.653780 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.659242 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1591916 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131524549 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.653992 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.659233 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34731076 26.40% 26.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28455457 21.63% 48.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13342482 10.14% 58.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11433888 8.69% 66.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13770355 10.47% 77.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7412668 5.64% 82.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3873056 2.94% 85.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3888664 2.96% 88.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14627404 11.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34720675 26.40% 26.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28457654 21.64% 48.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13339371 10.14% 58.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11431101 8.69% 66.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13773309 10.47% 77.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7413510 5.64% 82.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3874860 2.95% 85.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3887136 2.96% 88.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14626933 11.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131535050 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131524549 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -552,220 +552,220 @@ system.cpu.commit.branches 30563497 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14627404 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14626933 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 501549691 # The number of ROB reads -system.cpu.rob.rob_writes 774443009 # The number of ROB writes -system.cpu.timesIdled 6642 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 346038 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 501522594 # The number of ROB reads +system.cpu.rob.rob_writes 774405807 # The number of ROB writes +system.cpu.timesIdled 6645 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 348068 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated -system.cpu.cpi 0.501877 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.501877 # CPI: Total CPI of All Threads -system.cpu.ipc 1.992522 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.992522 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1770065591 # number of integer regfile reads -system.cpu.int_regfile_writes 233053939 # number of integer regfile writes -system.cpu.fp_regfile_reads 188169392 # number of floating regfile reads -system.cpu.fp_regfile_writes 132536105 # number of floating regfile writes -system.cpu.misc_regfile_reads 566956802 # number of misc regfile reads +system.cpu.cpi 0.501835 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.501835 # CPI: Total CPI of All Threads +system.cpu.ipc 1.992688 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.992688 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1769988396 # number of integer regfile reads +system.cpu.int_regfile_writes 233047297 # number of integer regfile writes +system.cpu.fp_regfile_reads 188164665 # number of floating regfile reads +system.cpu.fp_regfile_writes 132532739 # number of floating regfile writes +system.cpu.misc_regfile_reads 566941334 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.throughput 20102702 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 17643 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 17642 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1037 # Transaction distribution +system.cpu.toL2Bus.throughput 20093174 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 17631 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 17631 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1036 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2842 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2842 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31749 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10257 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 42006 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1015808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1377088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1377088 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31714 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10268 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 41982 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1014720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 1376320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1376320 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 11799000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 11791500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24347988 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24322738 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7401462 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7408962 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 13986 # number of replacements -system.cpu.icache.tags.tagsinuse 1848.638823 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 37596770 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15875 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2368.300472 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13968 # number of replacements +system.cpu.icache.tags.tagsinuse 1848.251388 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 37591948 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15858 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2370.535250 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1848.638823 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.902656 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.902656 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37596770 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37596770 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37596770 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37596770 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37596770 # number of overall hits -system.cpu.icache.overall_hits::total 37596770 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17358 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17358 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17358 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17358 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17358 # number of overall misses -system.cpu.icache.overall_misses::total 17358 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 450239984 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 450239984 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 450239984 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 450239984 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 450239984 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 450239984 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37614128 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37614128 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37614128 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37614128 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37614128 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37614128 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1848.251388 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.902466 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.902466 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37591948 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37591948 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37591948 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37591948 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37591948 # number of overall hits +system.cpu.icache.overall_hits::total 37591948 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17349 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17349 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17349 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17349 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17349 # number of overall misses +system.cpu.icache.overall_misses::total 17349 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 451171984 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 451171984 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 451171984 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 451171984 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 451171984 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 451171984 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37609297 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37609297 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37609297 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37609297 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37609297 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37609297 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000461 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000461 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000461 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000461 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000461 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000461 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25938.471252 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25938.471252 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25938.471252 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25938.471252 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25938.471252 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25938.471252 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2006 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26005.647818 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 26005.647818 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 26005.647818 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 26005.647818 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 26005.647818 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 26005.647818 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2002 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 87.217391 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 87.043478 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1481 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1481 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1481 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1481 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1481 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1481 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15877 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15877 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15877 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15877 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15877 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15877 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359424009 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 359424009 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359424009 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 359424009 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359424009 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 359424009 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1490 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1490 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1490 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1490 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1490 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1490 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15859 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15859 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15859 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15859 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15859 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15859 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359132259 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 359132259 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359132259 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 359132259 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359132259 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 359132259 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000422 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000422 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000422 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22638.030421 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22638.030421 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22638.030421 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22638.030421 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22638.030421 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22638.030421 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22645.328142 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22645.328142 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22645.328142 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22645.328142 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22645.328142 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22645.328142 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3939.771440 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13217 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5387 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.453499 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3941.799565 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13198 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5394 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.446793 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 378.229398 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2786.621740 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 774.920301 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011543 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.085041 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.023649 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.120232 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12824 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 299 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13123 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1037 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1037 # number of Writeback hits +system.cpu.l2cache.tags.occ_blocks::writebacks 379.005926 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2786.464306 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 776.329333 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011566 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.085036 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.023692 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.120294 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 12803 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 301 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 13104 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1036 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1036 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12824 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 316 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13140 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12824 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 316 # number of overall hits -system.cpu.l2cache.overall_hits::total 13140 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3049 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1467 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4516 # number of ReadReq misses +system.cpu.l2cache.demand_hits::cpu.inst 12803 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 318 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13121 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12803 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 318 # number of overall hits +system.cpu.l2cache.overall_hits::total 13121 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3052 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1471 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4523 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 2825 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 2825 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3049 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 4292 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7341 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3049 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 4292 # number of overall misses -system.cpu.l2cache.overall_misses::total 7341 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 215269250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 108631000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 323900250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 199625500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 199625500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 215269250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 308256500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 523525750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 215269250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 308256500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 523525750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 15873 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1766 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 17639 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1037 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1037 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 3052 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 4296 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7348 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3052 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 4296 # number of overall misses +system.cpu.l2cache.overall_misses::total 7348 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 215204250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 109433000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 324637250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 200213000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 200213000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 215204250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 309646000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 524850250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 215204250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 309646000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 524850250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 15855 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1772 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 17627 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1036 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1036 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 2842 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 2842 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 15873 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4608 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 20481 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15873 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4608 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 20481 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192087 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.830691 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.256024 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 15855 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4614 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 20469 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15855 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4614 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 20469 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192494 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.830135 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.256595 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994018 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.994018 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192087 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.931424 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.358430 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192087 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.931424 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.358430 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70603.230567 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74049.761418 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71722.818866 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70663.893805 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70663.893805 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70603.230567 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71821.178938 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71315.318077 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70603.230567 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71821.178938 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71315.318077 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192494 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.931079 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.358982 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192494 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.931079 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.358982 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70512.532765 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74393.609789 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71774.762326 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70871.858407 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70871.858407 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70512.532765 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72077.746741 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71427.633370 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70512.532765 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72077.746741 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71427.633370 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -783,112 +783,112 @@ system.cpu.l2cache.demand_mshr_hits::total 52 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 52 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3037 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1427 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4464 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3040 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1431 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4471 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2825 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 2825 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3037 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 4252 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7289 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3037 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 4252 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7289 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 176465000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 88132000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264597000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3040 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4256 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7296 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3040 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4256 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7296 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 176370000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 88886000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 265256000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 164645000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 164645000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176465000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 252777000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 429242000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176465000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 252777000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 429242000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191331 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.808041 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253076 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 165233500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 165233500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176370000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 254119500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 430489500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176370000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 254119500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 430489500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191738 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807562 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253645 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994018 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994018 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191331 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922743 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.355891 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191331 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922743 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.355891 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58105.037866 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61760.336370 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59273.521505 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191738 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922410 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.356441 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191738 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922410 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.356441 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58016.447368 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62114.605171 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59328.114516 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58281.415929 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58281.415929 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58105.037866 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59448.965193 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58889.010838 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58105.037866 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59448.965193 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58889.010838 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58489.734513 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58489.734513 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58016.447368 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59708.529135 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.495066 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58016.447368 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59708.529135 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59003.495066 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1414 # number of replacements -system.cpu.dcache.tags.tagsinuse 3101.535581 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 170993874 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4608 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37108.045573 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1417 # number of replacements +system.cpu.dcache.tags.tagsinuse 3102.941006 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170982340 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4614 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37057.290854 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3101.535581 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.757211 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.757211 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88940583 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88940583 # number of ReadReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 3102.941006 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.757554 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.757554 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88929043 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88929043 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82031381 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 82031381 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11003 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11003 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11009 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11009 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170971964 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170971964 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170971964 # number of overall hits -system.cpu.dcache.overall_hits::total 170971964 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3947 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3947 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 170960424 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170960424 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170960424 # number of overall hits +system.cpu.dcache.overall_hits::total 170960424 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3956 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3956 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 21284 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 21284 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25231 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25231 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25231 # number of overall misses -system.cpu.dcache.overall_misses::total 25231 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 233964205 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 233964205 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1259611139 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1259611139 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 25240 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25240 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25240 # number of overall misses +system.cpu.dcache.overall_misses::total 25240 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 235586955 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 235586955 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1260992389 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1260992389 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1493575344 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1493575344 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1493575344 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1493575344 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88944530 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88944530 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 1496579344 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1496579344 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1496579344 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1496579344 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88932999 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88932999 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11005 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11005 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11011 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11011 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170997195 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170997195 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170997195 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170997195 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 170985664 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170985664 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170985664 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170985664 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000259 # miss rate for WriteReq accesses @@ -899,52 +899,52 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000148 system.cpu.dcache.demand_miss_rate::total 0.000148 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000148 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000148 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59276.464403 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59276.464403 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59181.128500 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59181.128500 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59551.808645 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59551.808645 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59246.024666 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59246.024666 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59196.042329 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59196.042329 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59196.042329 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59196.042329 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28298 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59293.951823 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59293.951823 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59293.951823 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59293.951823 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28312 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 410 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 411 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.019512 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.885645 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 102 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1037 # number of writebacks -system.cpu.dcache.writebacks::total 1037 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2179 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2179 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1036 # number of writebacks +system.cpu.dcache.writebacks::total 1036 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2182 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2182 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18442 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 18442 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20621 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20621 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20621 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20621 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1768 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1768 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 20624 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20624 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20624 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20624 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1774 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1774 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2842 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2842 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4610 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4610 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4610 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4610 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 113556540 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 113556540 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 202620998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 202620998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 316177538 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 316177538 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 316177538 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 316177538 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 4616 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4616 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4616 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4616 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 114384040 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 114384040 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 203208498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 203208498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 317592538 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 317592538 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317592538 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 317592538 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -953,14 +953,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64228.812217 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64228.812217 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71295.213934 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71295.213934 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68585.149241 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68585.149241 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68585.149241 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68585.149241 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64478.038331 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64478.038331 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71501.934553 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71501.934553 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68802.542894 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68802.542894 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68802.542894 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68802.542894 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index 507dc65a9..3613fc19c 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,17 +518,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -482,6 +541,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -504,12 +564,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -528,7 +591,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -542,11 +606,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -566,6 +632,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -577,17 +644,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 23516d587..2a6478fe5 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.631518 # Nu sim_ticks 631518097500 # Number of ticks simulated final_tick 631518097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141288 # Simulator instruction rate (inst/s) -host_op_rate 141288 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48943367 # Simulator tick rate (ticks/s) -host_mem_usage 266484 # Number of bytes of host memory used -host_seconds 12903.04 # Real time elapsed on the host +host_inst_rate 116160 # Simulator instruction rate (inst/s) +host_op_rate 116160 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40238771 # Simulator tick rate (ticks/s) +host_mem_usage 286040 # Number of bytes of host memory used +host_seconds 15694.27 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 176128 # Number of bytes read from this memory @@ -273,8 +273,8 @@ system.physmem.bytesPerActivate::6848 54 0.03% 100.00% # By system.physmem.bytesPerActivate::6912 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 182335 # Bytes accessed per row activation -system.physmem.totQLat 2888041500 # Total ticks spent queuing -system.physmem.totMemAccLat 14116019000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2888040000 # Total ticks spent queuing +system.physmem.totMemAccLat 14116017500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2380155000 # Total ticks spent in databus transfers system.physmem.totBankLat 8847822500 # Total ticks spent accessing banks system.physmem.avgQLat 6066.92 # Average queueing delay per DRAM burst @@ -310,9 +310,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 34753664 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 34753664 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1230653000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1230652000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4488013000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4488013500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu.branchPred.lookups 388926557 # Number of BP lookups system.cpu.branchPred.condPredicted 255987580 # Number of conditional branches predicted @@ -339,10 +339,10 @@ system.cpu.dtb.data_hits 805300436 # DT system.cpu.dtb.data_misses 641311 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 805941747 # DTB accesses -system.cpu.itb.fetch_hits 394923337 # ITB hits +system.cpu.itb.fetch_hits 394923336 # ITB hits system.cpu.itb.fetch_misses 673 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 394924010 # ITB accesses +system.cpu.itb.fetch_accesses 394924009 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -359,62 +359,62 @@ system.cpu.workload.num_syscalls 39 # Nu system.cpu.numCycles 1263036196 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 410109211 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3275361916 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 410109214 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3275361918 # Number of instructions fetch has processed system.cpu.fetch.Branches 388926557 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 315652943 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 630278695 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 157942219 # Number of cycles fetch has spent squashing +system.cpu.fetch.SquashCycles 157942220 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 76359250 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 149 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 7183 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 394923337 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11250821 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1248398015 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 394923336 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11250823 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1248398019 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.623652 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.139094 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 618119320 49.51% 49.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 618119324 49.51% 49.51% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 57470502 4.60% 54.12% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 43321703 3.47% 57.59% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 71848580 5.76% 63.34% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 129169735 10.35% 73.69% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 46220345 3.70% 77.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41223037 3.30% 80.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41223036 3.30% 80.69% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 7614963 0.61% 81.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 233409830 18.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 233409831 18.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1248398015 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1248398019 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.307930 # Number of branch fetches per cycle system.cpu.fetch.rate 2.593245 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 438388188 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 62722157 # Number of cycles decode is blocked +system.cpu.decode.IdleCycles 438388192 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 62722156 # Number of cycles decode is blocked system.cpu.decode.RunCycles 606598506 # Number of cycles decode is running system.cpu.decode.UnblockCycles 9057712 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 131631452 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 131631453 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 31714965 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 12425 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 3194311917 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 46335 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 131631452 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 467678490 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 27888697 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 131631453 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 467678494 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 27888696 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 27235 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 586017174 # Number of cycles rename is running system.cpu.rename.UnblockCycles 35154967 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3095577928 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 3095577926 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 161 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 15278 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 28853292 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2054701915 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3579840201 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3494452831 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 2054701913 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3579840200 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3494452830 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 85387369 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 669732845 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 669732843 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4230 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 109697167 # count of insts added to the skid buffer @@ -422,30 +422,30 @@ system.cpu.memDep0.insertedLoads 743928173 # Nu system.cpu.memDep0.insertedStores 351370571 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 69056444 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 8824928 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2623617017 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 2623617019 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 88 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2160251370 # Number of instructions issued +system.cpu.iq.iqInstsIssued 2160251371 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 17943532 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 800506396 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 800506398 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 726504541 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1248398015 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1248398019 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.730419 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.803325 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 451794383 36.19% 36.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 196881070 15.77% 51.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 451794387 36.19% 36.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 196881068 15.77% 51.96% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 251357257 20.13% 72.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120660417 9.67% 81.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 104720930 8.39% 90.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79314006 6.35% 96.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120660419 9.67% 81.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 104720933 8.39% 90.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79314003 6.35% 96.50% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 24236778 1.94% 98.44% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 17665275 1.42% 99.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 1767899 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1248398015 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1248398019 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 1146213 3.11% 3.11% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.11% # attempts to use FU when none available @@ -481,7 +481,7 @@ system.cpu.iq.fu_full::MemWrite 10022787 27.21% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1234386708 57.14% 57.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1234386709 57.14% 57.14% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 17098 0.00% 57.14% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.14% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 27851280 1.29% 58.43% # Type of FU issued @@ -514,17 +514,17 @@ system.cpu.iq.FU_type_0::MemRead 589426190 27.29% 86.43% # Ty system.cpu.iq.FU_type_0::MemWrite 293107997 13.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2160251370 # Type of FU issued +system.cpu.iq.FU_type_0::total 2160251371 # Type of FU issued system.cpu.iq.rate 1.710364 # Inst issue rate system.cpu.iq.fu_busy_cnt 36833248 # FU busy when requested system.cpu.iq.fu_busy_rate 0.017050 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5472576315 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3336085104 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1990052080 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 5472576321 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3336085108 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1990052081 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 151101220 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 88112403 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 73609796 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2119632114 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 2119632115 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 77449752 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 62130294 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -537,11 +537,11 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 4420 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 2986 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 131631452 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 131631453 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 13854870 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 540713 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2987064962 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 734569 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispatchedInsts 2987064964 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 734565 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 743928173 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 351370571 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions @@ -553,31 +553,31 @@ system.cpu.iew.predictedNotTakenIncorrect 30372 # N system.cpu.iew.branchMispredicts 25831592 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 2066130188 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 522867337 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 94121182 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 94121183 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 363447857 # number of nop insts executed system.cpu.iew.exec_refs 805942372 # number of memory reference insts executed system.cpu.iew.exec_branches 277625839 # Number of branches executed system.cpu.iew.exec_stores 283075035 # Number of stores executed system.cpu.iew.exec_rate 1.635844 # Inst execution rate -system.cpu.iew.wb_sent 2066015512 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2063661876 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1180966909 # num instructions producing a value -system.cpu.iew.wb_consumers 1753315236 # num instructions consuming a value +system.cpu.iew.wb_sent 2066015513 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2063661877 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1180966911 # num instructions producing a value +system.cpu.iew.wb_consumers 1753315239 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.633890 # insts written-back per cycle system.cpu.iew.wb_fanout 0.673562 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 961121272 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 961121274 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 25796748 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1116766563 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 1116766566 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.798932 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.506928 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 497624739 44.56% 44.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 228755329 20.48% 65.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119853189 10.73% 75.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 497624741 44.56% 44.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 228755331 20.48% 65.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119853188 10.73% 75.78% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 58815833 5.27% 81.04% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 50567042 4.53% 85.57% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 24161277 2.16% 87.73% # Number of insts commited each cycle @@ -587,7 +587,7 @@ system.cpu.commit.committed_per_cycle::8 101220222 9.06% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1116766563 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1116766566 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -600,10 +600,10 @@ system.cpu.commit.int_insts 1778941351 # Nu system.cpu.commit.function_calls 39955347 # Number of function calls committed. system.cpu.commit.bw_lim_events 101220222 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3980018807 # The number of ROB reads -system.cpu.rob.rob_writes 6071851296 # The number of ROB writes +system.cpu.rob.rob_reads 3980018812 # The number of ROB reads +system.cpu.rob.rob_writes 6071851301 # The number of ROB writes system.cpu.timesIdled 346634 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 14638181 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 14638177 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated @@ -612,7 +612,7 @@ system.cpu.cpi_total 0.692817 # CP system.cpu.ipc 1.443382 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.443382 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 2627972093 # number of integer regfile reads -system.cpu.int_regfile_writes 1496658984 # number of integer regfile writes +system.cpu.int_regfile_writes 1496658985 # number of integer regfile writes system.cpu.fp_regfile_reads 78811105 # number of floating regfile reads system.cpu.fp_regfile_writes 52661052 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads @@ -639,54 +639,54 @@ system.cpu.toL2Bus.respLayer1.occupancy 2359590250 # La system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) system.cpu.icache.tags.replacements 8311 # number of replacements system.cpu.icache.tags.tagsinuse 1658.001589 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 394910394 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 394910393 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 10024 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 39396.487829 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 39396.487729 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1658.001589 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.809571 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.809571 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 394910394 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 394910394 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 394910394 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 394910394 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 394910394 # number of overall hits -system.cpu.icache.overall_hits::total 394910394 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 394910393 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 394910393 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 394910393 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 394910393 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 394910393 # number of overall hits +system.cpu.icache.overall_hits::total 394910393 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 12943 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 12943 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 12943 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 12943 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 12943 # number of overall misses system.cpu.icache.overall_misses::total 12943 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 383675499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 383675499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 383675499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 383675499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 383675499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 383675499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 394923337 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 394923337 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 394923337 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 394923337 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 394923337 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 394923337 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 383664999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 383664999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 383664999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 383664999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 383664999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 383664999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 394923336 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 394923336 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 394923336 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 394923336 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 394923336 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 394923336 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29643.475160 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29643.475160 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29643.475160 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29643.475160 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29643.475160 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29643.475160 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 706 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29642.663911 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29642.663911 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29642.663911 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29642.663911 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29642.663911 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29642.663911 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 707 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 54.307692 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 54.384615 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -702,24 +702,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10025 system.cpu.icache.demand_mshr_misses::total 10025 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10025 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10025 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281680749 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281680749 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281680749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281680749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281680749 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281680749 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281678249 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281678249 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281678249 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281678249 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281678249 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281678249 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28097.830324 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28097.830324 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28097.830324 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 28097.830324 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28097.830324 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 28097.830324 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28097.580948 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28097.580948 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28097.580948 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28097.580948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28097.580948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28097.580948 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 443340 # number of replacements system.cpu.l2cache.tags.tagsinuse 32689.012035 # Cycle average of tags in use @@ -758,17 +758,17 @@ system.cpu.l2cache.demand_misses::total 476119 # nu system.cpu.l2cache.overall_misses::cpu.inst 2752 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 473367 # number of overall misses system.cpu.l2cache.overall_misses::total 476119 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 198914750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 198912250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29323124000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29522038750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29522036250 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5227072250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 5227072250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 198914750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 198912250 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 34550196250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34749111000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 198914750 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 34749108500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 198912250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 34550196250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34749111000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34749108500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 10025 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1460252 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1470277 # number of ReadReq accesses(hits+misses) @@ -793,17 +793,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.308784 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.274514 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.309008 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.308784 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72280.069041 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72279.160610 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72133.122106 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72134.110212 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72134.104103 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78187.549549 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78187.549549 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72280.069041 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72279.160610 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72988.180946 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72984.088012 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72280.069041 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72984.082761 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72279.160610 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72988.180946 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72984.088012 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72984.082761 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -825,17 +825,17 @@ system.cpu.l2cache.demand_mshr_misses::total 476119 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2752 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 473367 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 476119 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164199250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164196250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24183867000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24348066250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24348063250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4422430250 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4422430250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164199250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164196250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28606297250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28770496500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164199250 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28770493500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164196250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28606297250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28770496500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28770493500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.274514 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278386 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278360 # mshr miss rate for ReadReq accesses @@ -847,17 +847,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.308784 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.274514 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309008 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.308784 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59665.425145 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59664.335029 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59490.858863 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59492.032688 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59492.025358 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66151.560139 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66151.560139 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59665.425145 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59664.335029 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60431.540961 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60427.112760 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59665.425145 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60427.106459 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59664.335029 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60431.540961 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60427.112760 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60427.106459 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 1527796 # number of replacements system.cpu.dcache.tags.tagsinuse 4094.588575 # Cycle average of tags in use @@ -888,10 +888,10 @@ system.cpu.dcache.demand_misses::cpu.data 2987711 # n system.cpu.dcache.demand_misses::total 2987711 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2987711 # number of overall misses system.cpu.dcache.overall_misses::total 2987711 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 77391156750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 77391156750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 46191877602 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 46191877602 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 77391157750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 77391157750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 46191876602 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 46191876602 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 78000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 78000 # number of LoadLockedReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 123583034352 # number of demand (read+write) miss cycles @@ -918,10 +918,10 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004453 system.cpu.dcache.demand_miss_rate::total 0.004453 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004453 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004453 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40187.415618 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40187.415618 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43497.019744 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43497.019744 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40187.416137 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40187.416137 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43497.018802 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43497.018802 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78000 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 41363.784634 # average overall miss latency diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index be78ce1bf..cbb921be0 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,18 +173,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -202,16 +216,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -220,22 +237,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -244,22 +265,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -268,10 +293,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -280,124 +307,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -406,10 +454,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -418,16 +468,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -436,10 +489,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -450,6 +505,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -472,14 +528,17 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -498,12 +557,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -514,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -536,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -560,7 +625,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -574,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -598,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -609,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 2fb0bf01c..6310afb8f 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,78 +1,78 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.633885 # Number of seconds simulated -sim_ticks 633884897500 # Number of ticks simulated -final_tick 633884897500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.629535 # Number of seconds simulated +sim_ticks 629535413500 # Number of ticks simulated +final_tick 629535413500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87779 # Simulator instruction rate (inst/s) -host_op_rate 119542 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40192628 # Simulator tick rate (ticks/s) -host_mem_usage 283676 # Number of bytes of host memory used -host_seconds 15771.17 # Real time elapsed on the host +host_inst_rate 71307 # Simulator instruction rate (inst/s) +host_op_rate 97111 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32426577 # Simulator tick rate (ticks/s) +host_mem_usage 303200 # Number of bytes of host memory used +host_seconds 19414.18 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 155136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30242944 # Number of bytes read from this memory -system.physmem.bytes_read::total 30398080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30242496 # Number of bytes read from this memory +system.physmem.bytes_read::total 30397632 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 155136 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 155136 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472546 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474970 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 472539 # Number of read requests responded to by this memory +system.physmem.num_reads::total 474963 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 244738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47710466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47955205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 244738 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 244738 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6673565 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6673565 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6673565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 244738 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47710466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54628770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 474970 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 246429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48039388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48285817 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 246429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 246429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6719673 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6719673 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6719673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 246429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48039388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55005490 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 474963 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 474970 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 474963 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30392000 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6080 # Total number of bytes read from write queue -system.physmem.bytesWritten 4230080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30398080 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 30390400 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue +system.physmem.bytesWritten 4229888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30397632 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4324 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 29875 # Per bank write bursts -system.physmem.perBankRdBursts::1 29673 # Per bank write bursts -system.physmem.perBankRdBursts::2 29745 # Per bank write bursts -system.physmem.perBankRdBursts::3 29707 # Per bank write bursts -system.physmem.perBankRdBursts::4 29817 # Per bank write bursts -system.physmem.perBankRdBursts::5 29835 # Per bank write bursts -system.physmem.perBankRdBursts::6 29655 # Per bank write bursts -system.physmem.perBankRdBursts::7 29450 # Per bank write bursts -system.physmem.perBankRdBursts::8 29485 # Per bank write bursts -system.physmem.perBankRdBursts::9 29492 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 4262 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 29871 # Per bank write bursts +system.physmem.perBankRdBursts::1 29675 # Per bank write bursts +system.physmem.perBankRdBursts::2 29749 # Per bank write bursts +system.physmem.perBankRdBursts::3 29712 # Per bank write bursts +system.physmem.perBankRdBursts::4 29816 # Per bank write bursts +system.physmem.perBankRdBursts::5 29834 # Per bank write bursts +system.physmem.perBankRdBursts::6 29642 # Per bank write bursts +system.physmem.perBankRdBursts::7 29444 # Per bank write bursts +system.physmem.perBankRdBursts::8 29480 # Per bank write bursts +system.physmem.perBankRdBursts::9 29489 # Per bank write bursts system.physmem.perBankRdBursts::10 29547 # Per bank write bursts -system.physmem.perBankRdBursts::11 29655 # Per bank write bursts -system.physmem.perBankRdBursts::12 29700 # Per bank write bursts -system.physmem.perBankRdBursts::13 29805 # Per bank write bursts +system.physmem.perBankRdBursts::11 29649 # Per bank write bursts +system.physmem.perBankRdBursts::12 29701 # Per bank write bursts +system.physmem.perBankRdBursts::13 29813 # Per bank write bursts system.physmem.perBankRdBursts::14 29629 # Per bank write bursts -system.physmem.perBankRdBursts::15 29805 # Per bank write bursts +system.physmem.perBankRdBursts::15 29799 # Per bank write bursts system.physmem.perBankWrBursts::0 4174 # Per bank write bursts system.physmem.perBankWrBursts::1 4102 # Per bank write bursts system.physmem.perBankWrBursts::2 4138 # Per bank write bursts system.physmem.perBankWrBursts::3 4148 # Per bank write bursts system.physmem.perBankWrBursts::4 4226 # Per bank write bursts system.physmem.perBankWrBursts::5 4224 # Per bank write bursts -system.physmem.perBankWrBursts::6 4174 # Per bank write bursts +system.physmem.perBankWrBursts::6 4173 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4094 # Per bank write bursts -system.physmem.perBankWrBursts::10 4096 # Per bank write bursts +system.physmem.perBankWrBursts::9 4093 # Per bank write bursts +system.physmem.perBankWrBursts::10 4095 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4140 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 633884833500 # Total gap between requests +system.physmem.totGap 629535350500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 474970 # Read request sizes (log2) +system.physmem.readPktSize::6 474963 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,13 +95,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407902 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 66 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -130,9 +130,9 @@ system.physmem.rdQLenPdf::31 0 # Wh system.physmem.wrQLenPdf::0 3005 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 3005 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3005 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3004 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3004 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 3004 # What write queue length does an incoming req see @@ -144,11 +144,11 @@ system.physmem.wrQLenPdf::13 3004 # Wh system.physmem.wrQLenPdf::14 3004 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 3004 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3005 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3006 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see @@ -159,161 +159,161 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 190556 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 181.682403 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 122.345891 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 377.529861 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 76623 40.21% 40.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 50018 26.25% 66.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 37571 19.72% 86.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 19599 10.29% 96.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 202 0.11% 96.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 233 0.12% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 93 0.05% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 219 0.11% 96.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 79 0.04% 96.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 190822 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 181.419082 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 122.160667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 377.205430 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 76972 40.34% 40.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 49989 26.20% 66.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 37639 19.72% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 19482 10.21% 96.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 187 0.10% 96.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 252 0.13% 96.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 85 0.04% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 218 0.11% 96.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 85 0.04% 96.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::640 231 0.12% 97.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 59 0.03% 97.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 225 0.12% 97.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 74 0.04% 97.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 178 0.09% 97.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 61 0.03% 97.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 176 0.09% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 47 0.02% 97.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 188 0.10% 97.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 71 0.04% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 186 0.10% 97.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 71 0.04% 97.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 3176 1.67% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 17 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 14 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 12 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 11 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 7 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 10 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 16 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 14 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 52 0.03% 97.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 225 0.12% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 65 0.03% 97.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 188 0.10% 97.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 60 0.03% 97.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 181 0.09% 97.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 44 0.02% 97.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 201 0.11% 97.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 67 0.04% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 181 0.09% 97.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 66 0.03% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 3167 1.66% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 20 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 13 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 12 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 12 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 13 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 17 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 15 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 15 0.01% 99.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::1984 19 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 23 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 18 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 9 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 10 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 18 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 13 0.01% 99.47% # Bytes accessed per row activation system.physmem.bytesPerActivate::2240 11 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 13 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 10 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 12 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 24 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 8 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 18 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 22 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 22 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 14 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 14 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 14 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 15 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 21 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 12 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 17 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 16 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 16 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 13 0.01% 99.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::2880 12 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 11 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 10 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 8 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136 14 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 4 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 19 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 19 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 21 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 17 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 18 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 12 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648 19 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712 10 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776 12 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840 10 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904 12 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968 16 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032 16 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 16 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 31 0.02% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 17 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288 10 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 9 0.00% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416 11 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480 6 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544 17 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 12 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 14 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 9 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136 19 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 10 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 20 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 10 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 16 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 12 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 21 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 13 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648 16 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712 15 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776 18 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840 7 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904 15 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968 17 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032 14 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 12 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 28 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 16 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288 14 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 7 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416 17 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480 11 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544 14 0.01% 99.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::4608 12 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672 16 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736 14 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 19 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864 17 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928 16 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 3 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 13 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 6 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184 7 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248 7 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312 10 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376 14 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440 20 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504 16 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672 19 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736 10 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800 13 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864 9 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928 17 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 8 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 17 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 7 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184 9 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248 9 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312 13 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376 11 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440 14 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504 12 0.01% 99.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::5568 15 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632 12 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696 34 0.02% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760 69 0.04% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824 58 0.03% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888 3 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016 3 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632 15 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696 31 0.02% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760 73 0.04% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824 59 0.03% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888 4 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952 3 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016 6 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::6080 8 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144 59 0.03% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144 53 0.03% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::6208 4 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 190556 # Bytes accessed per row activation -system.physmem.totQLat 3723849000 # Total ticks spent queuing -system.physmem.totMemAccLat 15162897750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2374375000 # Total ticks spent in databus transfers -system.physmem.totBankLat 9064673750 # Total ticks spent accessing banks -system.physmem.avgQLat 7841.75 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 19088.55 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::total 190822 # Bytes accessed per row activation +system.physmem.totQLat 3804882250 # Total ticks spent queuing +system.physmem.totMemAccLat 15248096000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2374250000 # Total ticks spent in databus transfers +system.physmem.totBankLat 9068963750 # Total ticks spent accessing banks +system.physmem.avgQLat 8012.81 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 19098.59 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31930.29 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 47.95 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.67 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 47.96 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 6.67 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 32111.40 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 48.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.72 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 48.29 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 6.72 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.43 # Data bus utilization in percentage -system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.41 # Average write queue length when enqueuing -system.physmem.readRowHits 301072 # Number of row buffer hits during reads -system.physmem.writeRowHits 49342 # Number of row buffer hits during writes -system.physmem.readRowHitRate 63.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.65 # Row buffer hit rate for writes -system.physmem.avgGap 1171543.75 # Average gap between requests -system.physmem.pageHitRate 64.77 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 24.91 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 54628770 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 408895 # Transaction distribution -system.membus.trans_dist::ReadResp 408895 # Transaction distribution +system.physmem.avgWrQLen 6.84 # Average write queue length when enqueuing +system.physmem.readRowHits 300749 # Number of row buffer hits during reads +system.physmem.writeRowHits 49371 # Number of row buffer hits during writes +system.physmem.readRowHitRate 63.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.69 # Row buffer hit rate for writes +system.physmem.avgGap 1163520.10 # Average gap between requests +system.physmem.pageHitRate 64.72 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 24.30 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 55005389 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 408886 # Transaction distribution +system.membus.trans_dist::ReadResp 408885 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4324 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4324 # Transaction distribution -system.membus.trans_dist::ReadExReq 66075 # Transaction distribution -system.membus.trans_dist::ReadExResp 66075 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024686 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1024686 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34628352 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34628352 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34628352 # Total data (bytes) +system.membus.trans_dist::UpgradeReq 4262 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4262 # Transaction distribution +system.membus.trans_dist::ReadExReq 66077 # Transaction distribution +system.membus.trans_dist::ReadExResp 66077 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024547 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1024547 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34627840 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34627840 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34627840 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1216897000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1215450500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4442648676 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4442867738 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.branchPred.lookups 445875274 # Number of BP lookups -system.cpu.branchPred.condPredicted 355714891 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 31013117 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 262160312 # Number of BTB lookups -system.cpu.branchPred.BTBHits 234316871 # Number of BTB hits +system.cpu.branchPred.lookups 438247561 # Number of BP lookups +system.cpu.branchPred.condPredicted 350864310 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 30620817 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 248480001 # Number of BTB lookups +system.cpu.branchPred.BTBHits 229339299 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.379231 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 52540791 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2805997 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.296884 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 52915671 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2805331 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -357,239 +357,239 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1267769796 # number of cpu cycles simulated +system.cpu.numCycles 1259070828 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 359604051 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2297734506 # Number of instructions fetch has processed -system.cpu.fetch.Branches 445875274 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 286857662 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 606667357 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 159378109 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 130943287 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 611 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11360 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 133 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 340050056 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11891209 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1225539818 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.573745 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.170795 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 354141008 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2279760487 # Number of instructions fetch has processed +system.cpu.fetch.Branches 438247561 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 282254970 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 601258072 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 157188088 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 134732646 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11340 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 159 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 334734643 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11658370 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1216659156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.575912 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.175897 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 618917347 50.50% 50.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42971146 3.51% 54.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 97897325 7.99% 62.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 56071890 4.58% 66.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 75061628 6.12% 72.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 45063261 3.68% 76.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31435951 2.57% 78.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31903606 2.60% 81.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226217664 18.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 615445856 50.58% 50.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42369042 3.48% 54.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 95794203 7.87% 61.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 57788183 4.75% 66.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 71908380 5.91% 72.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 44699242 3.67% 76.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31096366 2.56% 78.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31485891 2.59% 81.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226071993 18.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1225539818 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.351701 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.812423 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 410024939 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 104223819 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 567090713 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 15899066 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 128301281 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 47087821 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11947 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3044373258 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 26488 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 128301281 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 445072814 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37752394 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 469546 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 545867989 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 68075794 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2962731385 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 107 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4402501 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 53439360 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 9 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2946792223 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14100168268 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12232464769 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 87261724 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1216659156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.348072 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.810669 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 405371714 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 106745319 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 560686974 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17351070 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 126504079 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 44827999 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11498 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3022923361 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 26519 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 126504079 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 441422889 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38085775 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 457741 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 539750608 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 70438064 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2941756877 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 93 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4808697 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 54385480 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2930214829 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14001897517 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12151175707 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 84006834 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 953652133 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20387 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 17854 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 175792199 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 972804227 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 491413736 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 36509550 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 42116928 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2808310459 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27673 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2443543142 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13552705 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 910455744 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2345608138 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6289 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1225539818 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.993850 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.871016 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 937074739 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20556 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18072 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 179295872 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 971747851 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 485687926 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36754298 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 38315968 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2792666421 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27976 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2435152062 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13267287 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 894813451 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2308126927 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6592 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1216659156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.001507 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.873341 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 386142313 31.51% 31.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183212489 14.95% 46.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 204921233 16.72% 63.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 171581285 14.00% 77.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 134431508 10.97% 88.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 92278264 7.53% 95.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37194117 3.03% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12766594 1.04% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3012015 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 380682430 31.29% 31.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183043156 15.04% 46.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 204120943 16.78% 63.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 169552819 13.94% 77.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 132904789 10.92% 87.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 92975981 7.64% 95.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 37964484 3.12% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12393834 1.02% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3020720 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1225539818 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1216659156 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 692354 0.79% 0.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24381 0.03% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55108221 62.64% 63.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 32145057 36.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 714585 0.82% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24381 0.03% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55158409 62.92% 63.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 31764976 36.24% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1110380096 45.44% 45.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11223911 0.46% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876476 0.28% 46.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5502670 0.23% 46.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23408416 0.96% 47.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 840781219 34.41% 81.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 443995061 18.17% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1104246319 45.35% 45.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11223912 0.46% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876479 0.28% 46.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5502438 0.23% 46.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23399832 0.96% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 840060400 34.50% 81.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 442467389 18.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2443543142 # Type of FU issued -system.cpu.iq.rate 1.927434 # Inst issue rate -system.cpu.iq.fu_busy_cnt 87970013 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.036001 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6090822143 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3633185531 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2257760958 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 123326677 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 85675338 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56498576 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2467787139 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 63726016 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 85165626 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2435152062 # Type of FU issued +system.cpu.iq.rate 1.934087 # Inst issue rate +system.cpu.iq.fu_busy_cnt 87662351 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.035999 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6065395375 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3604907621 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2250139997 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 122497543 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 82667139 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56433103 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2459503230 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63311183 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 84462690 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 341417046 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 38150 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1428012 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 214418439 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 340360670 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 9529 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1430281 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 208692629 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 322 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 259 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 128301281 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16032166 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1560767 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2808350603 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 961806 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 972804227 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 491413736 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 17687 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1557116 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2524 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1428012 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 32911757 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1861954 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 34773711 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2367002070 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 794874980 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 76541072 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 126504079 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16045638 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1563592 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2792706843 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1386728 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 971747851 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 485687926 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 17990 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1559989 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2525 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1430281 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 32383306 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1525297 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 33908603 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2359934614 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 794158657 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 75217448 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12471 # number of nop insts executed -system.cpu.iew.exec_refs 1219940656 # number of memory reference insts executed -system.cpu.iew.exec_branches 321608336 # Number of branches executed -system.cpu.iew.exec_stores 425065676 # Number of stores executed -system.cpu.iew.exec_rate 1.867060 # Inst execution rate -system.cpu.iew.wb_sent 2340031230 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2314259534 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1351078205 # num instructions producing a value -system.cpu.iew.wb_consumers 2527156960 # num instructions consuming a value +system.cpu.iew.exec_nop 12446 # number of nop insts executed +system.cpu.iew.exec_refs 1217435243 # number of memory reference insts executed +system.cpu.iew.exec_branches 319532182 # Number of branches executed +system.cpu.iew.exec_stores 423276586 # Number of stores executed +system.cpu.iew.exec_rate 1.874346 # Inst execution rate +system.cpu.iew.wb_sent 2332318779 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2306573100 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1349155886 # num instructions producing a value +system.cpu.iew.wb_consumers 2527422056 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.825457 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.534624 # average fanout of values written-back +system.cpu.iew.wb_rate 1.831965 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.533807 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 923014366 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 907370613 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 31001379 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1097238537 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.718256 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.389874 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 30609580 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1090155077 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.729420 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.397089 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 455331878 41.50% 41.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 289999556 26.43% 67.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95581485 8.71% 76.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 70096070 6.39% 83.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46571745 4.24% 87.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22195585 2.02% 89.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15856765 1.45% 90.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11363497 1.04% 91.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90241956 8.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 449868803 41.27% 41.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288583121 26.47% 67.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95106429 8.72% 76.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 70222159 6.44% 82.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46473802 4.26% 87.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22181225 2.03% 89.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15848603 1.45% 90.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10986529 1.01% 91.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 90884406 8.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1097238537 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1090155077 # Number of insts commited each cycle system.cpu.commit.committedInsts 1384381606 # Number of instructions committed system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -600,222 +600,222 @@ system.cpu.commit.branches 298259106 # Nu system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 90241956 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 90884406 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3815328960 # The number of ROB reads -system.cpu.rob.rob_writes 5745013824 # The number of ROB writes -system.cpu.timesIdled 352945 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 42229978 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3791959297 # The number of ROB reads +system.cpu.rob.rob_writes 5711929091 # The number of ROB writes +system.cpu.timesIdled 353184 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 42411672 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384370590 # Number of Instructions Simulated system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated -system.cpu.cpi 0.915773 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.915773 # CPI: Total CPI of All Threads -system.cpu.ipc 1.091973 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.091973 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11799440532 # number of integer regfile reads -system.cpu.int_regfile_writes 2227507770 # number of integer regfile writes -system.cpu.fp_regfile_reads 68853045 # number of floating regfile reads -system.cpu.fp_regfile_writes 49554235 # number of floating regfile writes -system.cpu.misc_regfile_reads 1367872939 # number of misc regfile reads +system.cpu.cpi 0.909490 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.909490 # CPI: Total CPI of All Threads +system.cpu.ipc 1.099518 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.099518 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11767673862 # number of integer regfile reads +system.cpu.int_regfile_writes 2220512687 # number of integer regfile writes +system.cpu.fp_regfile_reads 68796181 # number of floating regfile reads +system.cpu.fp_regfile_writes 49544953 # number of floating regfile writes +system.cpu.misc_regfile_reads 1364568347 # number of misc regfile reads system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes -system.cpu.toL2Bus.throughput 167773046 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1492868 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1492867 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96315 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 4328 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 4328 # Transaction distribution +system.cpu.toL2Bus.throughput 169029894 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1493831 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1493830 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 96313 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 4265 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 4265 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72518 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72518 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52441 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178974 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3231415 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1539648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104532224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 106071872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 106071872 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 276928 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 929329999 # Layer occupancy (ticks) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54300 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178976 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3233276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1601152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104536256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 106137408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 106137408 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 272896 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 929776999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 42995247 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 44342246 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2368559798 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2368551488 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 22373 # number of replacements -system.cpu.icache.tags.tagsinuse 1644.727747 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 340012575 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24056 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 14134.210800 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 23332 # number of replacements +system.cpu.icache.tags.tagsinuse 1641.273486 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 334698554 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 25017 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13378.844546 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1644.727747 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.803090 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.803090 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 340019150 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 340019150 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 340019150 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 340019150 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 340019150 # number of overall hits -system.cpu.icache.overall_hits::total 340019150 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 30904 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 30904 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 30904 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 30904 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 30904 # number of overall misses -system.cpu.icache.overall_misses::total 30904 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 530577244 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 530577244 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 530577244 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 530577244 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 530577244 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 530577244 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 340050054 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 340050054 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 340050054 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 340050054 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 340050054 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 340050054 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000091 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000091 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000091 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000091 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000091 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000091 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17168.562128 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17168.562128 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17168.562128 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17168.562128 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17168.562128 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17168.562128 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1738 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1641.273486 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801403 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801403 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 334702534 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 334702534 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 334702534 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 334702534 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 334702534 # number of overall hits +system.cpu.icache.overall_hits::total 334702534 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 32107 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 32107 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 32107 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 32107 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 32107 # number of overall misses +system.cpu.icache.overall_misses::total 32107 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 545585992 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 545585992 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 545585992 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 545585992 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 545585992 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 545585992 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 334734641 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 334734641 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 334734641 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 334734641 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 334734641 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 334734641 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000096 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000096 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000096 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000096 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000096 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000096 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16992.742766 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16992.742766 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16992.742766 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16992.742766 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16992.742766 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16992.742766 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2092 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 31 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 38 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 56.064516 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55.052632 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2520 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2520 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2520 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2520 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2520 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2520 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28384 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 28384 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 28384 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 28384 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 28384 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 28384 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 424232750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 424232750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 424232750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 424232750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 424232750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 424232750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000083 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000083 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000083 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000083 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000083 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000083 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14946.193278 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14946.193278 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14946.193278 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14946.193278 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14946.193278 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14946.193278 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2825 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2825 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2825 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2825 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2825 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2825 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 29282 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 29282 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 29282 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 29282 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 29282 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 29282 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 435718750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 435718750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 435718750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 435718750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 435718750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 435718750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14880.088450 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14880.088450 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14880.088450 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14880.088450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14880.088450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14880.088450 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 442189 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32678.484609 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1109448 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 474936 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.335995 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 442179 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32678.084712 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1110777 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 474927 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.338837 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1308.214481 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.900676 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31321.369452 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.039924 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001492 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.955852 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997268 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 21631 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1057987 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1079618 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 96315 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 96315 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 6443 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 6443 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 21631 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1064430 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1086061 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 21631 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1064430 # number of overall hits -system.cpu.l2cache.overall_hits::total 1086061 # number of overall hits +system.cpu.l2cache.tags.occ_blocks::writebacks 1317.536897 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 51.699719 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31308.848096 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.040208 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001578 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.955470 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997256 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 22592 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1058063 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1080655 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 96313 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 96313 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 6441 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 6441 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 22592 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1064504 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1087096 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 22592 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1064504 # number of overall hits +system.cpu.l2cache.overall_hits::total 1087096 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2426 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 406497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 408923 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4324 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4324 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66075 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66075 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 406486 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 408912 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 4262 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 4262 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 66077 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66077 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 2426 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 472572 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 474998 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 472563 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 474989 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2426 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 472572 # number of overall misses -system.cpu.l2cache.overall_misses::total 474998 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175176750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30663807500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30838984250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4756616500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4756616500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 175176750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 35420424000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35595600750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 175176750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 35420424000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35595600750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 24057 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1464484 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1488541 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 96315 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 96315 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4328 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 4328 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 472563 # number of overall misses +system.cpu.l2cache.overall_misses::total 474989 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 176218750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30746587000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30922805750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4757394750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4757394750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 176218750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 35503981750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35680200500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 176218750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 35503981750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35680200500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 25018 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1464549 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1489567 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 96313 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 96313 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4265 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 4265 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 72518 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 72518 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 24057 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1537002 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1561059 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 24057 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1537002 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1561059 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.100844 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277570 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.274714 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999076 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999076 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911153 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911153 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.100844 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.307463 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.304279 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.100844 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.307463 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.304279 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72208.058533 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75434.277498 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75415.137446 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71988.142263 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71988.142263 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72208.058533 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74952.438993 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74938.422372 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72208.058533 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74952.438993 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74938.422372 # average overall miss latency +system.cpu.l2cache.demand_accesses::cpu.inst 25018 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1537067 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1562085 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 25018 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1537067 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1562085 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.096970 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277550 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.274517 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999297 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999297 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911181 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911181 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096970 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.307445 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.304074 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096970 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.307445 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.304074 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72637.572135 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75639.965460 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75622.152810 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71997.741272 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71997.741272 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72637.572135 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75130.684692 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75117.951153 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72637.572135 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75130.684692 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75117.951153 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -827,120 +827,120 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 26 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 26 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 26 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2424 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406471 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 408895 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4324 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 4324 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66075 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66075 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406462 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 408886 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4262 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 4262 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66077 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66077 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2424 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 472546 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 474970 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 472539 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 474963 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2424 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 472546 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 474970 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 144597750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25603608250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25748206000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43244324 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43244324 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3924227000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3924227000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 144597750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29527835250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29672433000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 144597750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29527835250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29672433000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100761 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277552 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274695 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999076 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999076 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911153 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911153 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100761 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307447 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.304261 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100761 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307447 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.304261 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59652.537129 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62989.999902 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62970.214847 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.data 472539 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 474963 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145637750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25686513500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25832151250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42624262 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42624262 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3924978750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3924978750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145637750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29611492250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29757130000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145637750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29611492250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29757130000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.096890 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277534 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274500 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999297 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999297 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911181 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911181 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096890 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307429 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.304057 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096890 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307429 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.304057 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60081.580033 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63195.362666 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63176.903220 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59390.495649 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59390.495649 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59652.537129 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62486.689656 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62472.225614 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59652.537129 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62486.689656 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62472.225614 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59400.074913 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59400.074913 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62664.652547 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62651.469693 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62664.652547 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62651.469693 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1532905 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.387385 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 971436889 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1537001 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 632.033999 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 400661250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.387385 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999606 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999606 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 695310256 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 695310256 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276092959 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276092959 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9998 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9998 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 1532970 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.376677 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 971409274 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1537066 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 631.989306 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 400505250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.376677 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999604 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999604 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 695282689 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 695282689 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276093049 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276093049 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10000 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10000 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 971403215 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 971403215 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 971403215 # number of overall hits -system.cpu.dcache.overall_hits::total 971403215 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1954136 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1954136 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 842719 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 842719 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 971375738 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 971375738 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 971375738 # number of overall hits +system.cpu.dcache.overall_hits::total 971375738 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1954115 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1954115 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 842629 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 842629 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2796855 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2796855 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2796855 # number of overall misses -system.cpu.dcache.overall_misses::total 2796855 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80332980069 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80332980069 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58617620770 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58617620770 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 225000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 225000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 138950600839 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 138950600839 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 138950600839 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 138950600839 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 697264392 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 697264392 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2796744 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2796744 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2796744 # number of overall misses +system.cpu.dcache.overall_misses::total 2796744 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80415300557 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80415300557 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 58619884416 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 58619884416 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 211750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 211750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 139035184973 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 139035184973 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 139035184973 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 139035184973 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 697236804 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 697236804 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10001 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10001 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 974200070 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 974200070 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 974200070 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 974200070 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 974172482 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 974172482 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 974172482 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 974172482 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002803 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002803 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003043 # miss rate for WriteReq accesses @@ -951,68 +951,68 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002871 system.cpu.dcache.demand_miss_rate::total 0.002871 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002871 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002871 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41109.206355 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41109.206355 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69557.730121 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69557.730121 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 75000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 75000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49681.017013 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49681.017013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 49681.017013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 49681.017013 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2430 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 892 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 56 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 86 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.392857 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10.372093 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41151.774874 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41151.774874 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69567.845892 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69567.845892 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70583.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70583.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 49713.232592 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 49713.232592 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 49713.232592 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 49713.232592 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2265 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 939 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 52 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.557692 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10.550562 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96315 # number of writebacks -system.cpu.dcache.writebacks::total 96315 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489650 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 489650 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765875 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 765875 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 96313 # number of writebacks +system.cpu.dcache.writebacks::total 96313 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489564 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 489564 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765848 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 765848 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1255525 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1255525 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1255525 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1255525 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464486 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464486 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76844 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76844 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541330 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541330 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541330 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541330 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42708562776 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 42708562776 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4994223926 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4994223926 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47702786702 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 47702786702 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47702786702 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 47702786702 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002100 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002100 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 1255412 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1255412 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1255412 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1255412 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464551 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464551 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76781 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76781 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541332 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541332 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541332 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541332 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42792232024 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 42792232024 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4993494488 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4993494488 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47785726512 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 47785726512 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47785726512 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47785726512 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002101 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002101 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001582 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001582 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29162.834452 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29162.834452 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64991.722529 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64991.722529 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30949.106747 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30949.106747 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30949.106747 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30949.106747 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.669766 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.669766 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65035.549003 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65035.549003 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index dd99e1fcc..d10bd65d5 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -56,6 +60,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fetchBuffSize=4 function_trace=false function_trace_start=0 @@ -90,6 +95,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -105,6 +111,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -127,11 +134,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -140,6 +149,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -162,17 +172,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -181,6 +195,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -203,12 +218,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -218,6 +235,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -227,7 +245,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 @@ -241,11 +260,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -265,6 +286,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -276,17 +298,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 4f4f69eed..fc01eaffa 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.043690 # Nu sim_ticks 43690025000 # Number of ticks simulated final_tick 43690025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111109 # Simulator instruction rate (inst/s) -host_op_rate 111109 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54950396 # Simulator tick rate (ticks/s) -host_mem_usage 264576 # Number of bytes of host memory used -host_seconds 795.08 # Real time elapsed on the host +host_inst_rate 91247 # Simulator instruction rate (inst/s) +host_op_rate 91247 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45127446 # Simulator tick rate (ticks/s) +host_mem_usage 283120 # Number of bytes of host memory used +host_seconds 968.15 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory @@ -327,9 +327,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 17888768 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17888768 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1218630500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1218631000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 1521664000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1521663500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.5 # Layer utilization (%) system.cpu.branchPred.lookups 18742723 # Number of BP lookups system.cpu.branchPred.condPredicted 12318363 # Number of conditional branches predicted @@ -395,7 +395,7 @@ system.cpu.execution_unit.executions 44777932 # Nu system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77196543 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77196544 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 232942 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 17804423 # Number of cycles cpu's stages were not processed @@ -577,14 +577,14 @@ system.cpu.l2cache.overall_misses::total 165515 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 550125750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2043322000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 2593447750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13452980750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 13452980750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13452980250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 13452980250 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 550125750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15496302750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16046428500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15496302250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16046428000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 550125750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15496302750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16046428500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15496302250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16046428000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 86417 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 146994 # number of ReadReq accesses(hits+misses) @@ -612,14 +612,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.569244 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77449.774743 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74243.223603 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 74901.018051 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102780.814042 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102780.814042 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102780.810222 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102780.810222 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77449.774743 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 97822.783312 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 96948.485032 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 97822.780156 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 96948.482011 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77449.774743 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 97822.783312 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 96948.485032 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 97822.780156 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 96948.482011 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -700,14 +700,14 @@ system.cpu.dcache.demand_misses::cpu.data 1135132 # n system.cpu.dcache.demand_misses::total 1135132 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1135132 # number of overall misses system.cpu.dcache.overall_misses::total 1135132 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5098666734 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5098666734 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 85921765880 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 85921765880 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91020432614 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91020432614 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91020432614 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91020432614 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5098666234 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5098666234 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 85921765380 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 85921765380 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91020431614 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91020431614 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91020431614 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91020431614 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -724,14 +724,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52920.377950 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 52920.377950 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82713.634839 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 82713.634839 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80184.888290 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80184.888290 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80184.888290 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80184.888290 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52920.372761 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 52920.372761 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82713.634358 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 82713.634358 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80184.887409 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80184.887409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80184.887409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80184.887409 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 5745787 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 77 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 116736 # number of cycles access was blocked @@ -760,12 +760,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 204346 system.cpu.dcache.overall_mshr_misses::total 204346 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2437943016 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2437943016 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13723509265 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13723509265 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16161452281 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16161452281 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16161452281 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16161452281 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13723508765 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13723508765 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16161451781 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16161451781 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16161451781 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16161451781 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -776,12 +776,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40120.182602 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40120.182602 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95580.925373 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95580.925373 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79088.664721 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 79088.664721 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79088.664721 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 79088.664721 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95580.921890 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95580.921890 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79088.662274 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 79088.662274 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79088.662274 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 79088.662274 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 684c8c0e1..08705e6b8 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,17 +518,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -482,6 +541,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -504,12 +564,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -528,7 +591,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 @@ -542,11 +606,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -566,6 +632,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -577,17 +644,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 5daeaeb73..63551bce4 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024874 # Number of seconds simulated -sim_ticks 24873813500 # Number of ticks simulated -final_tick 24873813500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024877 # Number of seconds simulated +sim_ticks 24876941500 # Number of ticks simulated +final_tick 24876941500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165069 # Simulator instruction rate (inst/s) -host_op_rate 165069 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51586823 # Simulator tick rate (ticks/s) -host_mem_usage 265596 # Number of bytes of host memory used -host_seconds 482.17 # Real time elapsed on the host +host_inst_rate 131928 # Simulator instruction rate (inst/s) +host_op_rate 131928 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41235030 # Simulator tick rate (ticks/s) +host_mem_usage 285168 # Number of bytes of host memory used +host_seconds 603.30 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 489600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10153536 # Number of bytes read from this memory -system.physmem.bytes_read::total 10643136 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 489600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 489600 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7297088 # Number of bytes written to this memory -system.physmem.bytes_written::total 7297088 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7650 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158649 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166299 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114017 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114017 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19683351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 408201822 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 427885173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19683351 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19683351 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 293364264 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 293364264 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 293364264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19683351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 408201822 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 721249438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166299 # Number of read requests accepted -system.physmem.writeReqs 114017 # Number of write requests accepted -system.physmem.readBursts 166299 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114017 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10643008 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue -system.physmem.bytesWritten 7296896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10643136 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7297088 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 490624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10154752 # Number of bytes read from this memory +system.physmem.bytes_read::total 10645376 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 490624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 490624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7297216 # Number of bytes written to this memory +system.physmem.bytes_written::total 7297216 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7666 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158668 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166334 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114019 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114019 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19722039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 408199376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 427921415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19722039 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19722039 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 293332522 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 293332522 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 293332522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19722039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 408199376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 721253937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166334 # Number of read requests accepted +system.physmem.writeReqs 114019 # Number of write requests accepted +system.physmem.readBursts 166334 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114019 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10645312 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 64 # Total number of bytes read from write queue +system.physmem.bytesWritten 7297024 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10645376 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7297216 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10432 # Per bank write bursts -system.physmem.perBankRdBursts::1 10453 # Per bank write bursts +system.physmem.perBankRdBursts::0 10436 # Per bank write bursts +system.physmem.perBankRdBursts::1 10466 # Per bank write bursts system.physmem.perBankRdBursts::2 10310 # Per bank write bursts -system.physmem.perBankRdBursts::3 10056 # Per bank write bursts +system.physmem.perBankRdBursts::3 10058 # Per bank write bursts system.physmem.perBankRdBursts::4 10431 # Per bank write bursts -system.physmem.perBankRdBursts::5 10400 # Per bank write bursts +system.physmem.perBankRdBursts::5 10410 # Per bank write bursts system.physmem.perBankRdBursts::6 9846 # Per bank write bursts -system.physmem.perBankRdBursts::7 10320 # Per bank write bursts -system.physmem.perBankRdBursts::8 10615 # Per bank write bursts -system.physmem.perBankRdBursts::9 10642 # Per bank write bursts -system.physmem.perBankRdBursts::10 10549 # Per bank write bursts -system.physmem.perBankRdBursts::11 10234 # Per bank write bursts -system.physmem.perBankRdBursts::12 10280 # Per bank write bursts -system.physmem.perBankRdBursts::13 10614 # Per bank write bursts +system.physmem.perBankRdBursts::7 10323 # Per bank write bursts +system.physmem.perBankRdBursts::8 10612 # Per bank write bursts +system.physmem.perBankRdBursts::9 10641 # Per bank write bursts +system.physmem.perBankRdBursts::10 10552 # Per bank write bursts +system.physmem.perBankRdBursts::11 10231 # Per bank write bursts +system.physmem.perBankRdBursts::12 10282 # Per bank write bursts +system.physmem.perBankRdBursts::13 10619 # Per bank write bursts system.physmem.perBankRdBursts::14 10489 # Per bank write bursts -system.physmem.perBankRdBursts::15 10626 # Per bank write bursts +system.physmem.perBankRdBursts::15 10627 # Per bank write bursts system.physmem.perBankWrBursts::0 7083 # Per bank write bursts -system.physmem.perBankWrBursts::1 7257 # Per bank write bursts -system.physmem.perBankWrBursts::2 7256 # Per bank write bursts -system.physmem.perBankWrBursts::3 6997 # Per bank write bursts +system.physmem.perBankWrBursts::1 7258 # Per bank write bursts +system.physmem.perBankWrBursts::2 7255 # Per bank write bursts +system.physmem.perBankWrBursts::3 6998 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts system.physmem.perBankWrBursts::5 7177 # Per bank write bursts -system.physmem.perBankWrBursts::6 6772 # Per bank write bursts -system.physmem.perBankWrBursts::7 7093 # Per bank write bursts -system.physmem.perBankWrBursts::8 7227 # Per bank write bursts +system.physmem.perBankWrBursts::6 6771 # Per bank write bursts +system.physmem.perBankWrBursts::7 7092 # Per bank write bursts +system.physmem.perBankWrBursts::8 7228 # Per bank write bursts system.physmem.perBankWrBursts::9 6941 # Per bank write bursts -system.physmem.perBankWrBursts::10 7084 # Per bank write bursts -system.physmem.perBankWrBursts::11 6990 # Per bank write bursts +system.physmem.perBankWrBursts::10 7087 # Per bank write bursts +system.physmem.perBankWrBursts::11 6989 # Per bank write bursts system.physmem.perBankWrBursts::12 6966 # Per bank write bursts system.physmem.perBankWrBursts::13 7287 # Per bank write bursts system.physmem.perBankWrBursts::14 7286 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 24873779500 # Total gap between requests +system.physmem.totGap 24876907500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166299 # Read request sizes (log2) +system.physmem.readPktSize::6 166334 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114017 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 71536 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56861 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 31949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5942 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114019 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 71615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56813 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 31969 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -127,233 +127,232 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4811 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 4806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 52112 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 344.243169 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 164.634788 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 670.449971 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 22509 43.19% 43.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 7813 14.99% 58.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4251 8.16% 66.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 3108 5.96% 72.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 2227 4.27% 76.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1678 3.22% 79.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1376 2.64% 82.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1167 2.24% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 816 1.57% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 658 1.26% 87.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 508 0.97% 88.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 506 0.97% 89.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 390 0.75% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 297 0.57% 90.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 306 0.59% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 440 0.84% 92.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 200 0.38% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 185 0.36% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 164 0.31% 93.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 351 0.67% 93.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 222 0.43% 94.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 266 0.51% 94.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 128 0.25% 95.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 805 1.54% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 220 0.42% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 67 0.13% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 43 0.08% 97.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 225 0.43% 97.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 103 0.20% 97.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 52 0.10% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 344.289837 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.462354 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 671.053187 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 22533 43.24% 43.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 7819 15.00% 58.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4221 8.10% 66.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 3179 6.10% 72.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2215 4.25% 76.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1656 3.18% 79.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1349 2.59% 82.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1165 2.24% 84.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 821 1.58% 86.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 640 1.23% 87.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 526 1.01% 88.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 503 0.97% 89.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 384 0.74% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 279 0.54% 90.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 312 0.60% 91.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 436 0.84% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 202 0.39% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 182 0.35% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 166 0.32% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 352 0.68% 93.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 220 0.42% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 250 0.48% 94.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 131 0.25% 95.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 818 1.57% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 224 0.43% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 79 0.15% 97.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 35 0.07% 97.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 217 0.42% 97.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 119 0.23% 97.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 48 0.09% 98.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::1984-1985 34 0.07% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 84 0.16% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 57 0.11% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 36 0.07% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 83 0.16% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 65 0.12% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 27 0.05% 98.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::2240-2241 17 0.03% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 55 0.11% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 59 0.11% 98.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::2368-2369 39 0.07% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 25 0.05% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 21 0.04% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 30 0.06% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 12 0.02% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 17 0.03% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 21 0.04% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 18 0.03% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 16 0.03% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 18 0.03% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 24 0.05% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 24 0.05% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 13 0.02% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 9 0.02% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 11 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 11 0.02% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 10 0.02% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 6 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 11 0.02% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 12 0.02% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 7 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 11 0.02% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 7 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 10 0.02% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 9 0.02% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 10 0.02% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 8 0.02% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 13 0.02% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 3 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 6 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 5 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 8 0.02% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 4 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 7 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 3 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 6 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 3 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 10 0.02% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 4 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 5 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 6 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 5 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 4 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 3 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 6 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 6 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 3 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 3 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 5 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 8 0.02% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 2 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 7 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 22 0.04% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 18 0.03% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 32 0.06% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 16 0.03% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 9 0.02% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 20 0.04% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 18 0.03% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 13 0.02% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 16 0.03% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 32 0.06% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 16 0.03% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 10 0.02% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 12 0.02% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 13 0.02% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 13 0.02% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 4 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 12 0.02% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 12 0.02% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 14 0.03% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 6 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 9 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 11 0.02% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 10 0.02% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 10 0.02% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 14 0.03% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 6 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 9 0.02% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 6 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 11 0.02% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 4 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 4 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 9 0.02% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 5 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 5 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 6 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 3 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 4 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 2 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 6 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 3 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 6 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 3 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 4 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 6 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 5 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 5 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 3 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 9 0.02% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 6 0.01% 99.73% # Bytes accessed per row activation system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.73% # Bytes accessed per row activation system.physmem.bytesPerActivate::6848-6849 4 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 5 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 3 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 3 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 8 0.02% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 3 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 4 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 10 0.02% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 4 0.01% 99.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 2 0.00% 99.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::8064-8065 4 0.01% 99.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 15 0.03% 99.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 82 0.16% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 52112 # Bytes accessed per row activation -system.physmem.totQLat 6321612000 # Total ticks spent queuing -system.physmem.totMemAccLat 8667027000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 831485000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1513930000 # Total ticks spent accessing banks -system.physmem.avgQLat 38013.99 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 9103.77 # Average bank access latency per DRAM burst +system.physmem.totQLat 6294270000 # Total ticks spent queuing +system.physmem.totMemAccLat 8641432500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 831665000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1515497500 # Total ticks spent accessing banks +system.physmem.avgQLat 37841.38 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 9111.23 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52117.76 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 427.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 293.36 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 427.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 293.36 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 51952.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 427.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 293.32 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 427.92 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 293.33 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 5.63 # Data bus utilization in percentage system.physmem.busUtilRead 3.34 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 2.29 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.35 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.68 # Average write queue length when enqueuing -system.physmem.readRowHits 152202 # Number of row buffer hits during reads -system.physmem.writeRowHits 75997 # Number of row buffer hits during writes +system.physmem.avgWrQLen 9.70 # Average write queue length when enqueuing +system.physmem.readRowHits 152220 # Number of row buffer hits during reads +system.physmem.writeRowHits 76017 # Number of row buffer hits during writes system.physmem.readRowHitRate 91.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.65 # Row buffer hit rate for writes -system.physmem.avgGap 88734.78 # Average gap between requests +system.physmem.writeRowHitRate 66.67 # Row buffer hit rate for writes +system.physmem.avgGap 88734.23 # Average gap between requests system.physmem.pageHitRate 81.41 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 12.04 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 721249438 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 35493 # Transaction distribution -system.membus.trans_dist::ReadResp 35493 # Transaction distribution -system.membus.trans_dist::Writeback 114017 # Transaction distribution -system.membus.trans_dist::ReadExReq 130806 # Transaction distribution -system.membus.trans_dist::ReadExResp 130806 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446615 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 446615 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940224 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17940224 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17940224 # Total data (bytes) +system.physmem.prechargeAllPercent 11.97 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 721253937 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 35533 # Transaction distribution +system.membus.trans_dist::ReadResp 35533 # Transaction distribution +system.membus.trans_dist::Writeback 114019 # Transaction distribution +system.membus.trans_dist::ReadExReq 130801 # Transaction distribution +system.membus.trans_dist::ReadExResp 130801 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446687 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 446687 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17942592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 17942592 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17942592 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1242127000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1242193000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 5.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 1539178500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1539567000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.2 # Layer utilization (%) -system.cpu.branchPred.lookups 16532535 # Number of BP lookups -system.cpu.branchPred.condPredicted 10677865 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 412540 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11187771 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7331268 # Number of BTB hits +system.cpu.branchPred.lookups 16535475 # Number of BP lookups +system.cpu.branchPred.condPredicted 10680150 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 413128 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11281450 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7332394 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.529300 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1986493 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 41581 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 64.995138 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1986702 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 41528 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22399036 # DTB read hits -system.cpu.dtb.read_misses 220951 # DTB read misses -system.cpu.dtb.read_acv 40 # DTB read access violations -system.cpu.dtb.read_accesses 22619987 # DTB read accesses -system.cpu.dtb.write_hits 15703469 # DTB write hits -system.cpu.dtb.write_misses 40937 # DTB write misses -system.cpu.dtb.write_acv 5 # DTB write access violations -system.cpu.dtb.write_accesses 15744406 # DTB write accesses -system.cpu.dtb.data_hits 38102505 # DTB hits -system.cpu.dtb.data_misses 261888 # DTB misses -system.cpu.dtb.data_acv 45 # DTB access violations -system.cpu.dtb.data_accesses 38364393 # DTB accesses -system.cpu.itb.fetch_hits 13899355 # ITB hits -system.cpu.itb.fetch_misses 34906 # ITB misses +system.cpu.dtb.read_hits 22396974 # DTB read hits +system.cpu.dtb.read_misses 220986 # DTB read misses +system.cpu.dtb.read_acv 45 # DTB read access violations +system.cpu.dtb.read_accesses 22617960 # DTB read accesses +system.cpu.dtb.write_hits 15703419 # DTB write hits +system.cpu.dtb.write_misses 41132 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 15744551 # DTB write accesses +system.cpu.dtb.data_hits 38100393 # DTB hits +system.cpu.dtb.data_misses 262118 # DTB misses +system.cpu.dtb.data_acv 49 # DTB access violations +system.cpu.dtb.data_accesses 38362511 # DTB accesses +system.cpu.itb.fetch_hits 13901400 # ITB hits +system.cpu.itb.fetch_misses 35038 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13934261 # ITB accesses +system.cpu.itb.fetch_accesses 13936438 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -367,139 +366,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 49747630 # number of cpu cycles simulated +system.cpu.numCycles 49753887 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15785028 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105317585 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16532535 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9317761 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19533050 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1994568 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7608263 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7898 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 310217 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 15785706 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105319377 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16535475 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9319096 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19535939 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1995771 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7614067 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7763 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 310803 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 76 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13899355 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 208294 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44693564 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.356437 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.120216 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 13901400 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 208167 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44703895 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.355933 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.120018 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25160514 56.30% 56.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1525973 3.41% 59.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1366086 3.06% 62.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1510374 3.38% 66.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4139884 9.26% 75.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1847459 4.13% 79.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 671184 1.50% 81.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1072337 2.40% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7399753 16.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25167956 56.30% 56.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1528006 3.42% 59.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1366750 3.06% 62.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1512499 3.38% 66.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4138976 9.26% 75.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1846420 4.13% 79.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 671442 1.50% 81.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1071050 2.40% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7400796 16.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44693564 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.332328 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.117037 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16872770 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7137515 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18556178 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 782832 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1344269 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3743968 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 106931 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103592319 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 303311 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1344269 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17342531 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4850765 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 84983 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18829662 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2241354 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102344042 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 512 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2574 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2122740 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61629886 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123330813 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123015128 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 315684 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44703895 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.332345 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.116807 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16874554 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7142634 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18558802 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 783225 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1344680 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3743647 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 107085 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103596223 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 302671 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1344680 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17346175 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4853031 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 85455 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18830704 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2243850 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102345999 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 509 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2584 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2124299 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61632193 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123331325 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123012632 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 318692 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9083005 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5524 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5522 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4827061 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23228738 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16269123 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1186061 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 452179 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90719899 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5267 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88414674 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 94911 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10680066 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4660295 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 684 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44693564 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.978242 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.110252 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9085312 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5523 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5521 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4830878 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23230757 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16269125 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1199559 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 452349 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90724395 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5268 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88415459 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 94171 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10689316 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4663748 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 685 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44703895 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.977802 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.109542 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16504766 36.93% 36.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6842289 15.31% 52.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5576642 12.48% 64.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4760179 10.65% 75.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4735432 10.60% 85.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2623142 5.87% 91.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1921443 4.30% 96.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1284900 2.87% 99.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 444771 1.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16507369 36.93% 36.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6840922 15.30% 52.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5582133 12.49% 64.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4775843 10.68% 75.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4724672 10.57% 85.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2622986 5.87% 91.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1924028 4.30% 96.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1282580 2.87% 99.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 443362 0.99% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44693564 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44703895 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 126888 6.81% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 786366 42.17% 48.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 951332 51.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 126532 6.78% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 788261 42.26% 49.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 950494 50.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49347874 55.81% 55.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43826 0.05% 55.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49348241 55.81% 55.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43886 0.05% 55.86% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 120827 0.14% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 120926 0.14% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 58 0.00% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38966 0.04% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121319 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121135 0.14% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38977 0.04% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued @@ -521,84 +520,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22848043 25.84% 82.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15894065 17.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22847876 25.84% 82.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15893880 17.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88414674 # Type of FU issued -system.cpu.iq.rate 1.777264 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1864586 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021089 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222880329 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101013312 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86537625 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 602080 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 409925 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294164 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 89978136 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 301124 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1470512 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88415459 # Type of FU issued +system.cpu.iq.rate 1.777056 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1865287 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021097 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222890546 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101022608 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86533727 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 603725 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 414375 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294393 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 89978801 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 301945 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1469946 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2952100 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4699 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18249 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1655746 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2954119 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4771 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18244 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1655748 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2987 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 95590 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3011 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 95424 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1344269 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3728175 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 74875 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100203568 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 217116 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23228738 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16269123 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5267 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 49826 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6538 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18249 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 191969 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 160202 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 352171 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87579420 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22623199 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 835254 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1344680 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3730457 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 74850 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100207935 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 218697 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23230757 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16269125 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5268 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49823 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6563 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18244 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 192844 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 159688 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 352532 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87575579 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22621211 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 839880 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9478402 # number of nop insts executed -system.cpu.iew.exec_refs 38367932 # number of memory reference insts executed -system.cpu.iew.exec_branches 15082234 # Number of branches executed -system.cpu.iew.exec_stores 15744733 # Number of stores executed -system.cpu.iew.exec_rate 1.760474 # Inst execution rate -system.cpu.iew.wb_sent 87221630 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86831789 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33348400 # num instructions producing a value -system.cpu.iew.wb_consumers 43473071 # num instructions consuming a value +system.cpu.iew.exec_nop 9478272 # number of nop insts executed +system.cpu.iew.exec_refs 38366084 # number of memory reference insts executed +system.cpu.iew.exec_branches 15081989 # Number of branches executed +system.cpu.iew.exec_stores 15744873 # Number of stores executed +system.cpu.iew.exec_rate 1.760176 # Inst execution rate +system.cpu.iew.wb_sent 87218892 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86828120 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33348545 # num instructions producing a value +system.cpu.iew.wb_consumers 43472168 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.745446 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.767105 # average fanout of values written-back +system.cpu.iew.wb_rate 1.745152 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.767124 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8866636 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8870802 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 307777 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43349295 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.037880 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.791190 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 308267 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43359215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.037414 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.791048 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20524240 47.35% 47.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7032147 16.22% 63.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3350548 7.73% 71.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2057076 4.75% 76.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2049777 4.73% 80.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1169910 2.70% 83.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1109421 2.56% 86.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 718391 1.66% 87.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5337785 12.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20533772 47.36% 47.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7032064 16.22% 63.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3351851 7.73% 71.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2056930 4.74% 76.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2048633 4.72% 80.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1170984 2.70% 83.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1108500 2.56% 86.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718184 1.66% 87.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5338297 12.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43349295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43359215 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -609,212 +608,212 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5337785 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5338297 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 133901476 # The number of ROB reads -system.cpu.rob.rob_writes 195761663 # The number of ROB writes -system.cpu.timesIdled 83653 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5054066 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133915050 # The number of ROB reads +system.cpu.rob.rob_writes 195770285 # The number of ROB writes +system.cpu.timesIdled 83590 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5049992 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.625035 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.625035 # CPI: Total CPI of All Threads -system.cpu.ipc 1.599911 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.599911 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115904116 # number of integer regfile reads -system.cpu.int_regfile_writes 57506232 # number of integer regfile writes -system.cpu.fp_regfile_reads 249599 # number of floating regfile reads -system.cpu.fp_regfile_writes 239957 # number of floating regfile writes -system.cpu.misc_regfile_reads 38110 # number of misc regfile reads +system.cpu.cpi 0.625114 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.625114 # CPI: Total CPI of All Threads +system.cpu.ipc 1.599709 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.599709 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115901393 # number of integer regfile reads +system.cpu.int_regfile_writes 57502981 # number of integer regfile writes +system.cpu.fp_regfile_reads 249622 # number of floating regfile reads +system.cpu.fp_regfile_writes 240154 # number of floating regfile writes +system.cpu.misc_regfile_reads 38048 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1204474416 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 155769 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 155768 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168935 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143420 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143420 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 187275 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580037 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 767312 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5992768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23967104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29959872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29959872 # Total data (bytes) +system.cpu.toL2Bus.throughput 1204366702 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 155800 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 155799 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168930 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143411 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143411 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 187341 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580010 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 767351 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5994880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23966080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 29960960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29960960 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 402997000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 403000500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 141831227 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 141888472 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 326236500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 326227248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 91589 # number of replacements -system.cpu.icache.tags.tagsinuse 1926.117780 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13792950 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 93637 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.302348 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 20015752250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1926.117780 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.940487 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.940487 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13792950 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13792950 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13792950 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13792950 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13792950 # number of overall hits -system.cpu.icache.overall_hits::total 13792950 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 106403 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 106403 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 106403 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 106403 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 106403 # number of overall misses -system.cpu.icache.overall_misses::total 106403 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2026702474 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2026702474 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2026702474 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2026702474 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2026702474 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2026702474 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13899353 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13899353 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13899353 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13899353 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13899353 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13899353 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007655 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007655 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007655 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007655 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007655 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007655 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19047.418531 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19047.418531 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19047.418531 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19047.418531 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19047.418531 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19047.418531 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 673 # number of cycles access was blocked +system.cpu.icache.tags.replacements 91622 # number of replacements +system.cpu.icache.tags.tagsinuse 1926.124790 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13794941 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 93670 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 147.271709 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 20019697250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1926.124790 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.940491 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.940491 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13794941 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13794941 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13794941 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13794941 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13794941 # number of overall hits +system.cpu.icache.overall_hits::total 13794941 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 106457 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 106457 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 106457 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 106457 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 106457 # number of overall misses +system.cpu.icache.overall_misses::total 106457 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2019960968 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2019960968 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2019960968 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2019960968 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2019960968 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2019960968 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13901398 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13901398 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13901398 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13901398 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13901398 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13901398 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007658 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007658 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007658 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007658 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007658 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007658 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18974.430690 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18974.430690 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18974.430690 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18974.430690 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18974.430690 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18974.430690 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 691 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 44.866667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 43.187500 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12765 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12765 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12765 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12765 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12765 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12765 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93638 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 93638 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 93638 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 93638 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 93638 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 93638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1554482273 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1554482273 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1554482273 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1554482273 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1554482273 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1554482273 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006737 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006737 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006737 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006737 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006737 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006737 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16600.976879 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16600.976879 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16600.976879 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16600.976879 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16600.976879 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16600.976879 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12786 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 12786 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 12786 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 12786 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 12786 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 12786 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93671 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 93671 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 93671 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 93671 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 93671 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 93671 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1551735028 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1551735028 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1551735028 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1551735028 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1551735028 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1551735028 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006738 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006738 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006738 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006738 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006738 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006738 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16565.799746 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16565.799746 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16565.799746 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16565.799746 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16565.799746 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16565.799746 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 132395 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30693.596872 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 159984 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164457 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.972801 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 132428 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30694.665852 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 159970 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 164497 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.972480 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26343.566994 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2104.284685 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 2245.745192 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.803942 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064218 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.068535 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.936694 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 85987 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 34288 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 120275 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168935 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168935 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12614 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12614 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 85987 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46902 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 132889 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 85987 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46902 # number of overall hits -system.cpu.l2cache.overall_hits::total 132889 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 7651 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 27843 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 35494 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130806 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130806 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 7651 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158649 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 166300 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 7651 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158649 # number of overall misses -system.cpu.l2cache.overall_misses::total 166300 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 600341000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2116503000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2716844000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13805964000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 13805964000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 600341000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15922467000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16522808000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 600341000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15922467000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16522808000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 93638 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 62131 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 155769 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 168935 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 168935 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143420 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143420 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 93638 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 205551 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 299189 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 93638 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 205551 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 299189 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.081708 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448134 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.227863 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912049 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.912049 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.081708 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.771823 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.555836 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.081708 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.771823 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.555836 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78465.690759 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76015.623316 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76543.753874 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105545.341957 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105545.341957 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78465.690759 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 100362.857629 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 99355.429946 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78465.690759 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 100362.857629 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 99355.429946 # average overall miss latency +system.cpu.l2cache.tags.occ_blocks::writebacks 26341.005950 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2105.517354 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 2248.142548 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.803864 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064255 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.068608 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.936727 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 86004 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 34262 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 120266 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 168930 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 168930 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12610 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12610 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 86004 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 46872 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 132876 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 86004 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 46872 # number of overall hits +system.cpu.l2cache.overall_hits::total 132876 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 7667 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 27867 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 35534 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 130801 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 130801 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 7667 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158668 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 166335 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 7667 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158668 # number of overall misses +system.cpu.l2cache.overall_misses::total 166335 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 597389250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2119099250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2716488500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13782092500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 13782092500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 597389250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15901191750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16498581000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 597389250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15901191750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16498581000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 93671 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 62129 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 155800 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 168930 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168930 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143411 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143411 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 93671 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 205540 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 299211 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 93671 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 205540 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 299211 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.081850 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448535 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.228074 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912071 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.912071 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.081850 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.771957 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.555912 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.081850 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.771957 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.555912 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77916.949263 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76043.321850 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76447.585411 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105366.874106 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105366.874106 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77916.949263 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 100216.752905 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 99188.871855 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77916.949263 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 100216.752905 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 99188.871855 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -823,164 +822,164 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114017 # number of writebacks -system.cpu.l2cache.writebacks::total 114017 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7651 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27843 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 35494 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130806 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130806 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7651 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158649 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 166300 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7651 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158649 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 166300 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 503573000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1760000500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2263573500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12201880000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12201880000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 503573000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13961880500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14465453500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 503573000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13961880500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14465453500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081708 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448134 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.227863 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912049 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912049 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081708 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771823 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.555836 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081708 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771823 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.555836 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65817.932296 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63211.597170 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63773.412408 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93282.265340 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93282.265340 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65817.932296 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88004.844027 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86984.085989 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65817.932296 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88004.844027 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86984.085989 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 114019 # number of writebacks +system.cpu.l2cache.writebacks::total 114019 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7667 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27867 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 35534 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130801 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130801 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7667 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158668 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166335 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7667 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158668 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166335 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 500389250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1762290750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2262680000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12178041500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12178041500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 500389250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13940332250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14440721500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 500389250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13940332250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14440721500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081850 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448535 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228074 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912071 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912071 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081850 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771957 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.555912 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081850 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771957 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.555912 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65265.325421 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63239.342233 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63676.478865 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93103.581012 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93103.581012 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65265.325421 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87858.498563 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86817.095019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65265.325421 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87858.498563 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86817.095019 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 201455 # number of replacements -system.cpu.dcache.tags.tagsinuse 4074.008979 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34185233 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205551 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 166.310225 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 201444 # number of replacements +system.cpu.dcache.tags.tagsinuse 4074.011744 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34183901 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205540 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 166.312645 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 220306250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4074.008979 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.994631 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994631 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20611135 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20611135 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574043 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574043 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 55 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 55 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34185178 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34185178 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34185178 # number of overall hits -system.cpu.dcache.overall_hits::total 34185178 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 267491 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 267491 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1039334 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1039334 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1306825 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1306825 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1306825 # number of overall misses -system.cpu.dcache.overall_misses::total 1306825 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 16297490000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 16297490000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 89003554001 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 89003554001 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 105301044001 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 105301044001 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 105301044001 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 105301044001 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20878626 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20878626 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 4074.011744 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.994632 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994632 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20609776 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20609776 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574069 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574069 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 56 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 56 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34183845 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34183845 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34183845 # number of overall hits +system.cpu.dcache.overall_hits::total 34183845 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 267478 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 267478 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1039308 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1039308 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1306786 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1306786 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1306786 # number of overall misses +system.cpu.dcache.overall_misses::total 1306786 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 16319754498 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 16319754498 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 88798095012 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 88798095012 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 105117849510 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 105117849510 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 105117849510 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 105117849510 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20877254 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20877254 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 55 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 55 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35492003 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35492003 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35492003 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35492003 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 56 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 56 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35490631 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35490631 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35490631 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35490631 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012812 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012812 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071122 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071122 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036820 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036820 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036820 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036820 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60927.246150 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60927.246150 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85635.179837 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 85635.179837 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80577.769786 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80577.769786 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80577.769786 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80577.769786 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5154697 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071120 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071120 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036821 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036821 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036821 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036821 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61013.445958 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61013.445958 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85439.633883 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 85439.633883 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80439.987504 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80439.987504 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80439.987504 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80439.987504 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5138864 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 131 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 112181 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.949822 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.808684 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 131 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168935 # number of writebacks -system.cpu.dcache.writebacks::total 168935 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205357 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 205357 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895917 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895917 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1101274 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1101274 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1101274 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1101274 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62134 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62134 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143417 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143417 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205551 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205551 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205551 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205551 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2523454750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2523454750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14076498244 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14076498244 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16599952994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16599952994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16599952994 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16599952994 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 168930 # number of writebacks +system.cpu.dcache.writebacks::total 168930 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205345 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 205345 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895901 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895901 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1101246 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1101246 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1101246 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1101246 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62133 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62133 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143407 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143407 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205540 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205540 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205540 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205540 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2525887252 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2525887252 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14052510994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14052510994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16578398246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16578398246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16578398246 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16578398246 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002976 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002976 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.005791 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005791 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40613.106351 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40613.106351 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98150.834587 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98150.834587 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80758.317858 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80758.317858 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80758.317858 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80758.317858 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40652.909919 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40652.909919 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97990.411863 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97990.411863 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80657.770974 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80657.770974 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80657.770974 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80657.770974 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index a8a1f643c..9b769867b 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,18 +173,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -202,16 +216,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -220,22 +237,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -244,22 +265,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -268,10 +293,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -280,124 +307,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -406,10 +454,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -418,16 +468,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -436,10 +489,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -450,6 +505,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -472,14 +528,17 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -498,12 +557,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -514,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -536,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -560,7 +625,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 @@ -574,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -598,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -609,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 1084e1661..df6074257 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026816 # Number of seconds simulated -sim_ticks 26816405500 # Number of ticks simulated -final_tick 26816405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026810 # Number of seconds simulated +sim_ticks 26810051000 # Number of ticks simulated +final_tick 26810051000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109329 # Simulator instruction rate (inst/s) -host_op_rate 155152 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41346943 # Simulator tick rate (ticks/s) -host_mem_usage 283460 # Number of bytes of host memory used -host_seconds 648.57 # Real time elapsed on the host +host_inst_rate 86453 # Simulator instruction rate (inst/s) +host_op_rate 122688 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32687774 # Simulator tick rate (ticks/s) +host_mem_usage 303000 # Number of bytes of host memory used +host_seconds 820.19 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 298432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7942848 # Number of bytes read from this memory -system.physmem.bytes_read::total 8241280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 298432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 298432 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372096 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372096 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4663 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124107 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128770 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83939 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83939 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11128710 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 296193612 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 307322322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11128710 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11128710 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 200328713 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 200328713 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 200328713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11128710 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 296193612 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 507651035 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128770 # Number of read requests accepted -system.physmem.writeReqs 83939 # Number of write requests accepted -system.physmem.readBursts 128770 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83939 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8241152 # Total number of bytes read from DRAM +system.physmem.bytes_read::cpu.inst 299136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7943232 # Number of bytes read from this memory +system.physmem.bytes_read::total 8242368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 299136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 299136 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372608 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372608 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4674 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124113 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128787 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83947 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83947 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11157607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 296278138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 307435745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11157607 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11157607 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 200395292 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 200395292 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 200395292 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11157607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 296278138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 507831037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128788 # Number of read requests accepted +system.physmem.writeReqs 83947 # Number of write requests accepted +system.physmem.readBursts 128788 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83947 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8242304 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371520 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8241280 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5372096 # Total written bytes from the system interface side +system.physmem.bytesWritten 5371392 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8242432 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5372608 # Total written bytes from the system interface side system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 318 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8144 # Per bank write bursts -system.physmem.perBankRdBursts::1 8386 # Per bank write bursts -system.physmem.perBankRdBursts::2 8247 # Per bank write bursts -system.physmem.perBankRdBursts::3 8164 # Per bank write bursts -system.physmem.perBankRdBursts::4 8296 # Per bank write bursts -system.physmem.perBankRdBursts::5 8451 # Per bank write bursts -system.physmem.perBankRdBursts::6 8094 # Per bank write bursts -system.physmem.perBankRdBursts::7 7961 # Per bank write bursts -system.physmem.perBankRdBursts::8 8061 # Per bank write bursts -system.physmem.perBankRdBursts::9 7610 # Per bank write bursts -system.physmem.perBankRdBursts::10 7787 # Per bank write bursts -system.physmem.perBankRdBursts::11 7813 # Per bank write bursts -system.physmem.perBankRdBursts::12 7882 # Per bank write bursts -system.physmem.perBankRdBursts::13 7886 # Per bank write bursts -system.physmem.perBankRdBursts::14 7979 # Per bank write bursts -system.physmem.perBankRdBursts::15 8007 # Per bank write bursts -system.physmem.perBankWrBursts::0 5180 # Per bank write bursts -system.physmem.perBankWrBursts::1 5376 # Per bank write bursts -system.physmem.perBankWrBursts::2 5287 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 308 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 8141 # Per bank write bursts +system.physmem.perBankRdBursts::1 8391 # Per bank write bursts +system.physmem.perBankRdBursts::2 8249 # Per bank write bursts +system.physmem.perBankRdBursts::3 8162 # Per bank write bursts +system.physmem.perBankRdBursts::4 8307 # Per bank write bursts +system.physmem.perBankRdBursts::5 8450 # Per bank write bursts +system.physmem.perBankRdBursts::6 8088 # Per bank write bursts +system.physmem.perBankRdBursts::7 7966 # Per bank write bursts +system.physmem.perBankRdBursts::8 8060 # Per bank write bursts +system.physmem.perBankRdBursts::9 7616 # Per bank write bursts +system.physmem.perBankRdBursts::10 7784 # Per bank write bursts +system.physmem.perBankRdBursts::11 7815 # Per bank write bursts +system.physmem.perBankRdBursts::12 7881 # Per bank write bursts +system.physmem.perBankRdBursts::13 7887 # Per bank write bursts +system.physmem.perBankRdBursts::14 7977 # Per bank write bursts +system.physmem.perBankRdBursts::15 8012 # Per bank write bursts +system.physmem.perBankWrBursts::0 5178 # Per bank write bursts +system.physmem.perBankWrBursts::1 5375 # Per bank write bursts +system.physmem.perBankWrBursts::2 5292 # Per bank write bursts system.physmem.perBankWrBursts::3 5157 # Per bank write bursts -system.physmem.perBankWrBursts::4 5265 # Per bank write bursts +system.physmem.perBankWrBursts::4 5267 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5205 # Per bank write bursts -system.physmem.perBankWrBursts::7 5049 # Per bank write bursts -system.physmem.perBankWrBursts::8 5030 # Per bank write bursts +system.physmem.perBankWrBursts::6 5206 # Per bank write bursts +system.physmem.perBankWrBursts::7 5050 # Per bank write bursts +system.physmem.perBankWrBursts::8 5028 # Per bank write bursts system.physmem.perBankWrBursts::9 5090 # Per bank write bursts -system.physmem.perBankWrBursts::10 5251 # Per bank write bursts -system.physmem.perBankWrBursts::11 5144 # Per bank write bursts +system.physmem.perBankWrBursts::10 5248 # Per bank write bursts +system.physmem.perBankWrBursts::11 5142 # Per bank write bursts system.physmem.perBankWrBursts::12 5342 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5223 # Per bank write bursts +system.physmem.perBankWrBursts::15 5222 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26816294000 # Total gap between requests +system.physmem.totGap 26810034000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128770 # Read request sizes (log2) +system.physmem.readPktSize::6 128788 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83939 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 72833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83947 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 72914 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -127,31 +127,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3685 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 3685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3681 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 3679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 3687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -159,189 +159,189 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37861 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 359.431816 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.292002 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 695.442994 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 15095 39.87% 39.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 5646 14.91% 54.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 3407 9.00% 63.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2352 6.21% 69.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1734 4.58% 74.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1565 4.13% 78.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1073 2.83% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 929 2.45% 83.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 665 1.76% 85.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 565 1.49% 87.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 384 1.01% 88.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 558 1.47% 89.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 286 0.76% 90.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 361 0.95% 91.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 176 0.46% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 218 0.58% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 133 0.35% 92.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 247 0.65% 93.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 117 0.31% 93.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 270 0.71% 94.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 104 0.27% 94.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 418 1.10% 95.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 100 0.26% 96.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 243 0.64% 96.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 38 0.10% 96.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 144 0.38% 97.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 38 0.10% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 86 0.23% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 29 0.08% 97.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 54 0.14% 97.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 16 0.04% 97.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 43 0.11% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 22 0.06% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 37958 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 358.604352 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 173.758574 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 692.410978 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 15190 40.02% 40.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 5700 15.02% 55.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 3416 9.00% 64.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2313 6.09% 70.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 1704 4.49% 74.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1539 4.05% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1108 2.92% 81.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 903 2.38% 83.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 681 1.79% 85.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 548 1.44% 87.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 355 0.94% 88.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 578 1.52% 89.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 299 0.79% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 386 1.02% 91.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 183 0.48% 91.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 223 0.59% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 117 0.31% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 252 0.66% 93.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 118 0.31% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 257 0.68% 94.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 108 0.28% 94.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 421 1.11% 95.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 88 0.23% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 246 0.65% 96.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 43 0.11% 96.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 122 0.32% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 43 0.11% 97.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 88 0.23% 97.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 29 0.08% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 65 0.17% 97.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 27 0.07% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 45 0.12% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 16 0.04% 98.03% # Bytes accessed per row activation system.physmem.bytesPerActivate::2176-2177 34 0.09% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 17 0.04% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 32 0.08% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 11 0.03% 98.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 29 0.08% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 17 0.04% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 31 0.08% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 15 0.04% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 15 0.04% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 11 0.03% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 16 0.04% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 11 0.03% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 9 0.02% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 8 0.02% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 21 0.06% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 4 0.01% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 10 0.03% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 11 0.03% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 21 0.06% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 8 0.02% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 15 0.04% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 29 0.08% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 15 0.04% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 24 0.06% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 13 0.03% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 34 0.09% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 13 0.03% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 17 0.04% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 7 0.02% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 19 0.05% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 9 0.02% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 17 0.04% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 10 0.03% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 27 0.07% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 7 0.02% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 14 0.04% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 10 0.03% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 15 0.04% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 6 0.02% 98.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::3456-3457 7 0.02% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 6 0.02% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 11 0.03% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 10 0.03% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 7 0.02% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 17 0.04% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 5 0.01% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 10 0.03% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 7 0.02% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 7 0.02% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 3 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 6 0.02% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 8 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 11 0.03% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 4 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 10 0.03% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 6 0.02% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 7 0.02% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 2 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 9 0.02% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 12 0.03% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 6 0.02% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 8 0.02% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 2 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 13 0.03% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 11 0.03% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 6 0.02% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 8 0.02% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 10 0.03% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 6 0.02% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 10 0.03% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 7 0.02% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 4 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 8 0.02% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 2 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 4 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 2 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 6 0.02% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 4 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 11 0.03% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 10 0.03% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 7 0.02% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 10 0.03% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 13 0.03% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 7 0.02% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 10 0.03% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 8 0.02% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 13 0.03% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 3 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 8 0.02% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 9 0.02% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 7 0.02% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 7 0.02% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 8 0.02% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 6 0.02% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 8 0.02% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 5 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 9 0.02% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 9 0.02% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 7 0.02% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 4 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 9 0.02% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 6 0.02% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 8 0.02% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 6 0.02% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 9 0.02% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 5 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 7 0.02% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 7 0.02% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 7 0.02% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 4 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 2 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 5 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 3 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 4 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 7 0.02% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 4 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 4 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 2 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 2 0.01% 99.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 5 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 3 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 6 0.02% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 4 0.01% 99.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::6912-6913 5 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 3 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 5 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 4 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 3 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 3 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 2 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 3 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 5 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 4 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 2 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 3 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 5 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 2 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 2 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 2 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 3 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.01% 99.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 5 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 36 0.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37861 # Bytes accessed per row activation -system.physmem.totQLat 3024623000 # Total ticks spent queuing -system.physmem.totMemAccLat 4968016750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 643840000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1299553750 # Total ticks spent accessing banks -system.physmem.avgQLat 23488.93 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 10092.21 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::8128-8129 5 0.01% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 35 0.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37958 # Bytes accessed per row activation +system.physmem.totQLat 3020745250 # Total ticks spent queuing +system.physmem.totMemAccLat 4967419000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 643930000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1302743750 # Total ticks spent accessing banks +system.physmem.avgQLat 23455.54 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 10115.57 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38581.14 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 307.32 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 200.31 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 307.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 200.33 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38571.11 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 307.43 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 200.35 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 307.44 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 200.40 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.97 # Data bus utilization in percentage system.physmem.busUtilRead 2.40 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.56 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 1.57 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.76 # Average write queue length when enqueuing -system.physmem.readRowHits 117866 # Number of row buffer hits during reads -system.physmem.writeRowHits 56971 # Number of row buffer hits during writes +system.physmem.avgWrQLen 9.73 # Average write queue length when enqueuing +system.physmem.readRowHits 117878 # Number of row buffer hits during reads +system.physmem.writeRowHits 56878 # Number of row buffer hits during writes system.physmem.readRowHitRate 91.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.87 # Row buffer hit rate for writes -system.physmem.avgGap 126070.33 # Average gap between requests -system.physmem.pageHitRate 82.20 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 11.88 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 507651035 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26514 # Transaction distribution -system.membus.trans_dist::ReadResp 26514 # Transaction distribution -system.membus.trans_dist::Writeback 83939 # Transaction distribution -system.membus.trans_dist::UpgradeReq 318 # Transaction distribution -system.membus.trans_dist::UpgradeResp 318 # Transaction distribution -system.membus.trans_dist::ReadExReq 102256 # Transaction distribution -system.membus.trans_dist::ReadExResp 102256 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342115 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 342115 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13613376 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13613376 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13613376 # Total data (bytes) +system.physmem.writeRowHitRate 67.75 # Row buffer hit rate for writes +system.physmem.avgGap 126025.50 # Average gap between requests +system.physmem.pageHitRate 82.15 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 11.63 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 507831037 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26531 # Transaction distribution +system.membus.trans_dist::ReadResp 26530 # Transaction distribution +system.membus.trans_dist::Writeback 83947 # Transaction distribution +system.membus.trans_dist::UpgradeReq 308 # Transaction distribution +system.membus.trans_dist::UpgradeResp 308 # Transaction distribution +system.membus.trans_dist::ReadExReq 102257 # Transaction distribution +system.membus.trans_dist::ReadExResp 102257 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342138 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 342138 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13614976 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13614976 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13614976 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 934803500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 934752500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1203423433 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1203686693 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.5 # Layer utilization (%) -system.cpu.branchPred.lookups 16622919 # Number of BP lookups -system.cpu.branchPred.condPredicted 12749857 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 605504 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10570940 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7775711 # Number of BTB hits +system.cpu.branchPred.lookups 16646392 # Number of BP lookups +system.cpu.branchPred.condPredicted 12773976 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 607235 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10818826 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7781096 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 73.557423 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1829148 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113993 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.921815 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1825486 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 113411 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -385,239 +385,239 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 53632812 # number of cpu cycles simulated +system.cpu.numCycles 53620103 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12575227 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85200235 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16622919 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9604859 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21200799 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2368859 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10684050 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 493 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11692200 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 184239 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46197272 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.582993 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.332808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12555863 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85327612 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16646392 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9606582 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21220606 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2386309 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10655499 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 479 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 60 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11697004 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 183631 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46184612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.586702 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.333983 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25016575 54.15% 54.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2138831 4.63% 58.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1968354 4.26% 63.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2045405 4.43% 67.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1466932 3.18% 70.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1376276 2.98% 73.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 961294 2.08% 75.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1190217 2.58% 78.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10033388 21.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24984951 54.10% 54.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2138585 4.63% 58.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1966197 4.26% 62.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2046003 4.43% 67.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1469884 3.18% 70.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1382868 2.99% 73.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 958032 2.07% 75.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1189943 2.58% 78.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10048149 21.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46197272 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.309939 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.588584 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14661485 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9032065 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19500717 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1369785 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1633220 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3334387 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 105402 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116870755 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 365005 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1633220 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16370455 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2587455 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1031873 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19111398 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5462871 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 114984523 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 46184612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.310451 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.591336 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14642918 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9005955 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19517473 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1369283 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1648983 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3334820 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 105179 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116999070 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 363013 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1648983 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16350179 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2575616 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1030832 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19130431 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5448571 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 115098604 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 171 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 15960 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4602334 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 241 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115277175 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529754178 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 476504412 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2548 # Number of floating rename lookups +system.cpu.rename.IQFullEvents 17023 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4589680 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 256 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115425064 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 530260724 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 476967295 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2691 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16144503 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20627 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20613 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12986013 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29603679 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22442541 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3905979 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4383979 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111534291 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 36144 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107247539 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 279427 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10792871 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25872402 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2358 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46197272 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.321512 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.989577 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16292392 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20388 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20384 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12970121 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29626660 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22464166 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3855353 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4357218 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111639066 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 36000 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107318490 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 273494 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10897204 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 26020912 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2214 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46184612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.323685 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.992080 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10946962 23.70% 23.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8090791 17.51% 41.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7422192 16.07% 57.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7125519 15.42% 72.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5414632 11.72% 84.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3916527 8.48% 92.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1842332 3.99% 96.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 865884 1.87% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 572433 1.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10954733 23.72% 23.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8081116 17.50% 41.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7387326 16.00% 57.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7126917 15.43% 72.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5408207 11.71% 84.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3931545 8.51% 92.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1847862 4.00% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 871002 1.89% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 575904 1.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46197272 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46184612 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 111334 4.52% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 1 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1349070 54.73% 59.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1004381 40.75% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112087 4.51% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 3 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1355242 54.58% 59.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1015813 40.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56643981 52.82% 52.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91446 0.09% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 176 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28888115 26.94% 79.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21623814 20.16% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56685703 52.82% 52.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91410 0.09% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 203 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28899327 26.93% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21641840 20.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107247539 # Type of FU issued -system.cpu.iq.rate 1.999663 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2464786 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022982 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263436010 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122391385 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105557389 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 553 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 926 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 158 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109712054 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 271 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2181647 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107318490 # Type of FU issued +system.cpu.iq.rate 2.001460 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2483145 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023138 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263577666 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122600736 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105627540 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 565 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 906 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 170 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109801353 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 282 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2178214 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2296571 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6409 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29938 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1886803 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2319552 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6675 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30486 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1908428 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 637 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 694 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1633220 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1092915 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45139 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111580294 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 294739 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29603679 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22442541 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 20224 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6335 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5295 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29938 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 394730 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 181332 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 576062 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106214921 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28587238 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1032618 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1648983 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1092293 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45577 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111684840 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 295051 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29626660 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22464166 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 20080 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6356 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5380 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30486 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 395595 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 182079 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 577674 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106281813 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28597262 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1036677 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9859 # number of nop insts executed -system.cpu.iew.exec_refs 49925863 # number of memory reference insts executed -system.cpu.iew.exec_branches 14600722 # Number of branches executed -system.cpu.iew.exec_stores 21338625 # Number of stores executed -system.cpu.iew.exec_rate 1.980409 # Inst execution rate -system.cpu.iew.wb_sent 105779922 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105557547 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53302648 # num instructions producing a value -system.cpu.iew.wb_consumers 103946447 # num instructions consuming a value +system.cpu.iew.exec_nop 9774 # number of nop insts executed +system.cpu.iew.exec_refs 49953963 # number of memory reference insts executed +system.cpu.iew.exec_branches 14606559 # Number of branches executed +system.cpu.iew.exec_stores 21356701 # Number of stores executed +system.cpu.iew.exec_rate 1.982126 # Inst execution rate +system.cpu.iew.wb_sent 105847179 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105627710 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53336530 # num instructions producing a value +system.cpu.iew.wb_consumers 104015656 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.968152 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.512790 # average fanout of values written-back +system.cpu.iew.wb_rate 1.969927 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.512774 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10948789 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11053294 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 502113 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44564052 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.258153 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.763889 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 504169 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44535629 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.259594 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.766011 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15506218 34.80% 34.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11644493 26.13% 60.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3446423 7.73% 68.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2869378 6.44% 75.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1870309 4.20% 79.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1959985 4.40% 83.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 685768 1.54% 85.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 560638 1.26% 86.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6020840 13.51% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15484235 34.77% 34.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11649742 26.16% 60.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3457573 7.76% 68.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2865921 6.44% 75.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1843682 4.14% 79.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1946516 4.37% 83.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 688008 1.54% 85.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 565195 1.27% 86.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6034757 13.55% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44564052 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44535629 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -628,226 +628,226 @@ system.cpu.commit.branches 13741485 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6020840 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6034757 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 150099130 # The number of ROB reads -system.cpu.rob.rob_writes 224804524 # The number of ROB writes -system.cpu.timesIdled 76985 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7435540 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 150161295 # The number of ROB reads +system.cpu.rob.rob_writes 225029668 # The number of ROB writes +system.cpu.timesIdled 76463 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7435491 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.756376 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.756376 # CPI: Total CPI of All Threads -system.cpu.ipc 1.322094 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.322094 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511539854 # number of integer regfile reads -system.cpu.int_regfile_writes 103334614 # number of integer regfile writes -system.cpu.fp_regfile_reads 734 # number of floating regfile reads -system.cpu.fp_regfile_writes 630 # number of floating regfile writes -system.cpu.misc_regfile_reads 49164319 # number of misc regfile reads +system.cpu.cpi 0.756197 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.756197 # CPI: Total CPI of All Threads +system.cpu.ipc 1.322408 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.322408 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511842322 # number of integer regfile reads +system.cpu.int_regfile_writes 103400028 # number of integer regfile writes +system.cpu.fp_regfile_reads 836 # number of floating regfile reads +system.cpu.fp_regfile_writes 732 # number of floating regfile writes +system.cpu.misc_regfile_reads 49193821 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.throughput 775188755 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 88572 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 88572 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 129187 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107050 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107050 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65806 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454775 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 520581 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2089088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18665280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 20754368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 20754368 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 33408 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 291762996 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 770392865 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 86565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 86563 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 129111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 321 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 321 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107049 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107049 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61854 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454640 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 516494 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18659456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 20623232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 20623232 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 31040 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 290637496 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 50495227 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 47495730 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 260303004 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 260347495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 30799 # number of replacements -system.cpu.icache.tags.tagsinuse 1804.677341 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 11655246 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 32836 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 354.953283 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 28815 # number of replacements +system.cpu.icache.tags.tagsinuse 1808.840382 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 11662045 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 30854 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 377.975141 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1804.677341 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.881190 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.881190 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11655255 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11655255 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11655255 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11655255 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11655255 # number of overall hits -system.cpu.icache.overall_hits::total 11655255 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 36945 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 36945 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 36945 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 36945 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 36945 # number of overall misses -system.cpu.icache.overall_misses::total 36945 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 836533724 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 836533724 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 836533724 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 836533724 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 836533724 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 836533724 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11692200 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11692200 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11692200 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11692200 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11692200 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11692200 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003160 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003160 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003160 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003160 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003160 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003160 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22642.677602 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22642.677602 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22642.677602 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22642.677602 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22642.677602 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22642.677602 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 965 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1808.840382 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.883223 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.883223 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11662047 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11662047 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11662047 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11662047 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11662047 # number of overall hits +system.cpu.icache.overall_hits::total 11662047 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 34957 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 34957 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 34957 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 34957 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 34957 # number of overall misses +system.cpu.icache.overall_misses::total 34957 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 813284976 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 813284976 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 813284976 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 813284976 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 813284976 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 813284976 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11697004 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11697004 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11697004 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11697004 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11697004 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11697004 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002989 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002989 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002989 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002989 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002989 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002989 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23265.296679 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23265.296679 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23265.296679 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23265.296679 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23265.296679 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23265.296679 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2987 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 48.250000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 129.869565 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3781 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3781 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3781 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3781 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3781 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3781 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33164 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 33164 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 33164 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 33164 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 33164 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 33164 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 680570772 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 680570772 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 680570772 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 680570772 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 680570772 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 680570772 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002836 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002836 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002836 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002836 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002836 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002836 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20521.371728 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20521.371728 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20521.371728 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20521.371728 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20521.371728 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20521.371728 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3787 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3787 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3787 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3787 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3787 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3787 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31170 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 31170 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 31170 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 31170 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 31170 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 31170 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 659799769 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 659799769 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 659799769 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 659799769 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 659799769 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 659799769 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002665 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002665 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002665 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002665 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002665 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002665 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21167.782130 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21167.782130 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21167.782130 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21167.782130 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21167.782130 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21167.782130 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 95639 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29886.699201 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 90376 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 126754 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.713003 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 95665 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29888.812560 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 88308 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 126769 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.696606 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26679.268686 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1365.813290 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1841.617225 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.814187 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041681 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.056202 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.912070 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 27962 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33496 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 61458 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 129187 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 129187 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 18 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 18 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4794 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4794 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 27962 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 38290 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 66252 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 27962 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 38290 # number of overall hits -system.cpu.l2cache.overall_hits::total 66252 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 4680 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 21912 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 26592 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 318 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 318 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 102256 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102256 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 4680 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 124168 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 128848 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 4680 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 124168 # number of overall misses -system.cpu.l2cache.overall_misses::total 128848 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 367025250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1881179499 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2248204749 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23499 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 23499 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8506522000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8506522000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 367025250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10387701499 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10754726749 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 367025250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10387701499 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10754726749 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 32642 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 55408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 88050 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 129187 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 129187 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 336 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 336 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 107050 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107050 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 32642 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 162458 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 195100 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 32642 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 162458 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 195100 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.143374 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395466 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.302010 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.946429 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.946429 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955217 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955217 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.143374 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.764308 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.660420 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.143374 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.764308 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.660420 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78424.198718 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85851.565307 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 84544.402414 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 73.896226 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 73.896226 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83188.487717 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83188.487717 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78424.198718 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83658.442586 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83468.325073 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78424.198718 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83658.442586 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83468.325073 # average overall miss latency +system.cpu.l2cache.tags.occ_blocks::writebacks 26671.340857 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1372.959347 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1844.512356 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.813945 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041899 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.056290 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.912134 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 25996 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 33476 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 59472 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 129111 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 129111 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 13 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 13 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4792 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4792 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 25996 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 38268 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 64264 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 25996 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 38268 # number of overall hits +system.cpu.l2cache.overall_hits::total 64264 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 4689 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 21919 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 26608 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 308 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 308 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 102257 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102257 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 4689 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 124176 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 128865 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 4689 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 124176 # number of overall misses +system.cpu.l2cache.overall_misses::total 128865 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 367952250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1871129000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2239081250 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22999 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 22999 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8515215250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8515215250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 367952250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10386344250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10754296500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 367952250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10386344250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10754296500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 30685 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 55395 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 86080 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 129111 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 129111 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 321 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 321 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 107049 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107049 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 30685 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 162444 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 193129 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 30685 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 162444 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 193129 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.152811 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395686 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.309108 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.959502 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.959502 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955235 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955235 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.152811 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.764423 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.667248 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.152811 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.764423 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.667248 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78471.369162 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85365.618869 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 84150.678367 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 74.672078 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 74.672078 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83272.687933 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83272.687933 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78471.369162 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83642.122874 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83453.975090 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78471.369162 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83642.122874 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83453.975090 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -856,195 +856,195 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83939 # number of writebacks -system.cpu.l2cache.writebacks::total 83939 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 78 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 78 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4663 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21851 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 26514 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 318 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 318 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102256 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102256 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4663 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 124107 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128770 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4663 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 124107 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128770 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 307037750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1604664499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1911702249 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3189317 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3189317 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7230852500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7230852500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 307037750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8835516999 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9142554749 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 307037750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8835516999 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9142554749 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.142853 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394365 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.301124 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.946429 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.946429 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955217 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955217 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.142853 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.763933 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.660021 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.142853 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.763933 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.660021 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65845.539352 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73436.661892 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72101.616090 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10029.298742 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10029.298742 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70713.234431 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70713.234431 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65845.539352 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71192.736904 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70999.104986 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65845.539352 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71192.736904 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70999.104986 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 83947 # number of writebacks +system.cpu.l2cache.writebacks::total 83947 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4674 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21857 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26531 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 308 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 308 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102257 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102257 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4674 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124114 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128788 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4674 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124114 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128788 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 308414000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1593918750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1902332750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3088307 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3088307 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7239546250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7239546250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 308414000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8833465000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9141879000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 308414000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8833465000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9141879000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152322 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394566 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308213 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.959502 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.959502 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955235 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955235 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152322 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764042 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.666850 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152322 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764042 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.666850 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65985.023534 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72924.863888 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71702.263390 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.970779 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.970779 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70797.561536 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70797.561536 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65985.023534 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71172.188472 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70983.934839 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65985.023534 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71172.188472 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70983.934839 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 158362 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.865935 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 44347537 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 162458 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 272.978474 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 158347 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.859504 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 44362534 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 162443 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 273.096003 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 363282250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.865935 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993375 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993375 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26048299 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26048299 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18266707 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18266707 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15986 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15986 # number of LoadLockedReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.859504 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993374 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993374 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26063246 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26063246 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18266759 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18266759 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15989 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15989 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44315006 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44315006 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44315006 # number of overall hits -system.cpu.dcache.overall_hits::total 44315006 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 125034 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 125034 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1583194 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1583194 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1708228 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1708228 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1708228 # number of overall misses -system.cpu.dcache.overall_misses::total 1708228 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5241649212 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5241649212 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 126812367989 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 126812367989 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 914750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 914750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 132054017201 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 132054017201 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 132054017201 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 132054017201 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26173333 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26173333 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 44330005 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44330005 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44330005 # number of overall hits +system.cpu.dcache.overall_hits::total 44330005 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 124539 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 124539 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1583142 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1583142 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 43 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 43 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1707681 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1707681 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1707681 # number of overall misses +system.cpu.dcache.overall_misses::total 1707681 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5216348715 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5216348715 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126998846491 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126998846491 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1036500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1036500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 132215195206 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 132215195206 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 132215195206 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 132215195206 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26187785 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26187785 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16027 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16027 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16032 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16032 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46023234 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46023234 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46023234 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46023234 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004777 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004777 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079758 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079758 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002558 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002558 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037117 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037117 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037117 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037117 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41921.790969 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41921.790969 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80099.070606 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80099.070606 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 22310.975610 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 22310.975610 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77304.679001 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77304.679001 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77304.679001 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77304.679001 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4730 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 139 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.028777 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 87.428571 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46037686 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46037686 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46037686 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46037686 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004756 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004756 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079756 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079756 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002682 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002682 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037093 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037093 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037093 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037093 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41885.262568 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41885.262568 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80219.491676 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80219.491676 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 24104.651163 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 24104.651163 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77423.825179 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77423.825179 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77423.825179 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77423.825179 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3791 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1217 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 149 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.442953 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 93.615385 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129187 # number of writebacks -system.cpu.dcache.writebacks::total 129187 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69592 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69592 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475842 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475842 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1545434 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1545434 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1545434 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1545434 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55442 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55442 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107352 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107352 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162794 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162794 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162794 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162794 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2274282063 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2274282063 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8672803924 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8672803924 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947085987 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10947085987 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947085987 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10947085987 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003537 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003537 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003537 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003537 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41020.923902 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41020.923902 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80788.470862 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80788.470862 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67245.021235 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67245.021235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67245.021235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67245.021235 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 129111 # number of writebacks +system.cpu.dcache.writebacks::total 129111 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69110 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69110 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475806 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475806 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 43 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 43 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1544916 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1544916 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1544916 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1544916 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55429 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55429 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107336 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107336 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162765 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162765 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162765 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162765 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2263965562 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2263965562 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8681187684 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8681187684 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10945153246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10945153246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10945153246 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10945153246 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40844.423713 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40844.423713 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80878.621190 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80878.621190 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67245.127921 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67245.127921 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67245.127921 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67245.127921 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini index 49239c031..cd7da392b 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -56,6 +60,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fetchBuffSize=4 function_trace=false function_trace_start=0 @@ -90,6 +95,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -105,6 +111,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -127,11 +134,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -140,6 +149,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -162,17 +172,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -181,6 +195,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -203,12 +218,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -218,6 +235,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -227,7 +245,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -241,11 +260,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -265,6 +286,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -276,17 +298,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index e22bfa1d8..864d4a591 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.009838 # Nu sim_ticks 1009838214500 # Number of ticks simulated final_tick 1009838214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108402 # Simulator instruction rate (inst/s) -host_op_rate 108402 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60154913 # Simulator tick rate (ticks/s) -host_mem_usage 256492 # Number of bytes of host memory used -host_seconds 16787.29 # Real time elapsed on the host +host_inst_rate 87394 # Simulator instruction rate (inst/s) +host_op_rate 87394 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48496748 # Simulator tick rate (ticks/s) +host_mem_usage 275936 # Number of bytes of host memory used +host_seconds 20822.81 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory @@ -95,10 +95,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1018055 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1662262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 204907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 70584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 21383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1662258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 204908 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70586 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 21384 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -128,27 +128,27 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 45504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 45757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 45743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 45756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 45744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 45699 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 45701 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 45665 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 45697 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 45681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 45684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 45673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 45686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 45671 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 45688 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 45723 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 45729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 45794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 45985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 45793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 45986 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 46199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 46504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 46502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47567 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 47005 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 48930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47073 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 1504 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 185 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see @@ -159,19 +159,19 @@ system.physmem.wrQLenPdf::28 1 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1862401 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 102.289945 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 79.389421 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 186.671108 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1500565 80.57% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 201454 10.82% 91.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 59784 3.21% 94.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 29274 1.57% 96.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 16603 0.89% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 10401 0.56% 97.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 7224 0.39% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 6892 0.37% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 4048 0.22% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1862398 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 102.290110 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 79.389553 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 186.671437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1500560 80.57% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 201450 10.82% 91.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 59792 3.21% 94.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 29273 1.57% 96.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 16605 0.89% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 10399 0.56% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 7221 0.39% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 6896 0.37% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 4046 0.22% 98.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-641 3343 0.18% 98.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::704-705 3041 0.16% 98.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-769 2820 0.15% 99.09% # Bytes accessed per row activation @@ -180,10 +180,10 @@ system.physmem.bytesPerActivate::896-897 1539 0.08% 99.26% # By system.physmem.bytesPerActivate::960-961 1515 0.08% 99.34% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1025 1490 0.08% 99.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::1088-1089 1330 0.07% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1308 0.07% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 968 0.05% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 1341 0.07% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 595 0.03% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 1307 0.07% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 969 0.05% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 1340 0.07% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 596 0.03% 99.72% # Bytes accessed per row activation system.physmem.bytesPerActivate::1408-1409 2192 0.12% 99.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::1472-1473 189 0.01% 99.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::1536-1537 700 0.04% 99.88% # Bytes accessed per row activation @@ -283,15 +283,15 @@ system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.99% # system.physmem.bytesPerActivate::7936-7937 5 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 154 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1862401 # Bytes accessed per row activation -system.physmem.totQLat 23049370500 # Total ticks spent queuing -system.physmem.totMemAccLat 84969994250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::total 1862398 # Bytes accessed per row activation +system.physmem.totQLat 23048924250 # Total ticks spent queuing +system.physmem.totMemAccLat 84969451750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 9795680000 # Total ticks spent in databus transfers -system.physmem.totBankLat 52124943750 # Total ticks spent accessing banks -system.physmem.avgQLat 11765.07 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 26606.09 # Average bank access latency per DRAM burst +system.physmem.totBankLat 52124847500 # Total ticks spent accessing banks +system.physmem.avgQLat 11764.84 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 26606.04 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43371.16 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 43370.88 # Average memory access latency per DRAM burst system.physmem.avgRdBW 124.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 64.52 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 124.20 # Average system read bandwidth in MiByte/s @@ -302,8 +302,8 @@ system.physmem.busUtilRead 0.97 # Da system.physmem.busUtilWrite 0.50 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.08 # Average read queue length when enqueuing system.physmem.avgWrQLen 10.29 # Average write queue length when enqueuing -system.physmem.readRowHits 771404 # Number of row buffer hits during reads -system.physmem.writeRowHits 343365 # Number of row buffer hits during writes +system.physmem.readRowHits 771409 # Number of row buffer hits during reads +system.physmem.writeRowHits 343363 # Number of row buffer hits during writes system.physmem.readRowHitRate 39.37 # Row buffer hit rate for reads system.physmem.writeRowHitRate 33.73 # Row buffer hit rate for writes system.physmem.avgGap 339128.71 # Average gap between requests @@ -321,39 +321,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1 system.membus.tot_pkt_size::total 190575552 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 190575552 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11787413500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11785228500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 18365913000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18364778000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.8 # Layer utilization (%) -system.cpu.branchPred.lookups 326538195 # Number of BP lookups -system.cpu.branchPred.condPredicted 252572806 # Number of conditional branches predicted +system.cpu.branchPred.lookups 326538257 # Number of BP lookups +system.cpu.branchPred.condPredicted 252572868 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 138234365 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 220428693 # Number of BTB lookups -system.cpu.branchPred.BTBHits 135446272 # Number of BTB hits +system.cpu.branchPred.BTBLookups 220428800 # Number of BTB lookups +system.cpu.branchPred.BTBHits 135446379 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.446752 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 61.446771 # BTB Hit Percentage system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444831815 # DTB read hits +system.cpu.dtb.read_hits 444831817 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449728893 # DTB read accesses +system.cpu.dtb.read_accesses 449728895 # DTB read accesses system.cpu.dtb.write_hits 160846718 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 162548022 # DTB write accesses -system.cpu.dtb.data_hits 605678533 # DTB hits +system.cpu.dtb.data_hits 605678535 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612276915 # DTB accesses -system.cpu.itb.fetch_hits 231928866 # ITB hits +system.cpu.dtb.data_accesses 612276917 # DTB accesses +system.cpu.itb.fetch_hits 231928870 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 231928888 # ITB accesses +system.cpu.itb.fetch_accesses 231928892 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -370,8 +370,8 @@ system.cpu.workload.num_syscalls 29 # Nu system.cpu.numCycles 2019676430 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 172263192 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 154275003 # Number of Branches Predicted As Not Taken (False). +system.cpu.branch_predictor.predictedTaken 172263299 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154274958 # Number of Branches Predicted As Not Taken (False). system.cpu.regfile_manager.intRegFileReads 1667627607 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileAccesses 3043830224 # Total Accesses (Read+Write) to the Int. Register File @@ -389,12 +389,12 @@ system.cpu.execution_unit.executions 1139356886 # Nu system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1742059065 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1742060649 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7515569 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 447943127 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1571733303 # Number of cycles cpu stages are processed. -system.cpu.activity 77.821045 # Percentage of cycles cpu is active +system.cpu.timesIdled 7515544 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 447943086 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571733344 # Number of cycles cpu stages are processed. +system.cpu.activity 77.821047 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -412,66 +412,66 @@ system.cpu.cpi_total 1.109846 # CP system.cpu.ipc 0.901026 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.ipc_total 0.901026 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 833031471 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1186644959 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 58.754211 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1085876245 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933800185 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.235138 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1047285366 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 972391064 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.idleCycles 833031386 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186645044 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 58.754216 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1085876271 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933800159 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.235137 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1047285367 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972391063 # Number of cycles 1+ instructions are processed. system.cpu.stage2.utilization 48.145884 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1610051905 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409624525 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.idleCycles 1610051904 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409624526 # Number of cycles 1+ instructions are processed. system.cpu.stage3.utilization 20.281691 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 998329603 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1021346827 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.idleCycles 998329594 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021346836 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 50.569825 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 668.332859 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 231927727 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 231927731 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 269997.353900 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 269997.358556 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 668.332859 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.326334 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.326334 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 231927727 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 231927727 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 231927727 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 231927727 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 231927727 # number of overall hits -system.cpu.icache.overall_hits::total 231927727 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 231927731 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 231927731 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 231927731 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 231927731 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 231927731 # number of overall hits +system.cpu.icache.overall_hits::total 231927731 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1139 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1139 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1139 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1139 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1139 # number of overall misses system.cpu.icache.overall_misses::total 1139 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 82717000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 82717000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 82717000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 82717000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 82717000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 82717000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 231928866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 231928866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 231928866 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 231928866 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 231928866 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 231928866 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 82716500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 82716500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 82716500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 82716500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 82716500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 82716500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 231928870 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 231928870 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 231928870 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 231928870 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 231928870 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 231928870 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72622.475856 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72622.475856 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72622.475856 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72622.475856 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72622.475856 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72622.475856 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72622.036874 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72622.036874 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72622.036874 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72622.036874 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72622.036874 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72622.036874 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 162 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -492,24 +492,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 859 system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65136750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 65136750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65136750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 65136750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65136750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 65136750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65136250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 65136250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65136250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 65136250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65136250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 65136250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75828.579744 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75828.579744 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75828.579744 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75828.579744 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75828.579744 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75828.579744 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75827.997672 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75827.997672 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75827.997672 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75827.997672 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75827.997672 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75827.997672 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.throughput 811573074 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 7222683 # Transaction distribution @@ -529,17 +529,17 @@ system.cpu.toL2Bus.reqLayer0.occupancy 10096073000 # La system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1445250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13991720500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13991718500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.l2cache.tags.replacements 1926957 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30919.698652 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30919.698369 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8958682 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1956750 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.578348 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 67892812750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14931.952178 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 14931.951876 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.659960 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15953.086514 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15953.086532 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.455687 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001058 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.486850 # Average percentage of cache occupancy @@ -565,17 +565,17 @@ system.cpu.l2cache.demand_misses::total 1959688 # nu system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1958829 # number of overall misses system.cpu.l2cache.overall_misses::total 1959688 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 64273750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98167461500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 98231735250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 71142206750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 71142206750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 64273750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 169309668250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 169373942000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 64273750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 169309668250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 169373942000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 64273250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98166669000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 98230942250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 71141350250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 71141350250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 64273250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 169308019250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 169372292500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 64273250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 169308019250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 169372292500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7221824 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7222683 # number of ReadReq accesses(hits+misses) @@ -600,17 +600,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.215060 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214986 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.215060 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74823.923166 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83367.057654 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 83360.830055 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91056.663224 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91056.663224 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74823.923166 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86434.123780 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86429.034622 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74823.923166 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86434.123780 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86429.034622 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74823.341094 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83366.384636 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 83360.157104 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91055.566968 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91055.566968 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74823.341094 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86433.281951 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86428.192906 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74823.341094 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86433.281951 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86428.192906 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -632,17 +632,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1959688 system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1958829 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1959688 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53492750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 83392423000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 83445915750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61355655750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61355655750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53492750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 144748078750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 144801571500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53492750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 144748078750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 144801571500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53491750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 83391618000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 83445109750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61355946750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61355946750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53491750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 144747564750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 144801056500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53491750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 144747564750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 144801056500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163152 # mshr miss rate for ReadReq accesses @@ -654,21 +654,21 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.215060 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214986 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.215060 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62273.282887 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70819.605905 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70813.375982 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78530.615477 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78530.615477 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62273.282887 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73895.209204 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73890.114906 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62273.282887 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73895.209204 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73890.114906 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62272.118743 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70818.922272 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70812.691999 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78530.987935 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78530.987935 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62272.118743 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73894.946802 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73889.852109 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62272.118743 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73894.946802 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73889.852109 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 9107351 # number of replacements system.cpu.dcache.tags.tagsinuse 4082.357931 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 593283203 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 593283202 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9111447 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 65.114049 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 12709353000 # Cycle when the warmup percentage was hit. @@ -677,28 +677,28 @@ system.cpu.dcache.tags.occ_percent::cpu.data 0.996669 system.cpu.dcache.tags.occ_percent::total 0.996669 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437268777 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437268777 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156014426 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156014426 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 593283203 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 593283203 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 593283203 # number of overall hits -system.cpu.dcache.overall_hits::total 593283203 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 156014425 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156014425 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593283202 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593283202 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593283202 # number of overall hits +system.cpu.dcache.overall_hits::total 593283202 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7326886 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7326886 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4714076 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4714076 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 12040962 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 12040962 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 12040962 # number of overall misses -system.cpu.dcache.overall_misses::total 12040962 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 183066802000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 183066802000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 258282974250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 258282974250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 441349776250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 441349776250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 441349776250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 441349776250 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 4714077 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4714077 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 12040963 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 12040963 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12040963 # number of overall misses +system.cpu.dcache.overall_misses::total 12040963 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 183066004000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 183066004000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 258278135000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 258278135000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 441344139000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 441344139000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 441344139000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 441344139000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -715,19 +715,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.019892 system.cpu.dcache.demand_miss_rate::total 0.019892 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.019892 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.019892 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24985.621723 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24985.621723 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54789.734881 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54789.734881 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36654.029491 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36654.029491 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36654.029491 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36654.029491 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12098438 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24985.512809 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24985.512809 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54788.696706 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54788.696706 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36653.558274 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36653.558274 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36653.558274 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36653.558274 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12098433 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 7855784 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 422645 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 422647 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 73423 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.625532 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.625385 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 106.993503 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -735,12 +735,12 @@ system.cpu.dcache.writebacks::writebacks 3693280 # nu system.cpu.dcache.writebacks::total 3693280 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104620 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 104620 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2824895 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2824895 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2929515 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2929515 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2929515 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2929515 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2824896 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2824896 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2929516 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2929516 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2929516 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2929516 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222266 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222266 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889181 # number of WriteReq MSHR misses @@ -749,14 +749,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111447 system.cpu.dcache.demand_mshr_misses::total 9111447 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111447 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111447 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 165960748500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 165960748500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84277565500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84277565500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250238314000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 250238314000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 250238314000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 250238314000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 165959957500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 165959957500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84276720000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84276720000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250236677500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 250236677500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 250236677500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 250236677500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -765,14 +765,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22979.041273 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22979.041273 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44610.635773 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44610.635773 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27464.168315 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27464.168315 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27464.168315 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27464.168315 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22978.931751 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22978.931751 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44610.188224 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44610.188224 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27463.988706 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27463.988706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27463.988706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27463.988706 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 898bd1404..3e178e75c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,17 +518,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -482,6 +541,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -504,12 +564,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -528,7 +591,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -542,11 +606,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -566,6 +632,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -577,17 +644,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index fbdbcc030..29e4de429 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.685488 # Number of seconds simulated -sim_ticks 685488076000 # Number of ticks simulated -final_tick 685488076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.685387 # Number of seconds simulated +sim_ticks 685386545000 # Number of ticks simulated +final_tick 685386545000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134484 # Simulator instruction rate (inst/s) -host_op_rate 134484 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53101916 # Simulator tick rate (ticks/s) -host_mem_usage 257516 # Number of bytes of host memory used -host_seconds 12908.91 # Real time elapsed on the host +host_inst_rate 111182 # Simulator instruction rate (inst/s) +host_op_rate 111182 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43894428 # Simulator tick rate (ticks/s) +host_mem_usage 276060 # Number of bytes of host memory used +host_seconds 15614.43 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125793664 # Number of bytes read from this memory -system.physmem.bytes_read::total 125855616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61952 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65265536 # Number of bytes written to this memory -system.physmem.bytes_written::total 65265536 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 968 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965526 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966494 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019774 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019774 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 90376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 183509631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 183600008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 90376 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 90376 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 95210316 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 95210316 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 95210316 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 90376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 183509631 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 278810323 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966494 # Number of read requests accepted -system.physmem.writeReqs 1019774 # Number of write requests accepted -system.physmem.readBursts 1966494 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1019774 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125820608 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 35008 # Total number of bytes read from write queue -system.physmem.bytesWritten 65264256 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125855616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65265536 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 547 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125792064 # Number of bytes read from this memory +system.physmem.bytes_read::total 125853824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65263104 # Number of bytes written to this memory +system.physmem.bytes_written::total 65263104 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965501 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966466 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019736 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019736 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 90110 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 183534481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 183624591 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 90110 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 90110 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 95220871 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 95220871 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 95220871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 90110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 183534481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 278845462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966466 # Number of read requests accepted +system.physmem.writeReqs 1019736 # Number of write requests accepted +system.physmem.readBursts 1966466 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1019736 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125817344 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 36480 # Total number of bytes read from write queue +system.physmem.bytesWritten 65263104 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125853824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65263104 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 570 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119024 # Per bank write bursts -system.physmem.perBankRdBursts::1 114431 # Per bank write bursts -system.physmem.perBankRdBursts::2 116551 # Per bank write bursts -system.physmem.perBankRdBursts::3 118044 # Per bank write bursts -system.physmem.perBankRdBursts::4 118169 # Per bank write bursts -system.physmem.perBankRdBursts::5 117821 # Per bank write bursts -system.physmem.perBankRdBursts::6 120193 # Per bank write bursts -system.physmem.perBankRdBursts::7 124929 # Per bank write bursts -system.physmem.perBankRdBursts::8 127563 # Per bank write bursts -system.physmem.perBankRdBursts::9 130460 # Per bank write bursts -system.physmem.perBankRdBursts::10 129120 # Per bank write bursts -system.physmem.perBankRdBursts::11 130791 # Per bank write bursts -system.physmem.perBankRdBursts::12 126621 # Per bank write bursts -system.physmem.perBankRdBursts::13 125625 # Per bank write bursts -system.physmem.perBankRdBursts::14 122955 # Per bank write bursts -system.physmem.perBankRdBursts::15 123650 # Per bank write bursts -system.physmem.perBankWrBursts::0 61294 # Per bank write bursts -system.physmem.perBankWrBursts::1 61576 # Per bank write bursts -system.physmem.perBankWrBursts::2 60653 # Per bank write bursts -system.physmem.perBankWrBursts::3 61320 # Per bank write bursts -system.physmem.perBankWrBursts::4 61767 # Per bank write bursts -system.physmem.perBankWrBursts::5 63184 # Per bank write bursts -system.physmem.perBankWrBursts::6 64210 # Per bank write bursts -system.physmem.perBankWrBursts::7 65704 # Per bank write bursts -system.physmem.perBankWrBursts::8 65475 # Per bank write bursts -system.physmem.perBankWrBursts::9 65876 # Per bank write bursts -system.physmem.perBankWrBursts::10 65422 # Per bank write bursts -system.physmem.perBankWrBursts::11 65733 # Per bank write bursts -system.physmem.perBankWrBursts::12 64307 # Per bank write bursts -system.physmem.perBankWrBursts::13 64297 # Per bank write bursts -system.physmem.perBankWrBursts::14 64633 # Per bank write bursts -system.physmem.perBankWrBursts::15 64303 # Per bank write bursts +system.physmem.perBankRdBursts::0 119017 # Per bank write bursts +system.physmem.perBankRdBursts::1 114428 # Per bank write bursts +system.physmem.perBankRdBursts::2 116569 # Per bank write bursts +system.physmem.perBankRdBursts::3 118023 # Per bank write bursts +system.physmem.perBankRdBursts::4 118127 # Per bank write bursts +system.physmem.perBankRdBursts::5 117816 # Per bank write bursts +system.physmem.perBankRdBursts::6 120202 # Per bank write bursts +system.physmem.perBankRdBursts::7 124913 # Per bank write bursts +system.physmem.perBankRdBursts::8 127544 # Per bank write bursts +system.physmem.perBankRdBursts::9 130446 # Per bank write bursts +system.physmem.perBankRdBursts::10 129104 # Per bank write bursts +system.physmem.perBankRdBursts::11 130773 # Per bank write bursts +system.physmem.perBankRdBursts::12 126663 # Per bank write bursts +system.physmem.perBankRdBursts::13 125636 # Per bank write bursts +system.physmem.perBankRdBursts::14 122981 # Per bank write bursts +system.physmem.perBankRdBursts::15 123654 # Per bank write bursts +system.physmem.perBankWrBursts::0 61274 # Per bank write bursts +system.physmem.perBankWrBursts::1 61571 # Per bank write bursts +system.physmem.perBankWrBursts::2 60654 # Per bank write bursts +system.physmem.perBankWrBursts::3 61312 # Per bank write bursts +system.physmem.perBankWrBursts::4 61747 # Per bank write bursts +system.physmem.perBankWrBursts::5 63190 # Per bank write bursts +system.physmem.perBankWrBursts::6 64213 # Per bank write bursts +system.physmem.perBankWrBursts::7 65700 # Per bank write bursts +system.physmem.perBankWrBursts::8 65483 # Per bank write bursts +system.physmem.perBankWrBursts::9 65878 # Per bank write bursts +system.physmem.perBankWrBursts::10 65419 # Per bank write bursts +system.physmem.perBankWrBursts::11 65720 # Per bank write bursts +system.physmem.perBankWrBursts::12 64327 # Per bank write bursts +system.physmem.perBankWrBursts::13 64305 # Per bank write bursts +system.physmem.perBankWrBursts::14 64649 # Per bank write bursts +system.physmem.perBankWrBursts::15 64294 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 685487953500 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times write queue was full causing retry +system.physmem.totGap 685386422500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1966494 # Read request sizes (log2) +system.physmem.readPktSize::6 1966466 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1019774 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1645141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 231582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 69181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20030 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1019736 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1645035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 231982 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 68923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -127,235 +127,234 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 45485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 45698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 45690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 45669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 45680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 45691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 45483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 45666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 45709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 45692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 45696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 45650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 45681 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 45674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 45676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 45713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 45709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 45705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 45771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 45761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 45979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 46118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 46280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 49534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 48711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 45697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 45708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 45706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 45762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 45739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 45791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 45957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 46127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 46326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 49473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 48655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1822247 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 104.837037 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 80.099826 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 197.854977 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1460763 80.16% 80.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 186024 10.21% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 72307 3.97% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 32393 1.78% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 16822 0.92% 97.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 10551 0.58% 97.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 6953 0.38% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 6800 0.37% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 3880 0.21% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3184 0.17% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2717 0.15% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2015 0.11% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1651 0.09% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1492 0.08% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1271 0.07% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1102 0.06% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 982 0.05% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1041 0.06% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 864 0.05% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 817 0.04% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 719 0.04% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 2906 0.16% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 391 0.02% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 753 0.04% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 249 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 220 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 185 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 207 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 171 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 149 0.01% 99.85% # Bytes accessed per row activation +system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1821867 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 104.857955 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 80.098310 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 197.882118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1460616 80.17% 80.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 186071 10.21% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 71892 3.95% 94.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 32365 1.78% 96.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 16766 0.92% 97.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 10653 0.58% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 7007 0.38% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 6870 0.38% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 3886 0.21% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3166 0.17% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2723 0.15% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 1980 0.11% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1594 0.09% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1502 0.08% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1242 0.07% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 1240 0.07% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 1003 0.06% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 1017 0.06% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 831 0.05% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 807 0.04% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 751 0.04% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 2873 0.16% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 389 0.02% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 742 0.04% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 289 0.02% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 237 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 196 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 198 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 161 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 147 0.01% 99.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::1984-1985 132 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 171 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 381 0.02% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 117 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 95 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 87 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 78 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 78 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 61 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 165 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 370 0.02% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 134 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 101 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 83 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 73 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 67 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 51 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::2560-2561 72 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 41 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 45 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 36 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 45 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 35 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 29 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 23 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 49 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 40 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 35 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 42 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 36 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 34 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 27 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::3072-3073 45 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 24 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 26 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 27 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 27 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 22 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 20 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 15 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 30 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 11 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 17 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 14 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 16 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 14 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 21 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 10 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 22 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 15 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 17 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 13 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 13 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 8 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 11 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 13 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 23 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 10 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 15 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 16 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 15 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 13 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 14 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 12 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 21 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 13 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 18 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 18 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 13 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 11 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 8 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 16 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 8 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 8 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 8 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 17 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 7 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 14 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 9 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 16 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 7 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 14 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 8 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 13 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 12 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 14 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 8 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 85 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 6 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 29 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 32 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 23 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 19 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 28 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 20 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 15 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 21 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 35 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 14 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 9 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 10 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 15 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 20 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 9 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 19 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 21 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 16 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 11 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 15 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 12 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 9 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 10 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 16 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 24 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 17 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 8 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 15 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 14 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 12 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 12 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 18 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 22 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 17 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 11 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 8 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 12 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 14 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 17 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 26 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 14 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 4 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 11 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 10 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 9 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 14 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 22 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 13 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 10 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 9 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 9 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 10 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 7 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 17 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 89 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 28 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 7 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 7 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 125 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1822247 # Bytes accessed per row activation -system.physmem.totQLat 24360796250 # Total ticks spent queuing -system.physmem.totMemAccLat 84735751250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9829735000 # Total ticks spent in databus transfers -system.physmem.totBankLat 50545220000 # Total ticks spent accessing banks -system.physmem.avgQLat 12391.38 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 25710.37 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::7936-7937 7 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 123 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1821867 # Bytes accessed per row activation +system.physmem.totQLat 24443368500 # Total ticks spent queuing +system.physmem.totMemAccLat 84807426000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9829480000 # Total ticks spent in databus transfers +system.physmem.totBankLat 50534577500 # Total ticks spent accessing banks +system.physmem.avgQLat 12433.70 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 25705.62 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43101.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 183.55 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 95.21 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 183.60 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 95.21 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 43139.32 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 183.57 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 95.22 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 183.62 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 95.22 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.18 # Data bus utilization in percentage system.physmem.busUtilRead 1.43 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.12 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.63 # Average write queue length when enqueuing -system.physmem.readRowHits 818889 # Number of row buffer hits during reads -system.physmem.writeRowHits 344565 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.65 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 33.79 # Row buffer hit rate for writes -system.physmem.avgGap 229546.70 # Average gap between requests -system.physmem.pageHitRate 38.97 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 7.09 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 278810323 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1191305 # Transaction distribution -system.membus.trans_dist::ReadResp 1191305 # Transaction distribution -system.membus.trans_dist::Writeback 1019774 # Transaction distribution -system.membus.trans_dist::ReadExReq 775189 # Transaction distribution -system.membus.trans_dist::ReadExResp 775189 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952762 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4952762 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191121152 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 191121152 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 191121152 # Total data (bytes) +system.physmem.avgWrQLen 10.01 # Average write queue length when enqueuing +system.physmem.readRowHits 819101 # Number of row buffer hits during reads +system.physmem.writeRowHits 344664 # Number of row buffer hits during writes +system.physmem.readRowHitRate 41.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 33.80 # Row buffer hit rate for writes +system.physmem.avgGap 229517.77 # Average gap between requests +system.physmem.pageHitRate 38.98 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 7.14 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 278845462 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1191273 # Transaction distribution +system.membus.trans_dist::ReadResp 1191273 # Transaction distribution +system.membus.trans_dist::Writeback 1019736 # Transaction distribution +system.membus.trans_dist::ReadExReq 775193 # Transaction distribution +system.membus.trans_dist::ReadExResp 775193 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952668 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4952668 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191116928 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 191116928 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 191116928 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11874044250 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11873404000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 18494220250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18493738500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.7 # Layer utilization (%) -system.cpu.branchPred.lookups 381678235 # Number of BP lookups -system.cpu.branchPred.condPredicted 296637110 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16088915 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 262749250 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259783318 # Number of BTB hits +system.cpu.branchPred.lookups 381642976 # Number of BP lookups +system.cpu.branchPred.condPredicted 296606399 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16082111 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 262443817 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259723367 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.871193 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24705471 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3030 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.963416 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24699577 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3003 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613987676 # DTB read hits -system.cpu.dtb.read_misses 11260420 # DTB read misses +system.cpu.dtb.read_hits 613972689 # DTB read hits +system.cpu.dtb.read_misses 11257711 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625248096 # DTB read accesses -system.cpu.dtb.write_hits 212348403 # DTB write hits -system.cpu.dtb.write_misses 7134109 # DTB write misses +system.cpu.dtb.read_accesses 625230400 # DTB read accesses +system.cpu.dtb.write_hits 212364531 # DTB write hits +system.cpu.dtb.write_misses 7123508 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219482512 # DTB write accesses -system.cpu.dtb.data_hits 826336079 # DTB hits -system.cpu.dtb.data_misses 18394529 # DTB misses +system.cpu.dtb.write_accesses 219488039 # DTB write accesses +system.cpu.dtb.data_hits 826337220 # DTB hits +system.cpu.dtb.data_misses 18381219 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 844730608 # DTB accesses -system.cpu.itb.fetch_hits 391118478 # ITB hits -system.cpu.itb.fetch_misses 44 # ITB misses +system.cpu.dtb.data_accesses 844718439 # DTB accesses +system.cpu.itb.fetch_hits 391054896 # ITB hits +system.cpu.itb.fetch_misses 42 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 391118522 # ITB accesses +system.cpu.itb.fetch_accesses 391054938 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -369,138 +368,137 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1370976153 # number of cpu cycles simulated +system.cpu.numCycles 1370773091 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402585457 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3161328538 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381678235 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 284488789 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 574592396 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140681937 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 190961804 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1466 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 391118478 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8069239 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1284965558 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.460244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.144346 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402523002 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3161115412 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381642976 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284422944 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574525052 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140645567 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 190952168 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1444 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 391054896 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8064214 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1284797805 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.460399 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.144459 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 710373162 55.28% 55.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42677954 3.32% 58.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21796461 1.70% 60.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39706509 3.09% 63.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129357441 10.07% 73.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61547596 4.79% 78.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38577258 3.00% 81.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28126573 2.19% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212802604 16.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 710272753 55.28% 55.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42667609 3.32% 58.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21782496 1.70% 60.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39699327 3.09% 63.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129330544 10.07% 73.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61540269 4.79% 78.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38580495 3.00% 81.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28116157 2.19% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212808155 16.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1284965558 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.278399 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.305896 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 434593706 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 172173126 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542518914 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18856302 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116823510 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58351123 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 876 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3088655283 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2048 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116823510 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 457554918 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116845929 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6766 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535622730 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 58111705 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3006575354 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 610156 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1852925 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 51779132 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2247748999 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3899198212 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3899055356 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 142855 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1284797805 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.278414 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.306082 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 434521910 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 172167391 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542471492 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18841651 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116795361 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58349498 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 879 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3088463521 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2045 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116795361 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 457475867 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116907635 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7798 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535572514 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 58038630 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3006337354 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 608843 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1808950 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 51752219 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2247576032 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3898866654 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3898722180 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 144473 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 871546036 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 162 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 160 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 123661161 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679705832 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255482967 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67737746 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 37011786 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2724988246 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2509612209 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3204133 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 979747229 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 416253397 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1284965558 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.953058 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.971218 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 871373069 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 157 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 156 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 123546719 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679659315 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255464076 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67507479 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 36716823 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2724801247 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 120 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2509489521 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3207288 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 979575578 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 416138423 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1284797805 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.953217 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.971436 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 442955350 34.47% 34.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 203613373 15.85% 50.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185757734 14.46% 64.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153374382 11.94% 76.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133013671 10.35% 87.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80752885 6.28% 93.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65067569 5.06% 98.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15309053 1.19% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5121541 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 442944970 34.48% 34.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 203642722 15.85% 50.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185470521 14.44% 64.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153370563 11.94% 76.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133097213 10.36% 87.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80758631 6.29% 93.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65098641 5.07% 98.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15296137 1.19% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5118407 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1284965558 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1284797805 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2189478 11.81% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11923612 64.31% 76.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4426862 23.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2193136 11.83% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11923525 64.32% 76.15% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4420966 23.85% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643894908 65.50% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 110 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643778581 65.50% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 107 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 256 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 159 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 28 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 275 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 160 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 33 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued @@ -523,84 +521,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641620248 25.57% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224096461 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641602507 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224107818 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2509612209 # Type of FU issued -system.cpu.iq.rate 1.830529 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18539952 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007388 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6324036158 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3703625637 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2413191204 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1897903 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1215976 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 850771 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2527214134 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 938027 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62593572 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2509489521 # Type of FU issued +system.cpu.iq.rate 1.830711 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18537627 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007387 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6323623582 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3703265011 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2413078875 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1898180 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1217876 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 850894 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2527088869 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 938279 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62595515 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 235110169 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 263246 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 107760 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94754465 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 235063652 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 262733 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 107683 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94735574 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 95 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1543010 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 113 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1541249 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116823510 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 56431673 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1297935 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2867161807 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8942583 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679705832 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255482967 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 282108 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18553 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 107760 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10367292 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8554999 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18922291 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2462270338 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625248683 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47341871 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116795361 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 56591518 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1298088 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2866959659 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8943399 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679659315 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255464076 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 120 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 282702 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18018 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 107683 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10360004 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8558145 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18918149 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2462143246 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625230973 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47346275 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142173439 # number of nop insts executed -system.cpu.iew.exec_refs 844731223 # number of memory reference insts executed -system.cpu.iew.exec_branches 300901770 # Number of branches executed -system.cpu.iew.exec_stores 219482540 # Number of stores executed -system.cpu.iew.exec_rate 1.795998 # Inst execution rate -system.cpu.iew.wb_sent 2441991151 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2414041975 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388322535 # num instructions producing a value -system.cpu.iew.wb_consumers 1764247998 # num instructions consuming a value +system.cpu.iew.exec_nop 142158292 # number of nop insts executed +system.cpu.iew.exec_refs 844719037 # number of memory reference insts executed +system.cpu.iew.exec_branches 300873221 # Number of branches executed +system.cpu.iew.exec_stores 219488064 # Number of stores executed +system.cpu.iew.exec_rate 1.796171 # Inst execution rate +system.cpu.iew.wb_sent 2441862108 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2413929769 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388272639 # num instructions producing a value +system.cpu.iew.wb_consumers 1764258225 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.760820 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.786920 # average fanout of values written-back +system.cpu.iew.wb_rate 1.760999 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.786887 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 826708029 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 826504574 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16088134 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1168142048 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.557841 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.499033 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16081360 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1168002444 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.558028 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.499439 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 654070645 55.99% 55.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174984637 14.98% 70.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86150926 7.38% 78.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53558629 4.58% 82.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34734385 2.97% 85.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26071538 2.23% 88.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21585678 1.85% 89.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22876428 1.96% 91.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94109182 8.06% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 654033697 56.00% 56.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174911016 14.98% 70.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86140681 7.38% 78.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53576194 4.59% 82.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34697975 2.97% 85.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25994339 2.23% 88.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21604457 1.85% 89.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22883851 1.96% 91.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94160234 8.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1168142048 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1168002444 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -611,95 +609,95 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94109182 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94160234 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3634741821 # The number of ROB reads -system.cpu.rob.rob_writes 5409898345 # The number of ROB writes -system.cpu.timesIdled 948322 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 86010595 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3634347710 # The number of ROB reads +system.cpu.rob.rob_writes 5409463480 # The number of ROB writes +system.cpu.timesIdled 947782 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 85975286 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.789713 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.789713 # CPI: Total CPI of All Threads -system.cpu.ipc 1.266283 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.266283 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3318184796 # number of integer regfile reads -system.cpu.int_regfile_writes 1932088897 # number of integer regfile writes -system.cpu.fp_regfile_reads 30223 # number of floating regfile reads -system.cpu.fp_regfile_writes 511 # number of floating regfile writes +system.cpu.cpi 0.789596 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.789596 # CPI: Total CPI of All Threads +system.cpu.ipc 1.266471 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.266471 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3318031256 # number of integer regfile reads +system.cpu.int_regfile_writes 1931984794 # number of integer regfile writes +system.cpu.fp_regfile_reads 30556 # number of floating regfile reads +system.cpu.fp_regfile_writes 536 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1204982897 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7297626 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7297626 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3725040 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1883606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1883606 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085568 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22087504 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61952 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825939456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 826001408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 826001408 # Total data (bytes) +system.cpu.toL2Bus.throughput 1205179048 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7297603 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7297603 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3725230 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1883628 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1883628 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1930 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085762 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22087692 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825951744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 826013504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 826013504 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10178244432 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10178550909 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1613250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1610000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14084473000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14084464250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 776.507603 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 391116973 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 968 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 404046.459711 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 773.100738 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 391053395 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 965 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 405236.678756 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 776.507603 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.379154 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.379154 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 391116973 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 391116973 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 391116973 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 391116973 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 391116973 # number of overall hits -system.cpu.icache.overall_hits::total 391116973 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1504 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1504 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1504 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1504 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1504 # number of overall misses -system.cpu.icache.overall_misses::total 1504 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 108221250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 108221250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 108221250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 108221250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 108221250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 108221250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 391118477 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 391118477 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 391118477 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 391118477 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 391118477 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 391118477 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 773.100738 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.377491 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.377491 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 391053395 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 391053395 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 391053395 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 391053395 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 391053395 # number of overall hits +system.cpu.icache.overall_hits::total 391053395 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1501 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1501 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1501 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1501 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1501 # number of overall misses +system.cpu.icache.overall_misses::total 1501 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 108152500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 108152500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 108152500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 108152500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 108152500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 108152500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 391054896 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 391054896 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 391054896 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 391054896 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 391054896 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 391054896 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71955.618351 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71955.618351 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71955.618351 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71955.618351 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71955.618351 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71955.618351 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 344 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72053.630913 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72053.630913 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72053.630913 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72053.630913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72053.630913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72053.630913 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 156 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 114.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 78 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -709,111 +707,111 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 536 system.cpu.icache.demand_mshr_hits::total 536 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 536 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 536 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 968 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 968 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 968 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 968 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 968 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75754750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 75754750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75754750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 75754750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75754750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 75754750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 965 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 965 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 965 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75095000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 75095000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75095000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 75095000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75095000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 75095000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78259.039256 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78259.039256 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78259.039256 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 78259.039256 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78259.039256 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 78259.039256 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77818.652850 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77818.652850 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77818.652850 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77818.652850 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77818.652850 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77818.652850 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1933792 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31423.528987 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9058568 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1963567 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.613323 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 1933762 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31423.393947 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9058762 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1963540 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.613485 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 28354220250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14586.952110 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.526107 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16810.050770 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.445158 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000810 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 14586.517425 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.834239 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16810.042284 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.445145 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000819 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.513002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.958970 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 6106321 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6106321 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3725040 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3725040 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108417 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108417 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7214738 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7214738 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7214738 # number of overall hits -system.cpu.l2cache.overall_hits::total 7214738 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 968 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1190337 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1191305 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 775189 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 775189 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 968 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1965526 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1966494 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 968 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1965526 # number of overall misses -system.cpu.l2cache.overall_misses::total 1966494 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 74779750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 102580412000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 102655191750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 67293864000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 67293864000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 74779750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 169874276000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 169949055750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 74779750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 169874276000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 169949055750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 968 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7296658 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7297626 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3725040 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3725040 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883606 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1883606 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 968 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9180264 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9181232 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 968 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9180264 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9181232 # number of overall (read+write) accesses +system.cpu.l2cache.tags.occ_percent::total 0.958966 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 6106330 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6106330 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3725230 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3725230 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108435 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108435 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7214765 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7214765 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7214765 # number of overall hits +system.cpu.l2cache.overall_hits::total 7214765 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 965 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1190308 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1191273 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 775193 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 775193 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 965 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1965501 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1966466 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 965 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1965501 # number of overall misses +system.cpu.l2cache.overall_misses::total 1966466 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 74125000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 102633894750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 102708019750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 67309627250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 67309627250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 74125000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 169943522000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 170017647000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 74125000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 169943522000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 170017647000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 965 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7296638 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7297603 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3725230 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3725230 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883628 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1883628 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 965 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9180266 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9181231 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 965 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9180266 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9181231 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163135 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.163246 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411545 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.411545 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163131 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163242 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411543 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.411543 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214103 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214186 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214101 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214183 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.214103 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214186 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77251.807851 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 86177.621968 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 86170.369259 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86809.621912 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86809.621912 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77251.807851 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86426.878098 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86422.361701 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77251.807851 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86426.878098 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86422.361701 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214101 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214183 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76813.471503 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 86224.653409 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 86217.029808 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86829.508587 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86829.508587 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76813.471503 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86463.208108 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86458.472712 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76813.471503 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86463.208108 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86458.472712 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -822,180 +820,180 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1019774 # number of writebacks -system.cpu.l2cache.writebacks::total 1019774 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190337 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1191305 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775189 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 775189 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 968 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1965526 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1966494 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 968 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1965526 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1966494 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 62594250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 87638263500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 87700857750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 57538532000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 57538532000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 62594250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 145176795500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 145239389750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 62594250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 145176795500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 145239389750 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1019736 # number of writebacks +system.cpu.l2cache.writebacks::total 1019736 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190308 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1191273 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775193 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 775193 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1965501 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1966466 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1965501 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1966466 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 61971000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 87692417750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 87754388750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 57554177250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 57554177250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61971000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 145246595000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 145308566000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61971000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 145246595000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 145308566000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163135 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163246 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411545 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411545 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163131 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163242 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411543 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411543 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214103 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214186 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214101 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214183 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214103 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214186 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64663.481405 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73624.749546 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 73617.468029 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74225.165734 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74225.165734 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64663.481405 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73861.549275 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73857.021557 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64663.481405 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73861.549275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73857.021557 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214101 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214183 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64218.652850 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73672.039296 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 73664.381506 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74244.965125 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74244.965125 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64218.652850 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73898.001069 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73893.251142 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64218.652850 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73898.001069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73893.251142 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9176168 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.562922 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 694279443 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9180264 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 75.627394 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 9176170 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.561673 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 694256138 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9180266 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 75.624839 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 5178034250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.562922 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.561673 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997940 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997940 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 538739511 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 538739511 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155539929 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155539929 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 694279440 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694279440 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 694279440 # number of overall hits -system.cpu.dcache.overall_hits::total 694279440 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11387381 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11387381 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5188573 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5188573 # number of WriteReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 538716411 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 538716411 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155539725 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155539725 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 694256136 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694256136 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 694256136 # number of overall hits +system.cpu.dcache.overall_hits::total 694256136 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11395033 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11395033 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5188777 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5188777 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16575954 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16575954 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16575954 # number of overall misses -system.cpu.dcache.overall_misses::total 16575954 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 342766302500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 342766302500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 296010973410 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 296010973410 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 274500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 274500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 638777275910 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 638777275910 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 638777275910 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 638777275910 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 550126892 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 550126892 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 16583810 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16583810 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16583810 # number of overall misses +system.cpu.dcache.overall_misses::total 16583810 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 343354515500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 343354515500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 296317441834 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 296317441834 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 92250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 639671957334 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 639671957334 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 639671957334 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 639671957334 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 550111444 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 550111444 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710855394 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710855394 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710855394 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710855394 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020700 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020700 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032282 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032282 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023318 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023318 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023318 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023318 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30100.538702 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30100.538702 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57050.555791 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57050.555791 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 274500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 274500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38536.380827 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38536.380827 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38536.380827 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38536.380827 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12380978 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8648655 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 745505 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.607505 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 132.782495 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 710839946 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710839946 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710839946 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710839946 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020714 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020714 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032283 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032283 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023330 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023330 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023330 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023330 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30131.945691 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30131.945691 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57107.376523 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57107.376523 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38572.074652 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38572.074652 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38572.074652 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38572.074652 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12375504 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8646342 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 745563 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65135 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.598871 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 132.744945 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3725040 # number of writebacks -system.cpu.dcache.writebacks::total 3725040 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4090717 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4090717 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3304974 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3304974 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7395691 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7395691 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7395691 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7395691 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296664 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296664 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883599 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883599 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3725230 # number of writebacks +system.cpu.dcache.writebacks::total 3725230 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4098384 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4098384 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3305161 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3305161 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7403545 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7403545 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7403545 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7403545 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296649 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296649 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883616 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883616 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180263 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180263 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180263 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180263 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171778792500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 171778792500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80694684874 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 80694684874 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 272500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 272500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 252473477374 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 252473477374 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 252473477374 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 252473477374 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9180265 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180265 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180265 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180265 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171833895250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 171833895250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80710616128 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 80710616128 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 89750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 89750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 252544511378 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 252544511378 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 252544511378 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 252544511378 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013264 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013264 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012914 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012914 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012914 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012914 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23542.099855 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23542.099855 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42840.692140 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42840.692140 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 272500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 272500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27501.769543 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27501.769543 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27501.769543 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27501.769543 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012915 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012915 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23549.700040 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23549.700040 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42848.763298 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42848.763298 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 89750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 89750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27509.501237 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27509.501237 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27509.501237 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27509.501237 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 30ce01df4..d4b45072d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,18 +173,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -202,16 +216,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -220,22 +237,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -244,22 +265,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -268,10 +293,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -280,124 +307,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -406,10 +454,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -418,16 +468,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -436,10 +489,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -450,6 +505,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -472,14 +528,17 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -498,12 +557,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -514,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -536,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -560,7 +625,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -574,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -598,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -609,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 7989e6703..19d70b574 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.533691 # Number of seconds simulated -sim_ticks 533690503000 # Number of ticks simulated -final_tick 533690503000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.533797 # Number of seconds simulated +sim_ticks 533797009000 # Number of ticks simulated +final_tick 533797009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128085 # Simulator instruction rate (inst/s) -host_op_rate 142888 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44256929 # Simulator tick rate (ticks/s) -host_mem_usage 275676 # Number of bytes of host memory used -host_seconds 12058.91 # Real time elapsed on the host +host_inst_rate 102910 # Simulator instruction rate (inst/s) +host_op_rate 114803 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35565366 # Simulator tick rate (ticks/s) +host_mem_usage 295220 # Number of bytes of host memory used +host_seconds 15008.90 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 47744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143713600 # Number of bytes read from this memory -system.physmem.bytes_read::total 143761344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70434112 # Number of bytes written to this memory -system.physmem.bytes_written::total 70434112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 746 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245525 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246271 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100533 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100533 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 89460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 269282663 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 269372123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 89460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 131975577 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 131975577 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 131975577 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 89460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 269282663 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 401347700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246271 # Number of read requests accepted -system.physmem.writeReqs 1100533 # Number of write requests accepted -system.physmem.readBursts 2246271 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1100533 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 143722048 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 39296 # Total number of bytes read from write queue -system.physmem.bytesWritten 70432960 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 143761344 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 70434112 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 614 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 47680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143743296 # Number of bytes read from this memory +system.physmem.bytes_read::total 143790976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70431872 # Number of bytes written to this memory +system.physmem.bytes_written::total 70431872 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 745 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2245989 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246734 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100498 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100498 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 89322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 269284566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 269373889 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 89322 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89322 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 131945048 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 131945048 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 131945048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 89322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 269284566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 401318937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246734 # Number of read requests accepted +system.physmem.writeReqs 1100498 # Number of write requests accepted +system.physmem.readBursts 2246734 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1100498 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 143754112 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 36864 # Total number of bytes read from write queue +system.physmem.bytesWritten 70430784 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 143790976 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 70431872 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 576 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 139609 # Per bank write bursts -system.physmem.perBankRdBursts::1 136206 # Per bank write bursts -system.physmem.perBankRdBursts::2 133832 # Per bank write bursts -system.physmem.perBankRdBursts::3 136344 # Per bank write bursts -system.physmem.perBankRdBursts::4 135019 # Per bank write bursts -system.physmem.perBankRdBursts::5 135288 # Per bank write bursts -system.physmem.perBankRdBursts::6 136231 # Per bank write bursts -system.physmem.perBankRdBursts::7 136121 # Per bank write bursts -system.physmem.perBankRdBursts::8 143692 # Per bank write bursts -system.physmem.perBankRdBursts::9 146373 # Per bank write bursts -system.physmem.perBankRdBursts::10 144432 # Per bank write bursts -system.physmem.perBankRdBursts::11 146294 # Per bank write bursts -system.physmem.perBankRdBursts::12 145666 # Per bank write bursts -system.physmem.perBankRdBursts::13 146070 # Per bank write bursts -system.physmem.perBankRdBursts::14 142065 # Per bank write bursts -system.physmem.perBankRdBursts::15 142415 # Per bank write bursts -system.physmem.perBankWrBursts::0 69121 # Per bank write bursts -system.physmem.perBankWrBursts::1 67439 # Per bank write bursts -system.physmem.perBankWrBursts::2 65729 # Per bank write bursts -system.physmem.perBankWrBursts::3 66294 # Per bank write bursts -system.physmem.perBankWrBursts::4 66241 # Per bank write bursts -system.physmem.perBankWrBursts::5 66403 # Per bank write bursts -system.physmem.perBankWrBursts::6 67965 # Per bank write bursts -system.physmem.perBankWrBursts::7 68773 # Per bank write bursts -system.physmem.perBankWrBursts::8 70328 # Per bank write bursts -system.physmem.perBankWrBursts::9 70962 # Per bank write bursts -system.physmem.perBankWrBursts::10 70540 # Per bank write bursts -system.physmem.perBankWrBursts::11 70927 # Per bank write bursts -system.physmem.perBankWrBursts::12 70302 # Per bank write bursts -system.physmem.perBankWrBursts::13 70806 # Per bank write bursts -system.physmem.perBankWrBursts::14 69598 # Per bank write bursts -system.physmem.perBankWrBursts::15 69087 # Per bank write bursts +system.physmem.perBankRdBursts::0 139750 # Per bank write bursts +system.physmem.perBankRdBursts::1 136273 # Per bank write bursts +system.physmem.perBankRdBursts::2 133708 # Per bank write bursts +system.physmem.perBankRdBursts::3 136246 # Per bank write bursts +system.physmem.perBankRdBursts::4 134906 # Per bank write bursts +system.physmem.perBankRdBursts::5 135253 # Per bank write bursts +system.physmem.perBankRdBursts::6 136175 # Per bank write bursts +system.physmem.perBankRdBursts::7 136295 # Per bank write bursts +system.physmem.perBankRdBursts::8 143732 # Per bank write bursts +system.physmem.perBankRdBursts::9 146555 # Per bank write bursts +system.physmem.perBankRdBursts::10 144302 # Per bank write bursts +system.physmem.perBankRdBursts::11 146237 # Per bank write bursts +system.physmem.perBankRdBursts::12 145788 # Per bank write bursts +system.physmem.perBankRdBursts::13 146277 # Per bank write bursts +system.physmem.perBankRdBursts::14 142119 # Per bank write bursts +system.physmem.perBankRdBursts::15 142542 # Per bank write bursts +system.physmem.perBankWrBursts::0 69128 # Per bank write bursts +system.physmem.perBankWrBursts::1 67452 # Per bank write bursts +system.physmem.perBankWrBursts::2 65650 # Per bank write bursts +system.physmem.perBankWrBursts::3 66298 # Per bank write bursts +system.physmem.perBankWrBursts::4 66182 # Per bank write bursts +system.physmem.perBankWrBursts::5 66379 # Per bank write bursts +system.physmem.perBankWrBursts::6 67939 # Per bank write bursts +system.physmem.perBankWrBursts::7 68869 # Per bank write bursts +system.physmem.perBankWrBursts::8 70353 # Per bank write bursts +system.physmem.perBankWrBursts::9 70986 # Per bank write bursts +system.physmem.perBankWrBursts::10 70505 # Per bank write bursts +system.physmem.perBankWrBursts::11 70955 # Per bank write bursts +system.physmem.perBankWrBursts::12 70250 # Per bank write bursts +system.physmem.perBankWrBursts::13 70819 # Per bank write bursts +system.physmem.perBankWrBursts::14 69624 # Per bank write bursts +system.physmem.perBankWrBursts::15 69092 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 533690432500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 533796944500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2246271 # Read request sizes (log2) +system.physmem.readPktSize::6 2246734 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1100533 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1620463 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 446151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 135620 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 43412 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1100498 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1621551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 445207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 135727 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 43660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -127,217 +127,215 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 48877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 49049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 49091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 49066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 49073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 49089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 49084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 49051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 49094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 49119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 49113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 49182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 49203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 49260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 49489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 49964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 50324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 52085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 51901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 51517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 52884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 52174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 48879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 49064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 49063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 49078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 49086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 49106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 49070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 49088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 49113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 49112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 49119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 49167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 49186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 49268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 49533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 49888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 50325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 52053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 51988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 51535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 52936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 52147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2077885 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.053834 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 79.951836 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 184.653120 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1660855 79.93% 79.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 226890 10.92% 90.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 69105 3.33% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 37676 1.81% 95.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 25011 1.20% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 12112 0.58% 97.77% # Bytes accessed per row activation +system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 2077673 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.074669 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 79.977753 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 184.400722 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1659880 79.89% 79.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 227444 10.95% 90.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 69322 3.34% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 37684 1.81% 95.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 24960 1.20% 97.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 12074 0.58% 97.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::448-449 8272 0.40% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 8103 0.39% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 4494 0.22% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3425 0.16% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2747 0.13% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2032 0.10% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1669 0.08% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1441 0.07% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1240 0.06% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1051 0.05% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 987 0.05% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 902 0.04% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 711 0.03% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 8168 0.39% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 4452 0.21% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3374 0.16% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2842 0.14% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2038 0.10% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1716 0.08% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1451 0.07% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1190 0.06% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 1071 0.05% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 949 0.05% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 909 0.04% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 717 0.03% 99.56% # Bytes accessed per row activation system.physmem.bytesPerActivate::1280-1281 682 0.03% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 694 0.03% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3096 0.15% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 406 0.02% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 291 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 190 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 185 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 205 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 473 0.02% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 132 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 131 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 122 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 122 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 103 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 129 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 71 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 83 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 90 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 83 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 94 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 68 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 57 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 64 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 70 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 60 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 55 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 48 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 43 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 58 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 55 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 43 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 33 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 30 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 32 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 24 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 28 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 19 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 34 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 24 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 26 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 14 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 19 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 24 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 24 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 17 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 19 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 19 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 21 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 13 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 17 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 15 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 21 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 12 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 20 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 12 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 676 0.03% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 3081 0.15% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 420 0.02% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 289 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 203 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 186 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 219 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 499 0.02% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 133 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 143 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 125 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 127 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 94 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 128 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 92 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 97 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 82 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 82 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 62 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 59 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 52 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 72 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 47 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 62 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 51 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 51 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 39 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 48 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 40 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 42 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 28 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 34 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 28 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 44 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 23 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 30 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 29 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 27 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 28 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 16 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 17 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 28 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 15 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 19 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 9 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 25 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 15 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 12 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 18 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 18 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 19 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 22 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 11 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 34 0.00% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::4800-4801 14 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 13 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 16 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 16 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 27 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 36 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 17 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 14 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 16 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 187 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 8 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 12 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 7 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 17 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 11 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 23 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 14 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 20 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 13 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 17 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 15 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 185 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 13 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 17 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 2 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 9 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 13 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 14 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 8 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 12 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 9 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 34 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 7 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 16 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 38 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 8 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::7040-7041 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 26 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 4 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 4 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 3 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 3 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 13 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 83 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2077885 # Bytes accessed per row activation -system.physmem.totQLat 32824703500 # Total ticks spent queuing -system.physmem.totMemAccLat 104040704750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 11228285000 # Total ticks spent in databus transfers -system.physmem.totBankLat 59987716250 # Total ticks spent accessing banks -system.physmem.avgQLat 14616.97 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 26712.77 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::8192-8193 82 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2077673 # Bytes accessed per row activation +system.physmem.totQLat 32821468000 # Total ticks spent queuing +system.physmem.totMemAccLat 104059554250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 11230790000 # Total ticks spent in databus transfers +system.physmem.totBankLat 60007296250 # Total ticks spent accessing banks +system.physmem.avgQLat 14612.27 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 26715.53 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46329.74 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 46327.80 # Average memory access latency per DRAM burst system.physmem.avgRdBW 269.30 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 131.97 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 131.94 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 269.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 131.98 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 131.95 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.13 # Data bus utilization in percentage system.physmem.busUtilRead 2.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.08 # Average write queue length when enqueuing -system.physmem.readRowHits 931610 # Number of row buffer hits during reads -system.physmem.writeRowHits 336677 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 30.59 # Row buffer hit rate for writes -system.physmem.avgGap 159462.71 # Average gap between requests -system.physmem.pageHitRate 37.90 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 5.89 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 401347580 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1419678 # Transaction distribution -system.membus.trans_dist::ReadResp 1419677 # Transaction distribution -system.membus.trans_dist::Writeback 1100533 # Transaction distribution -system.membus.trans_dist::ReadExReq 826593 # Transaction distribution -system.membus.trans_dist::ReadExResp 826593 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5593074 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214195392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 214195392 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 214195392 # Total data (bytes) +system.physmem.avgWrQLen 10.35 # Average write queue length when enqueuing +system.physmem.readRowHits 932509 # Number of row buffer hits during reads +system.physmem.writeRowHits 336457 # Number of row buffer hits during writes +system.physmem.readRowHitRate 41.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 30.57 # Row buffer hit rate for writes +system.physmem.avgGap 159474.14 # Average gap between requests +system.physmem.pageHitRate 37.92 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 5.98 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 401318817 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1420235 # Transaction distribution +system.membus.trans_dist::ReadResp 1420234 # Transaction distribution +system.membus.trans_dist::Writeback 1100498 # Transaction distribution +system.membus.trans_dist::ReadExReq 826499 # Transaction distribution +system.membus.trans_dist::ReadExResp 826499 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593965 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5593965 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214222784 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 214222784 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 214222784 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12924294750 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 12926153000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 21079818750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.9 # Layer utilization (%) -system.cpu.branchPred.lookups 303467870 # Number of BP lookups -system.cpu.branchPred.condPredicted 249715061 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15195903 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 175178105 # Number of BTB lookups -system.cpu.branchPred.BTBHits 161776963 # Number of BTB hits +system.membus.respLayer1.occupancy 21085487000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.0 # Layer utilization (%) +system.cpu.branchPred.lookups 303451211 # Number of BP lookups +system.cpu.branchPred.condPredicted 249690817 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15200865 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 174297258 # Number of BTB lookups +system.cpu.branchPred.BTBHits 161770128 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.349990 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17540871 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 204 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.812779 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17550277 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 188 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -381,133 +379,132 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1067381007 # number of cpu cycles simulated +system.cpu.numCycles 1067594019 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 299148062 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2189533318 # Number of instructions fetch has processed -system.cpu.fetch.Branches 303467870 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 179317834 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 435752088 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 88086251 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 164106751 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 339 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 289566494 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5997594 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 968963067 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.499628 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.206367 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 299164557 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2189663567 # Number of instructions fetch has processed +system.cpu.fetch.Branches 303451211 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 179320405 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 435777521 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 88106670 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 164181608 # Number of cycles fetch has spent blocked +system.cpu.fetch.PendingTrapStallCycles 55 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 289571528 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5986152 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 969098859 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.499353 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.206220 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 533211067 55.03% 55.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25485631 2.63% 57.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39032754 4.03% 61.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48282665 4.98% 66.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43767932 4.52% 71.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46382840 4.79% 75.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38389210 3.96% 79.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18960850 1.96% 81.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175450118 18.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 533321418 55.03% 55.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25465587 2.63% 57.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39057125 4.03% 61.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48306210 4.98% 66.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43759030 4.52% 71.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46389880 4.79% 75.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38408230 3.96% 79.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18944401 1.95% 81.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175446978 18.10% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 968963067 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.284311 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.051314 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 331377153 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 141962670 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 405350137 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20317948 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 69955159 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46017147 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 694 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2369104960 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2426 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 69955159 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 354884990 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 70530339 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17935 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 400511119 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 73063525 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2306250708 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 150920 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5011927 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 60136403 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 4 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2282159345 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10649371145 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9763416611 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 460 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 969098859 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.284238 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.051026 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 331405346 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 142029656 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 405372937 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20316462 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69974458 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46022119 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 690 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2369134638 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2461 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 69974458 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 354905741 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 70599540 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20110 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 400539970 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 73059040 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2306329085 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 151792 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5017639 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 60125136 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2282204226 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10649650977 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9763673843 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 354 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 575839415 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 404 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 401 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 160989021 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624749088 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220784728 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 85932352 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 70842412 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2202316968 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 440 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2018777354 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4015619 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 474672323 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1127531541 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 270 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 968963067 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.083441 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906294 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 575884296 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 843 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 840 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 160951749 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624757210 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220789926 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 85935761 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 70812981 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2202388527 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 863 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2018815703 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4014611 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 474721541 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1127548434 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 693 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 969098859 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.083189 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906427 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 286087063 29.53% 29.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 153648666 15.86% 45.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 160841319 16.60% 61.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120316001 12.42% 74.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 123517924 12.75% 87.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73816539 7.62% 94.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38325528 3.96% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9889728 1.02% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2520299 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 286260209 29.54% 29.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 153575867 15.85% 45.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 160890539 16.60% 61.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120276383 12.41% 74.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 123547545 12.75% 87.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73803065 7.62% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38319485 3.95% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9898934 1.02% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2526832 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 968963067 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 969098859 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 895423 3.74% 3.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5601 0.02% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18274862 76.27% 80.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4786167 19.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 899836 3.76% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5555 0.02% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18259038 76.22% 80.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4790984 20.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236899038 61.27% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 924736 0.05% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236944304 61.27% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 924745 0.05% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -529,90 +526,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 48 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 39 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587872837 29.12% 90.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193080663 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587884247 29.12% 90.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193062337 9.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2018777354 # Type of FU issued -system.cpu.iq.rate 1.891337 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23962053 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011870 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5034495136 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2677178912 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1957310102 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 311 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 694 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 129 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2042739250 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 157 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64569425 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2018815703 # Type of FU issued +system.cpu.iq.rate 1.890996 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23955413 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011866 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5034700006 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2677299944 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957368325 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 283 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 522 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 110 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2042770975 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 141 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64606441 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138822319 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 268987 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192391 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45937683 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138830441 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 271664 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192064 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45942881 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4778132 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4771033 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 69955159 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 33483642 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1603224 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2202317539 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7879544 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624749088 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220784728 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 378 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 478707 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 97428 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192391 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8138332 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9600465 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17738797 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1988042975 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 574015030 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30734379 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69974458 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 33522833 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1603829 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2202389482 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7882723 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624757210 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220789926 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 801 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 479284 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 97151 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192064 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8143428 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9602990 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17746418 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1988074209 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 574028107 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30741494 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 131 # number of nop insts executed -system.cpu.iew.exec_refs 764217607 # number of memory reference insts executed -system.cpu.iew.exec_branches 238311346 # Number of branches executed -system.cpu.iew.exec_stores 190202577 # Number of stores executed -system.cpu.iew.exec_rate 1.862543 # Inst execution rate -system.cpu.iew.wb_sent 1965731650 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1957310231 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1295404026 # num instructions producing a value -system.cpu.iew.wb_consumers 2059270839 # num instructions consuming a value +system.cpu.iew.exec_nop 92 # number of nop insts executed +system.cpu.iew.exec_refs 764206037 # number of memory reference insts executed +system.cpu.iew.exec_branches 238324356 # Number of branches executed +system.cpu.iew.exec_stores 190177930 # Number of stores executed +system.cpu.iew.exec_rate 1.862201 # Inst execution rate +system.cpu.iew.wb_sent 1965784253 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957368435 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1295422958 # num instructions producing a value +system.cpu.iew.wb_consumers 2059236430 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.833750 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.629060 # average fanout of values written-back +system.cpu.iew.wb_rate 1.833439 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.629079 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 479343339 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 479415060 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15195240 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 899007908 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.916639 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.718451 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15200205 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 899124401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.916391 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.718302 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 410513863 45.66% 45.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193235979 21.49% 67.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72768373 8.09% 75.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35278706 3.92% 79.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18862057 2.10% 81.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30820454 3.43% 84.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19957331 2.22% 86.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11398634 1.27% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106172511 11.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 410581675 45.66% 45.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193287424 21.50% 67.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72783200 8.09% 75.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35268105 3.92% 79.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18874620 2.10% 81.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30803459 3.43% 84.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19949403 2.22% 86.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11408599 1.27% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106167916 11.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 899007908 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 899124401 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -623,90 +620,90 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106172511 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106167916 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2995251990 # The number of ROB reads -system.cpu.rob.rob_writes 4474939624 # The number of ROB writes -system.cpu.timesIdled 1152982 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 98417940 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2995444799 # The number of ROB reads +system.cpu.rob.rob_writes 4475102834 # The number of ROB writes +system.cpu.timesIdled 1153332 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 98495160 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.691057 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.691057 # CPI: Total CPI of All Threads -system.cpu.ipc 1.447059 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.447059 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9956212388 # number of integer regfile reads -system.cpu.int_regfile_writes 1937181821 # number of integer regfile writes -system.cpu.fp_regfile_reads 130 # number of floating regfile reads -system.cpu.fp_regfile_writes 139 # number of floating regfile writes -system.cpu.misc_regfile_reads 737624314 # number of misc regfile reads +system.cpu.cpi 0.691195 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.691195 # CPI: Total CPI of All Threads +system.cpu.ipc 1.446770 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.446770 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9956366000 # number of integer regfile reads +system.cpu.int_regfile_writes 1937254103 # number of integer regfile writes +system.cpu.fp_regfile_reads 112 # number of floating regfile reads +system.cpu.fp_regfile_writes 111 # number of floating regfile writes +system.cpu.misc_regfile_reads 737634139 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1605146644 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7709082 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7709081 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3782685 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1893414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1893414 # Transaction distribution +system.cpu.toL2Bus.throughput 1604602532 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7709032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7709031 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3780837 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1893445 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1893445 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1548 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22986128 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22987676 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22984242 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22985790 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856601984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 856651520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 856651520 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856482496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 856532032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 856532032 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10475431595 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10472653342 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1294249 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1293249 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14768966243 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14769367993 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 22 # number of replacements -system.cpu.icache.tags.tagsinuse 628.527972 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 289565308 # Total number of references to valid blocks. +system.cpu.icache.tags.replacements 20 # number of replacements +system.cpu.icache.tags.tagsinuse 628.438821 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 289570320 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 774 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 374115.385013 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 374121.860465 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 628.527972 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.306898 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.306898 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 289565308 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 289565308 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 289565308 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 289565308 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 289565308 # number of overall hits -system.cpu.icache.overall_hits::total 289565308 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1186 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1186 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1186 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1186 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1186 # number of overall misses -system.cpu.icache.overall_misses::total 1186 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 82924749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 82924749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 82924749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 82924749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 82924749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 82924749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 289566494 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 289566494 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 289566494 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 289566494 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 289566494 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 289566494 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 628.438821 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.306855 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.306855 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 289570320 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 289570320 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 289570320 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 289570320 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 289570320 # number of overall hits +system.cpu.icache.overall_hits::total 289570320 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1208 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1208 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1208 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1208 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1208 # number of overall misses +system.cpu.icache.overall_misses::total 1208 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 83080499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 83080499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 83080499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 83080499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 83080499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 83080499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 289571528 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 289571528 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 289571528 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 289571528 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 289571528 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 289571528 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69919.687184 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69919.687184 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69919.687184 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69919.687184 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69919.687184 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69919.687184 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68775.247517 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68775.247517 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68775.247517 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68775.247517 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68775.247517 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68775.247517 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 202 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -715,120 +712,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 50.500000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 412 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 412 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 412 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 412 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 412 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 412 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 434 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 434 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 434 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 434 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 434 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 434 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 774 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 774 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 774 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 57029751 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 57029751 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 57029751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 57029751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 57029751 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 57029751 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56793251 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 56793251 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56793251 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 56793251 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56793251 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 56793251 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73681.848837 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73681.848837 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73681.848837 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73681.848837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73681.848837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73681.848837 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73376.293282 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73376.293282 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73376.293282 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73376.293282 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73376.293282 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73376.293282 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 2213583 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31532.604049 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9247674 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2243357 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.122248 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 2214050 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31533.035321 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9245310 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2243823 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.120338 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 21623958250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14306.578053 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.421352 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 17205.604643 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.436602 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000623 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.525073 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.962299 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6289369 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6289396 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3782685 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3782685 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1066821 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1066821 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7356190 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7356217 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7356190 # number of overall hits -system.cpu.l2cache.overall_hits::total 7356217 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 747 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1418939 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1419686 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 826593 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 826593 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 747 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2245532 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2246279 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 747 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2245532 # number of overall misses -system.cpu.l2cache.overall_misses::total 2246279 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 55980750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 125563538750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 125619519500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 76414651500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 76414651500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 55980750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 201978190250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 202034171000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 55980750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 201978190250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 202034171000 # number of overall miss cycles +system.cpu.l2cache.tags.occ_blocks::writebacks 14302.277072 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.244042 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 17210.514207 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.436471 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000618 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.525223 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.962312 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6288761 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6288789 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3780837 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3780837 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1066946 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1066946 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7355707 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7355735 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7355707 # number of overall hits +system.cpu.l2cache.overall_hits::total 7355735 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 746 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1419497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1420243 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 826499 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 826499 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 746 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2245996 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2246742 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 746 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2245996 # number of overall misses +system.cpu.l2cache.overall_misses::total 2246742 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 55733750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 125730219750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 125785953500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 76291008750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 76291008750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 55733750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 202021228500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 202076962250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 55733750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 202021228500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 202076962250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 774 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7708308 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7709082 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3782685 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3782685 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893414 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1893414 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7708258 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7709032 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3780837 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3780837 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893445 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1893445 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 774 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9601722 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9602496 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9601703 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9602477 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 774 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9601722 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9602496 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965116 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184079 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.184158 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436562 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.436562 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965116 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.233868 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.233927 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965116 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.233868 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.233927 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74940.763052 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88491.146378 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 88484.016536 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92445.316498 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92445.316498 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74940.763052 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89946.698711 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 89941.708488 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74940.763052 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89946.698711 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 89941.708488 # average overall miss latency +system.cpu.l2cache.overall_accesses::cpu.data 9601703 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9602477 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963824 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184153 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.184231 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436505 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.436505 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963824 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.233916 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.233975 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963824 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.233916 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.233975 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74710.120643 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88573.783354 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 88566.501296 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92306.232373 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92306.232373 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74710.120643 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89947.278846 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 89942.219556 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74710.120643 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89947.278846 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 89942.219556 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -837,8 +834,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1100533 # number of writebacks -system.cpu.l2cache.writebacks::total 1100533 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1100498 # number of writebacks +system.cpu.l2cache.writebacks::total 1100498 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits @@ -848,176 +845,176 @@ system.cpu.l2cache.demand_mshr_hits::total 8 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 746 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1418932 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1419678 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826593 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 826593 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 746 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2245525 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2246271 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 746 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2245525 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2246271 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 46519250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 107766607500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 107813126750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 66030369000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 66030369000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 46519250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 173796976500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 173843495750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 46519250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173796976500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 173843495750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.963824 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184078 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184157 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436562 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436562 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963824 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233867 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.233926 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963824 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233867 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.233926 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62358.243968 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75949.099393 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75941.957789 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79882.564938 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79882.564938 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62358.243968 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77397.034769 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77392.040297 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62358.243968 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77397.034769 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77392.040297 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 745 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419490 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1420235 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826499 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 826499 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 745 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2245989 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2246734 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 745 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2245989 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2246734 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 46285250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 107925588000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 107971873250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 65906925250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 65906925250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 46285250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 173832513250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 173878798500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 46285250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173832513250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 173878798500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962532 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184152 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184230 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436505 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436505 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962532 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233916 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.233974 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962532 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233916 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.233974 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62127.852349 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 76031.242207 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76023.949030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79742.292792 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79742.292792 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62127.852349 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77396.867594 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77391.804504 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62127.852349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77396.867594 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77391.804504 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9597625 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.040332 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 656028832 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9601721 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 68.324088 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 9597606 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.041920 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 656019476 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9601702 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 68.323249 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 3547188250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.040332 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.041920 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998057 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998057 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 489072771 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 489072771 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 166955934 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 166955934 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 66 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 66 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 489062653 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 489062653 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 166956698 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166956698 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 64 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 64 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 656028705 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 656028705 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 656028705 # number of overall hits -system.cpu.dcache.overall_hits::total 656028705 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11514039 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11514039 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5630113 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5630113 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 656019351 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 656019351 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 656019351 # number of overall hits +system.cpu.dcache.overall_hits::total 656019351 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11507496 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11507496 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5629349 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5629349 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17144152 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17144152 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17144152 # number of overall misses -system.cpu.dcache.overall_misses::total 17144152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 363445631238 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 363445631238 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 307798034677 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 307798034677 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 225500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 225500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 671243665915 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 671243665915 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 671243665915 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 671243665915 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500586810 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500586810 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17136845 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17136845 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17136845 # number of overall misses +system.cpu.dcache.overall_misses::total 17136845 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 363702842488 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 363702842488 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 307744962906 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 307744962906 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 224500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 671447805394 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 671447805394 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 671447805394 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 671447805394 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500570149 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500570149 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 69 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 69 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673172857 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673172857 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673172857 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673172857 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023001 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.023001 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032622 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032622 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.043478 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043478 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025468 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025468 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025468 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025468 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31565.433402 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31565.433402 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54669.956833 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54669.956833 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 75166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 75166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39152.923161 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39152.923161 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39152.923161 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39152.923161 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24614592 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3988980 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1212230 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65133 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.305216 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61.243609 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 673156196 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673156196 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673156196 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673156196 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022989 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022989 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032618 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032618 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025457 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025457 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025457 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025457 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31605.732688 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31605.732688 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54667.948799 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54667.948799 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 74833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 74833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39181.529937 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39181.529937 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39181.529937 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39181.529937 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24597243 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3988018 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1212289 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65131 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.289917 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61.230720 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3782685 # number of writebacks -system.cpu.dcache.writebacks::total 3782685 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3805731 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3805731 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3736699 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3736699 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3780837 # number of writebacks +system.cpu.dcache.writebacks::total 3780837 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3799238 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3799238 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3735904 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3735904 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7542430 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7542430 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7542430 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7542430 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708308 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7708308 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893414 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893414 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9601722 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9601722 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9601722 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9601722 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198054864257 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 198054864257 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89469568032 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 89469568032 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287524432289 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 287524432289 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287524432289 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 287524432289 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 7535142 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7535142 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7535142 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7535142 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708258 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7708258 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893445 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893445 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9601703 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9601703 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9601703 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9601703 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198213123757 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 198213123757 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89346986214 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 89346986214 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287560109971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 287560109971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287560109971 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 287560109971 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015399 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015399 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014263 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25693.688454 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25693.688454 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47253.040292 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47253.040292 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29945.090296 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29945.090296 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29945.090296 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29945.090296 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014264 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014264 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014264 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014264 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25714.386280 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25714.386280 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47187.526553 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47187.526553 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29948.865318 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29948.865318 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29948.865318 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29948.865318 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index c08f958c6..8a347565f 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -56,6 +60,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fetchBuffSize=4 function_trace=false function_trace_start=0 @@ -90,6 +95,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -105,6 +111,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -127,11 +134,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -140,6 +149,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -162,17 +172,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -181,6 +195,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -203,12 +218,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -218,6 +235,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -227,7 +245,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 @@ -241,11 +260,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -265,6 +286,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -276,17 +298,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index d049654a9..5f89f07e5 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.041680 # Nu sim_ticks 41680207000 # Number of ticks simulated final_tick 41680207000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118687 # Simulator instruction rate (inst/s) -host_op_rate 118687 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53827332 # Simulator tick rate (ticks/s) -host_mem_usage 260144 # Number of bytes of host memory used -host_seconds 774.33 # Real time elapsed on the host +host_inst_rate 93645 # Simulator instruction rate (inst/s) +host_op_rate 93645 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42470141 # Simulator tick rate (ticks/s) +host_mem_usage 279708 # Number of bytes of host memory used +host_seconds 981.40 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -203,14 +203,14 @@ system.physmem.bytesPerActivate::8064-8065 1 0.13% 99.73% # system.physmem.bytesPerActivate::8128-8129 1 0.13% 99.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 743 # Bytes accessed per row activation -system.physmem.totQLat 34068750 # Total ticks spent queuing -system.physmem.totMemAccLat 126422500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 34070750 # Total ticks spent queuing +system.physmem.totMemAccLat 126424500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 24690000 # Total ticks spent in databus transfers system.physmem.totBankLat 67663750 # Total ticks spent accessing banks -system.physmem.avgQLat 6899.30 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6899.71 # Average queueing delay per DRAM burst system.physmem.avgBankLat 13702.66 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25601.96 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25602.37 # Average memory access latency per DRAM burst system.physmem.avgRdBW 7.58 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 7.58 # Average system read bandwidth in MiByte/s @@ -239,9 +239,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 316032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 5776500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 5775000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 45976500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 45973500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.branchPred.lookups 13412627 # Number of BP lookups system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted @@ -310,9 +310,9 @@ system.cpu.contextSwitches 1 # Nu system.cpu.threadCycles 82971123 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 10519 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7752656 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75607759 # Number of cycles cpu stages are processed. -system.cpu.activity 90.699835 # Percentage of cycles cpu is active +system.cpu.idleCycles 7752655 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75607760 # Number of cycles cpu stages are processed. +system.cpu.activity 90.699836 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -342,9 +342,9 @@ system.cpu.stage2.utilization 59.802183 # Pe system.cpu.stage3.idleCycles 65333914 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed. system.cpu.stage3.utilization 21.624774 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29500659 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53859756 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.610710 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29500658 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53859757 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.610711 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 7635 # number of replacements system.cpu.icache.tags.tagsinuse 1492.182806 # Cycle average of tags in use system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks. @@ -366,12 +366,12 @@ system.cpu.icache.demand_misses::cpu.inst 11399 # n system.cpu.icache.demand_misses::total 11399 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11399 # number of overall misses system.cpu.icache.overall_misses::total 11399 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 325867750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 325867750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 325867750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 325867750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 325867750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 325867750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 325866750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 325866750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 325866750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 325866750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 325866750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 325866750 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 9956950 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 9956950 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 9956950 # number of demand (read+write) accesses @@ -384,12 +384,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28587.398017 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28587.398017 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28587.398017 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28587.398017 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28587.398017 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28587.398017 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28587.310290 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28587.310290 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28587.310290 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28587.310290 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28587.310290 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28587.310290 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -410,24 +410,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 9520 system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 266340500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 266340500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 266340500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 266340500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 266340500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 266340500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 266339500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 266339500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 266339500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 266339500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 266339500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 266339500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27976.943277 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27976.943277 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27976.943277 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27976.943277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27976.943277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27976.943277 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27976.838235 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27976.838235 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27976.838235 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27976.838235 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27976.838235 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27976.838235 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.throughput 18195687 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution @@ -486,17 +486,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 189283000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 189282000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32395250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 221678250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 122427250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 122427250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 189283000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 154822500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 344105500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 189283000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 154822500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 344105500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 221677250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 122425750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 122425750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 189282000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 154821000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 344103000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 189282000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 154821000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 344103000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses) @@ -521,17 +521,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67746.241947 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67745.884037 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76765.995261 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68929.804104 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71095.963995 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71095.963995 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67746.241947 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72211.986940 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69685.196436 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67746.241947 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72211.986940 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69685.196436 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68929.493159 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71095.092915 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71095.092915 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67745.884037 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72211.287313 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69684.690158 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67745.884037 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72211.287313 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69684.690158 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -554,14 +554,14 @@ system.cpu.l2cache.overall_mshr_misses::total 4938 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154136500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27132250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 181268750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101289250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101289250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101289750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101289750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 154136500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128421500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 282558000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128422000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 282558500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 154136500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128421500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 282558000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128422000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 282558500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses @@ -576,22 +576,22 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55166.964925 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64294.431280 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56364.661070 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58820.702671 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58820.702671 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58820.993031 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58820.993031 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59898.087687 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57221.142163 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59898.320896 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57221.243418 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59898.087687 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57221.142163 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59898.320896 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57221.243418 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1441.367779 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1441.367780 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26488450 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11915.632029 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1441.367779 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.367780 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.351896 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.351896 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 19995621 # number of ReadReq hits @@ -610,14 +610,14 @@ system.cpu.dcache.demand_misses::cpu.data 8851 # n system.cpu.dcache.demand_misses::total 8851 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 8851 # number of overall misses system.cpu.dcache.overall_misses::total 8851 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 41022750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 41022750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 492651500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 492651500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 533674250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 533674250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 533674250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 533674250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 41023250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 41023250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 492650500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 492650500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 533673750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 533673750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 533673750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 533673750 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -634,19 +634,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71096.620451 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71096.620451 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59542.119894 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59542.119894 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60295.362106 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60295.362106 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60295.362106 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60295.362106 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23885 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71097.487002 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71097.487002 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59541.999033 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59541.999033 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60295.305615 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60295.305615 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60295.305615 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60295.305615 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23884 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 841 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.400713 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.399524 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -670,12 +670,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 2223 system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33418750 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 33418750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124444750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 124444750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 157863500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 157863500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157863500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 157863500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124443250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 124443250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 157862000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 157862000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157862000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 157862000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -686,12 +686,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70355.263158 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70355.263158 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71192.648741 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71192.648741 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71013.720198 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71013.720198 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71013.720198 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71013.720198 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71191.790618 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71191.790618 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71013.045434 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71013.045434 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71013.045434 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71013.045434 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index b1f130dee..201e62f46 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,17 +518,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -482,6 +541,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -504,12 +564,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -528,7 +591,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 @@ -542,11 +606,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -566,6 +632,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -577,17 +644,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 1aa820757..445692444 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.023462 # Nu sim_ticks 23461709500 # Number of ticks simulated final_tick 23461709500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165875 # Simulator instruction rate (inst/s) -host_op_rate 165875 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46230980 # Simulator tick rate (ticks/s) -host_mem_usage 261164 # Number of bytes of host memory used -host_seconds 507.49 # Real time elapsed on the host +host_inst_rate 127245 # Simulator instruction rate (inst/s) +host_op_rate 127245 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35464472 # Simulator tick rate (ticks/s) +host_mem_usage 280732 # Number of bytes of host memory used +host_seconds 661.56 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory @@ -204,14 +204,14 @@ system.physmem.bytesPerActivate::8000-8001 1 0.13% 99.60% # system.physmem.bytesPerActivate::8128-8129 2 0.27% 99.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 750 # Bytes accessed per row activation -system.physmem.totQLat 37518250 # Total ticks spent queuing -system.physmem.totMemAccLat 134402000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 37518750 # Total ticks spent queuing +system.physmem.totMemAccLat 134402500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26140000 # Total ticks spent in databus transfers system.physmem.totBankLat 70743750 # Total ticks spent accessing banks -system.physmem.avgQLat 7176.41 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7176.50 # Average queueing delay per DRAM burst system.physmem.avgBankLat 13531.70 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25708.11 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25708.21 # Average memory access latency per DRAM burst system.physmem.avgRdBW 14.26 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 14.26 # Average system read bandwidth in MiByte/s @@ -240,17 +240,17 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 334592 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 334592 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6831000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 49013750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 49012250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu.branchPred.lookups 14847721 # Number of BP lookups system.cpu.branchPred.condPredicted 10774921 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 922205 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 8301784 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6957683 # Number of BTB hits +system.cpu.branchPred.BTBHits 6957680 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.809492 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 83.809456 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1467978 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3097 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits @@ -289,93 +289,93 @@ system.cpu.workload.num_syscalls 389 # Nu system.cpu.numCycles 46923420 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15463377 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 126961895 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 15463381 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 126961894 # Number of instructions fetch has processed system.cpu.fetch.Branches 14847721 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8425661 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22130057 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4473004 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5559399 # Number of cycles fetch has spent blocked +system.cpu.fetch.predictedBranches 8425658 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22130056 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4473003 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5559398 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 2205 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 14734161 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 324640 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46671602 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 324644 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46671603 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.720324 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.376096 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24541545 52.58% 52.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24541547 52.58% 52.58% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 2361252 5.06% 57.64% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 1192515 2.56% 60.20% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 1742111 3.73% 63.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2755702 5.90% 69.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2755701 5.90% 69.84% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 1149393 2.46% 72.30% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 1220691 2.62% 74.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 771783 1.65% 76.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10936610 23.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 771780 1.65% 76.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10936613 23.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46671602 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 46671603 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.316425 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.705726 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17289391 # Number of cycles decode is idle +system.cpu.fetch.rate 2.705725 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17289395 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 4257221 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20524695 # Number of cycles decode is running +system.cpu.decode.RunCycles 20524693 # Number of cycles decode is running system.cpu.decode.UnblockCycles 1095542 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3504753 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 3504752 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 2511898 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12165 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 123979131 # Number of instructions handled by decode +system.cpu.decode.BranchMispred 12167 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 123979126 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 31595 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3504753 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18431775 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 3504752 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18431780 # Number of cycles rename is idle system.cpu.rename.BlockCycles 963421 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 7928 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20455401 # Number of cycles rename is running +system.cpu.rename.RunCycles 20455398 # Number of cycles rename is running system.cpu.rename.UnblockCycles 3308324 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121154586 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 121154570 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 87 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 400162 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 2430153 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 88974234 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157440436 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 150394666 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 88974225 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 157440425 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 150394655 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 7045769 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20546873 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 20546864 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 749 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 744 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 8783261 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25363135 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8241350 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 25363133 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8241349 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 2569635 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 893782 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105438340 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 105438334 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 961 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96565073 # Number of instructions issued +system.cpu.iq.iqInstsIssued 96565072 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 178504 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20784584 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15622472 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 20784578 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15622466 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 572 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46671602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 46671603 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.069033 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.876517 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12133901 26.00% 26.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9340973 20.01% 46.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12133902 26.00% 26.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9340972 20.01% 46.01% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 8404137 18.01% 64.02% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 6285068 13.47% 77.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4921134 10.54% 88.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2853572 6.11% 94.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4921137 10.54% 88.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2853571 6.11% 94.14% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 1727806 3.70% 97.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 798698 1.71% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 798697 1.71% 99.56% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 206313 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46671602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46671603 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 187905 11.99% 11.99% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 11.99% # attempts to use FU when none available @@ -411,7 +411,7 @@ system.cpu.iq.fu_full::MemWrite 78699 5.02% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58732394 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58732393 60.82% 60.82% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 479878 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2798409 2.90% 64.22% # Type of FU issued @@ -444,36 +444,36 @@ system.cpu.iq.FU_type_0::MemRead 23829441 24.68% 92.59% # Ty system.cpu.iq.FU_type_0::MemWrite 7151262 7.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96565073 # Type of FU issued +system.cpu.iq.FU_type_0::total 96565072 # Type of FU issued system.cpu.iq.rate 2.057929 # Inst issue rate system.cpu.iq.fu_busy_cnt 1566710 # FU busy when requested system.cpu.iq.fu_busy_rate 0.016224 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226434514 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117518312 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_reads 226434513 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117518300 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 87069210 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 15112448 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 8740080 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 7062492 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90145383 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 90145382 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7986393 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 1518186 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5366937 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 5366935 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 18425 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 34629 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1740247 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 1740246 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 10551 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 2023 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3504753 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 3504752 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 133474 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 18356 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115674273 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 115674265 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 366324 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25363135 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8241350 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 25363133 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8241349 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 961 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2994 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 35 # Number of times the LSQ has become full, causing a stall @@ -483,41 +483,41 @@ system.cpu.iew.predictedNotTakenIncorrect 494157 # N system.cpu.iew.branchMispredicts 1029364 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 95337689 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 23310553 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1227384 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 1227383 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10234972 # number of nop insts executed +system.cpu.iew.exec_nop 10234970 # number of nop insts executed system.cpu.iew.exec_refs 30380075 # number of memory reference insts executed system.cpu.iew.exec_branches 12022158 # Number of branches executed system.cpu.iew.exec_stores 7069522 # Number of stores executed system.cpu.iew.exec_rate 2.031772 # Inst execution rate -system.cpu.iew.wb_sent 94652013 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent 94652012 # cumulative count of insts sent to commit system.cpu.iew.wb_count 94131702 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64474348 # num instructions producing a value -system.cpu.iew.wb_consumers 89850693 # num instructions consuming a value +system.cpu.iew.wb_producers 64474346 # num instructions producing a value +system.cpu.iew.wb_consumers 89850691 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.006071 # insts written-back per cycle system.cpu.iew.wb_fanout 0.717572 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23772324 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23772316 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 910471 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43166849 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 43166851 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.129019 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.746086 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16723467 38.74% 38.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9908467 22.95% 61.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16723468 38.74% 38.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9908468 22.95% 61.70% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 4486822 10.39% 72.09% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 2263317 5.24% 77.33% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 1605459 3.72% 81.05% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 1122723 2.60% 83.65% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 719573 1.67% 85.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 818064 1.90% 87.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5518957 12.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 818065 1.90% 87.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5518956 12.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43166849 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43166851 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -528,12 +528,12 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5518957 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5518956 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153322231 # The number of ROB reads -system.cpu.rob.rob_writes 234879486 # The number of ROB writes +system.cpu.rob.rob_reads 153322226 # The number of ROB reads +system.cpu.rob.rob_writes 234879469 # The number of ROB writes system.cpu.timesIdled 5401 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 251818 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 251817 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated @@ -542,7 +542,7 @@ system.cpu.cpi_total 0.557420 # CP system.cpu.ipc 1.793981 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.793981 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 129048096 # number of integer regfile reads -system.cpu.int_regfile_writes 70519804 # number of integer regfile writes +system.cpu.int_regfile_writes 70519803 # number of integer regfile writes system.cpu.fp_regfile_reads 6188545 # number of floating regfile reads system.cpu.fp_regfile_writes 6044303 # number of floating regfile writes system.cpu.misc_regfile_reads 714547 # number of misc regfile reads @@ -568,32 +568,32 @@ system.cpu.toL2Bus.respLayer0.utilization 0.1 # L system.cpu.toL2Bus.respLayer1.occupancy 3547000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.icache.tags.replacements 9576 # number of replacements -system.cpu.icache.tags.tagsinuse 1596.482982 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14719875 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1596.482984 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14719872 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11510 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1278.877063 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1278.876803 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1596.482982 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1596.482984 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.779533 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.779533 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14719875 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14719875 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14719875 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14719875 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14719875 # number of overall hits -system.cpu.icache.overall_hits::total 14719875 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14285 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14285 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14285 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14285 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14285 # number of overall misses -system.cpu.icache.overall_misses::total 14285 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 413142250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 413142250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 413142250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 413142250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 413142250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 413142250 # number of overall miss cycles +system.cpu.icache.ReadReq_hits::cpu.inst 14719872 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14719872 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14719872 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14719872 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14719872 # number of overall hits +system.cpu.icache.overall_hits::total 14719872 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14288 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14288 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14288 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14288 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14288 # number of overall misses +system.cpu.icache.overall_misses::total 14288 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 413271500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 413271500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 413271500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 413271500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 413271500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 413271500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 14734160 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 14734160 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 14734160 # number of demand (read+write) accesses @@ -606,12 +606,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000970 system.cpu.icache.demand_miss_rate::total 0.000970 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000970 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000970 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28921.403570 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28921.403570 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28921.403570 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28921.403570 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28921.403570 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28921.403570 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28924.377100 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28924.377100 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28924.377100 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28924.377100 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28924.377100 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28924.377100 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 548 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked @@ -620,45 +620,45 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 68.500000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2775 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2775 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2775 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2775 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2775 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2775 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2778 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2778 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2778 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2778 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2778 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2778 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11510 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 11510 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 11510 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 11510 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11510 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303669750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 303669750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303669750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 303669750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 303669750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 303669750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303668250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 303668250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303668250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 303668250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 303668250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 303668250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000781 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000781 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000781 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000781 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000781 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000781 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26383.123371 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26383.123371 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26383.123371 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26383.123371 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26383.123371 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26383.123371 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26382.993050 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26382.993050 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26382.993050 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26382.993050 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26382.993050 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26382.993050 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2409.583503 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2409.583505 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8517 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3590 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.372423 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 17.678720 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2010.447961 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2010.447963 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 381.456822 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061354 # Average percentage of cache occupancy @@ -688,17 +688,17 @@ system.cpu.l2cache.demand_misses::total 5228 # nu system.cpu.l2cache.overall_misses::cpu.inst 3062 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2166 # number of overall misses system.cpu.l2cache.overall_misses::total 5228 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 207669750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34561250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 242231000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 124309250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 124309250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 207669750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 158870500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 366540250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 207669750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 158870500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 366540250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 207668250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34560750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 242229000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 124310250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 124310250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 207668250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 158871000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 366539250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 207668250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 158871000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 366539250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 11510 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 516 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 12026 # number of ReadReq accesses(hits+misses) @@ -723,17 +723,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.380025 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.266030 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963952 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.380025 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67821.603527 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74970.173536 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68757.025263 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72908.651026 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72908.651026 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67821.603527 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73347.414589 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70110.988906 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67821.603527 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73347.414589 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70110.988906 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67821.113651 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74969.088937 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68756.457565 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72909.237537 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72909.237537 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67821.113651 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73347.645429 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70110.797628 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67821.113651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73347.645429 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70110.797628 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -753,17 +753,17 @@ system.cpu.l2cache.demand_mshr_misses::total 5228 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2166 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5228 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 168835250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 168834750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 28858250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 197693500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 103389750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 103389750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168835250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132248000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 301083250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168835250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132248000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 301083250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 197693000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 103390750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 103390750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168834750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132249000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 301083750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168834750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132249000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 301083750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266030 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.893411 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.292949 # mshr miss rate for ReadReq accesses @@ -775,25 +775,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.380025 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266030 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.380025 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55138.879817 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55138.716525 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62599.240781 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56115.100766 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60639.149560 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60639.149560 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55138.879817 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61056.325023 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57590.522188 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55138.879817 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61056.325023 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57590.522188 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56114.958842 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60639.736070 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60639.736070 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55138.716525 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61056.786704 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57590.617827 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55138.716525 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61056.786704 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57590.617827 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 159 # number of replacements -system.cpu.dcache.tags.tagsinuse 1459.152637 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1459.152638 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 28079168 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2247 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12496.291945 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1459.152637 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1459.152638 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.356238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.356238 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 21586035 # number of ReadReq hits @@ -816,16 +816,16 @@ system.cpu.dcache.demand_misses::cpu.data 9208 # n system.cpu.dcache.demand_misses::total 9208 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9208 # number of overall misses system.cpu.dcache.overall_misses::total 9208 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58289750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58289750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 505815795 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 505815795 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58289250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58289250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 505816795 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 505816795 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 564105545 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 564105545 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 564105545 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 564105545 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 564106045 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 564106045 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 564106045 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 564106045 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 21587009 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 21587009 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -846,16 +846,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59845.739220 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59845.739220 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61430.142701 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61430.142701 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59845.225873 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59845.225873 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61430.264149 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61430.264149 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61262.548328 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61262.548328 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61262.548328 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61262.548328 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61262.602628 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61262.602628 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61262.602628 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61262.602628 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 24052 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 336 # number of cycles access was blocked @@ -884,16 +884,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2246 system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35552500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 35552500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126440497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 126440497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35552000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 35552000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126441497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 126441497 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161992997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161992997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161992997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161992997 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161993497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 161993497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161993497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161993497 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses @@ -904,16 +904,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69033.980583 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69033.980583 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73044.770075 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73044.770075 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69033.009709 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69033.009709 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73045.347776 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73045.347776 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72125.109973 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72125.109973 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72125.109973 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72125.109973 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72125.332591 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72125.332591 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72125.332591 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72125.332591 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index d981a43f0..90382fb26 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,18 +173,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -202,16 +216,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -220,22 +237,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -244,22 +265,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -268,10 +293,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -280,124 +307,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -406,10 +454,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -418,16 +468,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -436,10 +489,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -450,6 +505,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -472,14 +528,17 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -498,12 +557,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -514,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -536,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -560,7 +625,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/twolf +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -574,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -598,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -609,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 4425c72f1..ac21abc99 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.074220 # Nu sim_ticks 74219948500 # Number of ticks simulated final_tick 74219948500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110839 # Simulator instruction rate (inst/s) -host_op_rate 121359 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47744278 # Simulator tick rate (ticks/s) -host_mem_usage 278976 # Number of bytes of host memory used -host_seconds 1554.53 # Real time elapsed on the host +host_inst_rate 84730 # Simulator instruction rate (inst/s) +host_op_rate 92772 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36497737 # Simulator tick rate (ticks/s) +host_mem_usage 298520 # Number of bytes of host memory used +host_seconds 2033.55 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 131072 # Number of bytes read from this memory @@ -197,14 +197,14 @@ system.physmem.bytesPerActivate::3712-3713 1 0.14% 99.72% # system.physmem.bytesPerActivate::6656-6657 1 0.14% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 1 0.14% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation -system.physmem.totQLat 25205500 # Total ticks spent queuing -system.physmem.totMemAccLat 100715500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 25203500 # Total ticks spent queuing +system.physmem.totMemAccLat 100713500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 18970000 # Total ticks spent in databus transfers system.physmem.totBankLat 56540000 # Total ticks spent accessing banks -system.physmem.avgQLat 6643.52 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6642.99 # Average queueing delay per DRAM burst system.physmem.avgBankLat 14902.48 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26545.99 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26545.47 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.27 # Average system read bandwidth in MiByte/s @@ -233,18 +233,18 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 242752 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 242752 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 4683500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4682500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35533250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35532750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 94784279 # Number of BP lookups -system.cpu.branchPred.condPredicted 74784012 # Number of conditional branches predicted +system.cpu.branchPred.lookups 94784274 # Number of BP lookups +system.cpu.branchPred.condPredicted 74784006 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 6281562 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44678427 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 44678423 # Number of BTB lookups system.cpu.branchPred.BTBHits 43050018 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.355268 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4356637 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 96.355276 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4356639 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 88400 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses @@ -292,95 +292,95 @@ system.cpu.workload.num_syscalls 400 # Nu system.cpu.numCycles 148439898 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39656913 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380179952 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94784279 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47406655 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80370667 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27283129 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7220970 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 39656921 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380179930 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94784274 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47406657 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80370665 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27283127 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7220968 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 6188 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36850892 # Number of cache lines fetched +system.cpu.fetch.CacheLines 36850894 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 1831983 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148240575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 148240577 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.801601 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.152871 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68038754 45.90% 45.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68038757 45.90% 45.90% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 5265463 3.55% 49.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10540667 7.11% 56.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10540668 7.11% 56.56% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 10285704 6.94% 63.50% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 8660470 5.84% 69.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6545128 4.42% 73.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6545129 4.42% 73.76% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 6246382 4.21% 77.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8002829 5.40% 83.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24655178 16.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8002830 5.40% 83.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24655174 16.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148240575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 148240577 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.638536 # Number of branch fetches per cycle system.cpu.fetch.rate 2.561171 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45513789 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5886753 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74804125 # Number of cycles decode is running +system.cpu.decode.IdleCycles 45513795 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5886752 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74804124 # Number of cycles decode is running system.cpu.decode.UnblockCycles 1203493 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20832415 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14327913 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 20832413 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14327914 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 164349 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392779898 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 392779880 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 733794 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20832415 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50900742 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 20832413 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50900748 # Number of cycles rename is idle system.cpu.rename.BlockCycles 730699 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 603190 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70558310 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4615219 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371308094 # Number of instructions processed by rename +system.cpu.rename.serializeStallCycles 603191 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70558309 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4615217 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371308082 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 339277 # Number of times rename has blocked due to IQ full +system.cpu.rename.IQFullEvents 339275 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 3661219 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 233 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631703486 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1581699955 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1506871299 # Number of integer rename lookups +system.cpu.rename.FullRegisterEvents 231 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 631703471 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1581699910 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1506871257 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3203425 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333659347 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 333659332 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 25072 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 25068 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 13010245 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43012685 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 43012682 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 16416405 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 5733542 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 3666500 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329190158 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 329190147 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 47154 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249456619 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 789371 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139503403 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 362002811 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 249456617 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 789368 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139503392 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 362002773 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1938 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148240575 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 148240577 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.682782 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.761427 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56059831 37.82% 37.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56059832 37.82% 37.82% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 22638796 15.27% 53.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24824163 16.75% 69.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24824164 16.75% 69.83% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 20343400 13.72% 83.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12534795 8.46% 92.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12534797 8.46% 92.01% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 6516114 4.40% 96.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4026097 2.72% 99.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4026095 2.72% 99.12% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 1116067 0.75% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 181312 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148240575 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148240577 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 965215 38.57% 38.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 5593 0.22% 38.79% # attempts to use FU when none available @@ -416,7 +416,7 @@ system.cpu.iq.fu_full::MemWrite 372730 14.89% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194899965 78.13% 78.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194899963 78.13% 78.13% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 979613 0.39% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued @@ -449,21 +449,21 @@ system.cpu.iq.FU_type_0::MemRead 38355278 15.38% 94.41% # Ty system.cpu.iq.FU_type_0::MemWrite 13948063 5.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249456619 # Type of FU issued +system.cpu.iq.FU_type_0::total 249456617 # Type of FU issued system.cpu.iq.rate 1.680523 # Inst issue rate system.cpu.iq.fu_busy_cnt 2502654 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010032 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646705831 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466563436 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_reads 646705826 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466563414 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 237885445 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 3740007 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2195697 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 1842613 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250082854 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 250082852 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 1876419 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 2013198 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13163201 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 13163198 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 11604 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 18881 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 3771771 # Number of stores squashed @@ -472,12 +472,12 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 18 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 107 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20832415 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 20832413 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 18550 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 893 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329254508 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 329254497 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 785294 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43012685 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 43012682 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 16416405 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 24746 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 188 # Number of times the IQ has become full, causing a stall @@ -488,7 +488,7 @@ system.cpu.iew.predictedNotTakenIncorrect 3760086 # N system.cpu.iew.branchMispredicts 7650044 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 242960519 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 36851938 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6496100 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 6496098 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 17196 # number of nop insts executed system.cpu.iew.exec_refs 50500394 # number of memory reference insts executed @@ -497,23 +497,23 @@ system.cpu.iew.exec_stores 13648456 # Nu system.cpu.iew.exec_rate 1.636760 # Inst execution rate system.cpu.iew.wb_sent 240785663 # cumulative count of insts sent to commit system.cpu.iew.wb_count 239728058 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148474079 # num instructions producing a value -system.cpu.iew.wb_consumers 267261472 # num instructions consuming a value +system.cpu.iew.wb_producers 148474078 # num instructions producing a value +system.cpu.iew.wb_consumers 267261470 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.614984 # insts written-back per cycle system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140583620 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 140583609 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 6128235 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127408160 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 127408164 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.480838 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.185451 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57701826 45.29% 45.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31696936 24.88% 70.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13777779 10.81% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7640619 6.00% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57701829 45.29% 45.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31696937 24.88% 70.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13777780 10.81% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7640618 6.00% 86.98% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 4387787 3.44% 90.42% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 1321958 1.04% 91.46% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 1703212 1.34% 92.80% # Number of insts commited each cycle @@ -522,7 +522,7 @@ system.cpu.commit.committed_per_cycle::8 7870029 6.18% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127408160 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 127408164 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -535,10 +535,10 @@ system.cpu.commit.int_insts 150106217 # Nu system.cpu.commit.function_calls 1848934 # Number of function calls committed. system.cpu.commit.bw_lim_events 7870029 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448787441 # The number of ROB reads -system.cpu.rob.rob_writes 679451137 # The number of ROB writes +system.cpu.rob.rob_reads 448787434 # The number of ROB reads +system.cpu.rob.rob_writes 679451113 # The number of ROB writes system.cpu.timesIdled 2805 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 199323 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 199321 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated @@ -574,49 +574,49 @@ system.cpu.toL2Bus.respLayer1.occupancy 3047739 # La system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.icache.tags.replacements 2394 # number of replacements system.cpu.icache.tags.tagsinuse 1347.740549 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 36845555 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 36845557 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4125 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8932.255758 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 8932.256242 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740549 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.658076 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.658076 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 36845555 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36845555 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36845555 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36845555 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36845555 # number of overall hits -system.cpu.icache.overall_hits::total 36845555 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 36845557 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36845557 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36845557 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36845557 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36845557 # number of overall hits +system.cpu.icache.overall_hits::total 36845557 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5337 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5337 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5337 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5337 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5337 # number of overall misses system.cpu.icache.overall_misses::total 5337 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 225944745 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 225944745 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 225944745 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 225944745 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 225944745 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 225944745 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36850892 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36850892 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36850892 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36850892 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36850892 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36850892 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 225938245 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 225938245 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 225938245 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 225938245 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 225938245 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 225938245 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36850894 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36850894 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36850894 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36850894 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36850894 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36850894 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42335.534008 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42335.534008 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42335.534008 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42335.534008 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42334.316095 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42334.316095 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42334.316095 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42334.316095 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1128 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked @@ -637,33 +637,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4126 system.cpu.icache.demand_mshr_misses::total 4126 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4126 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4126 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168091004 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 168091004 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168091004 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 168091004 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168091004 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 168091004 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168088504 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 168088504 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168088504 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 168088504 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168088504 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 168088504 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40739.458071 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40739.458071 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40739.458071 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40739.458071 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40739.458071 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40739.458071 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40738.852157 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40738.852157 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1967.449765 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 1967.449764 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2162 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2732 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.791362 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 4.994098 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569688 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569687 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 536.885979 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043505 # Average percentage of cache occupancy @@ -693,17 +693,17 @@ system.cpu.l2cache.demand_misses::total 3809 # nu system.cpu.l2cache.overall_misses::cpu.inst 2053 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses system.cpu.l2cache.overall_misses::total 3809 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143228000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51384000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 194612000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72291750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 72291750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 143228000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 123675750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 266903750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 143228000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 123675750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 266903750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143225500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51383000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 194608500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72292250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 72292250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 143225500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 123675250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 266900750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 143225500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 123675250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 266900750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4126 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 773 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4899 # number of ReadReq accesses(hits+misses) @@ -728,17 +728,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.637170 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.497576 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.948164 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.637170 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69765.221627 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75013.138686 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71078.159240 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.299720 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.299720 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69765.221627 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70430.381549 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70071.869257 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69765.221627 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70430.381549 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70071.869257 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69764.003897 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75011.678832 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71076.880935 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.766573 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.766573 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70071.081649 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70071.081649 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -767,17 +767,17 @@ system.cpu.l2cache.demand_mshr_misses::total 3794 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2049 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3794 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117254500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42298000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159552500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117253000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42297000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159550000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58841750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58841750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117254500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101139750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 218394250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117254500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101139750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 218394250 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117253000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101138750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 218391750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117253000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101138750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 218391750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871928 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.555828 # mshr miss rate for ReadReq accesses @@ -789,17 +789,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.634660 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.634660 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57225.231820 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62756.676558 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58594.381197 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57224.499756 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62755.192878 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58593.463092 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54940.943044 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54940.943044 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57225.231820 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.742120 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57563.060095 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57225.231820 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.742120 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57563.060095 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 57 # number of replacements system.cpu.dcache.tags.tagsinuse 1406.103135 # Cycle average of tags in use @@ -832,16 +832,16 @@ system.cpu.dcache.demand_misses::cpu.data 9625 # n system.cpu.dcache.demand_misses::total 9625 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9625 # number of overall misses system.cpu.dcache.overall_misses::total 9625 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 121870727 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 121870727 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623246 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 465623246 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 121862727 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 121862727 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623746 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 465623746 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 587493973 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 587493973 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 587493973 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 587493973 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 587486473 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 587486473 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 587486473 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 587486473 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 34386613 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 34386613 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) @@ -864,16 +864,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64075.040484 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64075.040484 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.463033 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.463033 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64070.834385 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64070.834385 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.527774 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.527774 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61038.334857 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61038.334857 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61037.555636 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61037.555636 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 314 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked @@ -902,14 +902,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1852 system.cpu.dcache.demand_mshr_misses::total 1852 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1852 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1852 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53114761 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 53114761 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73392998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 73392998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507759 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 126507759 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507759 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 126507759 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53113761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 53113761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73393498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 73393498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507259 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 126507259 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507259 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 126507259 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses @@ -918,14 +918,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68623.722222 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68623.722222 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68082.558442 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68082.558442 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68622.430233 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68622.430233 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68083.022263 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68083.022263 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 5e4a8f947..210f89c36 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -125,6 +131,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.branchPred] type=BranchPredictor @@ -133,6 +140,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -148,6 +156,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -170,18 +179,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[3] @@ -190,15 +202,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -207,16 +222,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -225,22 +243,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -249,22 +271,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -273,10 +299,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -285,124 +313,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -411,10 +460,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -423,16 +474,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -441,10 +495,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -455,6 +511,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -477,12 +534,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -493,16 +552,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[2] @@ -513,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -535,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -550,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -559,7 +625,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -573,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -597,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -608,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 003c2ae7a..3f8722e89 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.144463 # Nu sim_ticks 144463317000 # Number of ticks simulated final_tick 144463317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66822 # Simulator instruction rate (inst/s) -host_op_rate 111999 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73091533 # Simulator tick rate (ticks/s) -host_mem_usage 308580 # Number of bytes of host memory used -host_seconds 1976.47 # Real time elapsed on the host +host_inst_rate 55445 # Simulator instruction rate (inst/s) +host_op_rate 92931 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60647702 # Simulator tick rate (ticks/s) +host_mem_usage 328672 # Number of bytes of host memory used +host_seconds 2382.01 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 217088 # Number of bytes read from this memory @@ -207,14 +207,14 @@ system.physmem.bytesPerActivate::5312 1 0.10% 99.79% # By system.physmem.bytesPerActivate::5696 1 0.10% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::5952 1 0.10% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 957 # Bytes accessed per row activation -system.physmem.totQLat 28805000 # Total ticks spent queuing -system.physmem.totMemAccLat 137868750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 28783000 # Total ticks spent queuing +system.physmem.totMemAccLat 137846750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26770000 # Total ticks spent in databus transfers system.physmem.totBankLat 82293750 # Total ticks spent accessing banks -system.physmem.avgQLat 5380.09 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5375.98 # Average queueing delay per DRAM burst system.physmem.avgBankLat 15370.52 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25750.61 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25746.50 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s @@ -247,12 +247,12 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342656 system.membus.tot_pkt_size::total 342656 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 342656 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6948500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6950000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 50662837 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 18648234 # Number of BP lookups -system.cpu.branchPred.condPredicted 18648234 # Number of conditional branches predicted +system.cpu.branchPred.lookups 18648233 # Number of BP lookups +system.cpu.branchPred.condPredicted 18648233 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1490176 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 11407549 # Number of BTB lookups system.cpu.branchPred.BTBHits 10790529 # Number of BTB hits @@ -264,90 +264,90 @@ system.cpu.workload.num_syscalls 400 # Nu system.cpu.numCycles 289221873 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 23458037 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 206724223 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18648234 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 23458043 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 206724218 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18648233 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 12110896 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 54209099 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 15518775 # Number of cycles fetch has spent squashing +system.cpu.fetch.Cycles 54209097 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 15518774 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 178161359 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1571 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 9111 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22353213 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 224062 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269612466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 22353211 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 224061 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 269612469 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.268180 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.756310 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 216842558 80.43% 80.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 216842563 80.43% 80.43% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 2848142 1.06% 81.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2312056 0.86% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2312055 0.86% 82.34% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 2633842 0.98% 83.32% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 3218714 1.19% 84.51% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 3388946 1.26% 85.77% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 3831195 1.42% 87.19% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 2559437 0.95% 88.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31977576 11.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31977575 11.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269612466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 269612469 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.064477 # Number of branch fetches per cycle system.cpu.fetch.rate 0.714760 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36899349 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 167130008 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 41545231 # Number of cycles decode is running +system.cpu.decode.IdleCycles 36899359 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 167130004 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 41545229 # Number of cycles decode is running system.cpu.decode.UnblockCycles 10264627 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13773251 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336001478 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 13773251 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44972476 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116686700 # Number of cycles rename is blocking +system.cpu.decode.SquashCycles 13773250 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336001462 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 13773250 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44972487 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116686698 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 32545 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 42701692 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51445802 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 329633797 # Number of instructions processed by rename +system.cpu.rename.RunCycles 42701689 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51445800 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 329633775 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 10827 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 26123597 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22730551 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 382342114 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 917586762 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 605878307 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 22730549 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 382342090 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 917586713 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 605878272 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4127660 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 122912664 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 122912640 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 2051 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 2042 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 105140053 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 84507278 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.skidInsts 105140052 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 84507276 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 30107186 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 58355212 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 18979888 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322730912 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 322730905 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 260501997 # Number of instructions issued +system.cpu.iq.iqInstsIssued 260501994 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 116055 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 100987198 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 210203666 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 100987191 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 210203655 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269612466 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 269612469 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.966209 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.343680 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 143429906 53.20% 53.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55567349 20.61% 73.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34108146 12.65% 86.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19044984 7.06% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10887633 4.04% 97.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4152281 1.54% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1816698 0.67% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143429912 53.20% 53.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55567346 20.61% 73.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34108148 12.65% 86.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19044980 7.06% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10887634 4.04% 97.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4152283 1.54% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1816697 0.67% 99.78% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 472473 0.18% 99.95% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 132996 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269612466 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269612469 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 130605 4.82% 4.82% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.82% # attempts to use FU when none available @@ -383,7 +383,7 @@ system.cpu.iq.fu_full::MemWrite 302412 11.15% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1210810 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 162055945 62.21% 62.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 162055944 62.21% 62.67% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 789191 0.30% 62.98% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 7035649 2.70% 65.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 1445882 0.56% 66.23% # Type of FU issued @@ -412,26 +412,26 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 65414515 25.11% 91.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 65414513 25.11% 91.34% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 22550005 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 260501997 # Type of FU issued -system.cpu.iq.rate 0.900700 # Inst issue rate +system.cpu.iq.FU_type_0::total 260501994 # Type of FU issued +system.cpu.iq.rate 0.900699 # Inst issue rate system.cpu.iq.fu_busy_cnt 2712094 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010411 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 788557581 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 420384882 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 255147074 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 788557578 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 420384868 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 255147075 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4887028 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 3615221 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2349564 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 259544029 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 259544026 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2459252 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18903383 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 18903382 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27857691 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25993 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 27857689 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25992 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 283319 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 9591469 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address @@ -439,57 +439,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 49752 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13773251 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 85040641 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 13773250 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 85040639 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 5471570 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 322734981 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 322734974 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 133239 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 84507278 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 84507276 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 30107186 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 1979 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2708196 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 13910 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 283319 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 639398 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 901241 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1540639 # Number of branch mispredicts detected at execute +system.cpu.iew.predictedNotTakenIncorrect 901242 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1540640 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 258732431 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 64645019 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1769566 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 1769563 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_refs 86992194 # number of memory reference insts executed -system.cpu.iew.exec_branches 14265860 # Number of branches executed +system.cpu.iew.exec_branches 14265859 # Number of branches executed system.cpu.iew.exec_stores 22347175 # Number of stores executed system.cpu.iew.exec_rate 0.894581 # Inst execution rate -system.cpu.iew.wb_sent 258096694 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 257496638 # cumulative count of insts written-back +system.cpu.iew.wb_sent 258096693 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 257496639 # cumulative count of insts written-back system.cpu.iew.wb_producers 205928299 # num instructions producing a value -system.cpu.iew.wb_consumers 369130532 # num instructions consuming a value +system.cpu.iew.wb_consumers 369130530 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 0.890308 # insts written-back per cycle system.cpu.iew.wb_fanout 0.557874 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 101448847 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 101448840 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1491529 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255839215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 255839219 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.865244 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.654327 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156486613 61.17% 61.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 156486617 61.17% 61.17% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 57197635 22.36% 83.52% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 14067876 5.50% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12054069 4.71% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4176262 1.63% 95.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2944385 1.15% 96.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 904563 0.35% 96.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1049057 0.41% 97.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6958755 2.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12054068 4.71% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4176261 1.63% 95.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2944387 1.15% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 904564 0.35% 96.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1049058 0.41% 97.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6958753 2.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255839215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 255839219 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -500,12 +500,12 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. system.cpu.commit.function_calls 797818 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6958755 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6958753 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571692691 # The number of ROB reads -system.cpu.rob.rob_writes 659422929 # The number of ROB writes +system.cpu.rob.rob_reads 571692690 # The number of ROB reads +system.cpu.rob.rob_writes 659422914 # The number of ROB writes system.cpu.timesIdled 5933064 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19609407 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 19609404 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated @@ -513,13 +513,13 @@ system.cpu.cpi 2.189894 # CP system.cpu.cpi_total 2.189894 # CPI: Total CPI of All Threads system.cpu.ipc 0.456643 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.456643 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 451224157 # number of integer regfile reads +system.cpu.int_regfile_reads 451224153 # number of integer regfile reads system.cpu.int_regfile_writes 233957254 # number of integer regfile writes system.cpu.fp_regfile_reads 3215586 # number of floating regfile reads system.cpu.fp_regfile_writes 2009211 # number of floating regfile writes -system.cpu.cc_regfile_reads 102809518 # number of cc regfile reads -system.cpu.cc_regfile_writes 59799385 # number of cc regfile writes -system.cpu.misc_regfile_reads 133324418 # number of misc regfile reads +system.cpu.cc_regfile_reads 102809513 # number of cc regfile reads +system.cpu.cc_regfile_writes 59799383 # number of cc regfile writes +system.cpu.misc_regfile_reads 133324417 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes system.cpu.toL2Bus.throughput 3898568 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 7250 # Transaction distribution @@ -545,49 +545,49 @@ system.cpu.toL2Bus.respLayer1.occupancy 3467413 # La system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.icache.tags.replacements 4653 # number of replacements system.cpu.icache.tags.tagsinuse 1619.938452 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22344301 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 22344300 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6620 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3375.272054 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3375.271903 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1619.938452 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.790986 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.790986 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 22344301 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22344301 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22344301 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22344301 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22344301 # number of overall hits -system.cpu.icache.overall_hits::total 22344301 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8911 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8911 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8911 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8911 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8911 # number of overall misses -system.cpu.icache.overall_misses::total 8911 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 368225749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 368225749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 368225749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 368225749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 368225749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 368225749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22353212 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22353212 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22353212 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22353212 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22353212 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22353212 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22344300 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22344300 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22344300 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22344300 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22344300 # number of overall hits +system.cpu.icache.overall_hits::total 22344300 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8910 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8910 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8910 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8910 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8910 # number of overall misses +system.cpu.icache.overall_misses::total 8910 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 368144999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 368144999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 368144999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 368144999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 368144999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 368144999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22353210 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22353210 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22353210 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22353210 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22353210 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22353210 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41322.606778 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41322.606778 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41322.606778 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41322.606778 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41322.606778 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41322.606778 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41318.181706 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41318.181706 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41318.181706 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41318.181706 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 877 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked @@ -596,45 +596,45 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 43.850000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2127 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2127 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2127 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2127 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2127 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2127 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2126 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2126 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2126 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2126 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2126 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2126 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6784 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 6784 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 6784 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 6784 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 6784 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 6784 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 271661249 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 271661249 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 271661249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 271661249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271661249 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 271661249 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 271638749 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 271638749 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 271638749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 271638749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271638749 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 271638749 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000303 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000303 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.405808 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40044.405808 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40044.405808 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40044.405808 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40044.405808 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40044.405808 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40041.089180 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40041.089180 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2543.926921 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2543.926920 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3266 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3826 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.853633 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 1.725256 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2230.334816 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2230.334814 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 311.866849 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068064 # Average percentage of cache occupancy @@ -666,17 +666,17 @@ system.cpu.l2cache.demand_misses::total 5355 # nu system.cpu.l2cache.overall_misses::cpu.inst 3393 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1962 # number of overall misses system.cpu.l2cache.overall_misses::total 5355 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232439500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232417000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32755500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 265195000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 265172500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104434000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 104434000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 232439500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 232417000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 137189500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 369629000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 232439500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 369606500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 232417000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 137189500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 369629000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 369606500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6620 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 466 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7086 # number of ReadReq accesses(hits+misses) @@ -705,17 +705,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.620870 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.512538 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.978554 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.620870 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68505.599764 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68498.968464 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76175.581395 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69368.297149 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69362.411719 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68168.407311 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68168.407311 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68505.599764 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68498.968464 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69923.292559 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69025.023343 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68505.599764 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69020.821662 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68498.968464 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69923.292559 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69025.023343 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69020.821662 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -737,19 +737,19 @@ system.cpu.l2cache.demand_mshr_misses::total 5355 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3393 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1962 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5355 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 189922000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 189899500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27426500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 217348500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 217326000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1630163 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1630163 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 84874000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 84874000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189922000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189899500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 112300500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 302222500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189922000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 302200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189899500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 112300500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 302222500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 302200000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.922747 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.539515 # mshr miss rate for ReadReq accesses @@ -763,37 +763,37 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.620870 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.620870 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55974.653699 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55968.022399 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63782.558140 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56852.864243 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56846.978812 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55400.783290 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55400.783290 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 57 # number of replacements system.cpu.dcache.tags.tagsinuse 1438.861304 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 66102355 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 66102356 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2004 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32985.207086 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32985.207585 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 1438.861304 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.351284 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.351284 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 45588096 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45588096 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 45588097 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45588097 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514029 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 20514029 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66102125 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66102125 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66102125 # number of overall hits -system.cpu.dcache.overall_hits::total 66102125 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 66102126 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 66102126 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 66102126 # number of overall hits +system.cpu.dcache.overall_hits::total 66102126 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 935 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 935 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1702 # number of WriteReq misses @@ -810,14 +810,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 176670730 system.cpu.dcache.demand_miss_latency::total 176670730 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 176670730 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 176670730 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45589031 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45589031 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 45589032 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45589032 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66104762 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66104762 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66104762 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66104762 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 66104763 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66104763 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66104763 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66104763 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses |