diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-24 04:16:59 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-24 04:16:59 -0500 |
| commit | 28289e5995f80ce15fdf26a61e865b30cde48af7 (patch) | |
| tree | c674350be3f0cde557c720c44285eeeec6fb806a /tests/long | |
| parent | 7958f34797857fecf803fa4a2fcd018a8fffb640 (diff) | |
| download | gem5-28289e5995f80ce15fdf26a61e865b30cde48af7.tar.xz | |
stats: Update stats to reflect forwarding of InvalidateReq
Diffstat (limited to 'tests/long')
14 files changed, 20727 insertions, 20613 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index d1b3d40ca..83d2eea36 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,171 +1,171 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.461935 # Number of seconds simulated -sim_ticks 47461934895000 # Number of ticks simulated -final_tick 47461934895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.496138 # Number of seconds simulated +sim_ticks 47496138032000 # Number of ticks simulated +final_tick 47496138032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 231788 # Simulator instruction rate (inst/s) -host_op_rate 272612 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12136870284 # Simulator tick rate (ticks/s) -host_mem_usage 762440 # Number of bytes of host memory used -host_seconds 3910.56 # Real time elapsed on the host -sim_insts 906421729 # Number of instructions simulated -sim_ops 1066065309 # Number of ops (including micro ops) simulated +host_inst_rate 287392 # Simulator instruction rate (inst/s) +host_op_rate 338020 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15163142641 # Simulator tick rate (ticks/s) +host_mem_usage 759192 # Number of bytes of host memory used +host_seconds 3132.34 # Real time elapsed on the host +sim_insts 900209792 # Number of instructions simulated +sim_ops 1058792792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 128960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 112832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 8192640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 40731208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 14846528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 153920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 132096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3008640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 17045264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 15179584 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 435648 # Number of bytes read from this memory -system.physmem.bytes_read::total 99967320 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 8192640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3008640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11201280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 79350912 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 123968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 99904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 7981184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 13323912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 15275072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 135168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 122048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3081152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 10821968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 12736320 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 446656 # Number of bytes read from this memory +system.physmem.bytes_read::total 64147352 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 7981184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3081152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11062336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 76613760 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 79371496 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2015 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1763 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 128010 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 636438 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 231977 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2405 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 47010 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 266345 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 237181 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6807 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1562015 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1239858 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 76634344 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1937 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1561 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 124706 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 208199 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 238673 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2112 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1907 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 48143 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 169106 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 199005 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6979 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1002328 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1197090 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1242432 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2377 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 172615 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 858187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 312809 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3243 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 63391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 359135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 319826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2106263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 172615 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 63391 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 236006 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1671885 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1199664 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 168039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 280526 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 321607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2846 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2570 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 64872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 227849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 268155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1350580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 168039 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 64872 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 232910 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1613052 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1672319 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1671885 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2377 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 172615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 858620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 312809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3243 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 63391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 359136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 319826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3778582 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1562015 # Number of read requests accepted -system.physmem.writeReqs 1242432 # Number of write requests accepted -system.physmem.readBursts 1562015 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1242432 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 99934848 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 34112 # Total number of bytes read from write queue -system.physmem.bytesWritten 79370432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 99967320 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 79371496 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 533 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1613486 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1613052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 168039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 280960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 321607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 64872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 227850 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 268155 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2964066 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1002328 # Number of read requests accepted +system.physmem.writeReqs 1199664 # Number of write requests accepted +system.physmem.readBursts 1002328 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1199664 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 64118976 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 30016 # Total number of bytes read from write queue +system.physmem.bytesWritten 76632896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 64147352 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 76634344 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 469 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 93757 # Per bank write bursts -system.physmem.perBankRdBursts::1 100629 # Per bank write bursts -system.physmem.perBankRdBursts::2 93977 # Per bank write bursts -system.physmem.perBankRdBursts::3 99615 # Per bank write bursts -system.physmem.perBankRdBursts::4 97211 # Per bank write bursts -system.physmem.perBankRdBursts::5 108899 # Per bank write bursts -system.physmem.perBankRdBursts::6 95410 # Per bank write bursts -system.physmem.perBankRdBursts::7 95079 # Per bank write bursts -system.physmem.perBankRdBursts::8 84413 # Per bank write bursts -system.physmem.perBankRdBursts::9 140545 # Per bank write bursts -system.physmem.perBankRdBursts::10 87149 # Per bank write bursts -system.physmem.perBankRdBursts::11 92128 # Per bank write bursts -system.physmem.perBankRdBursts::12 89605 # Per bank write bursts -system.physmem.perBankRdBursts::13 97795 # Per bank write bursts -system.physmem.perBankRdBursts::14 91413 # Per bank write bursts -system.physmem.perBankRdBursts::15 93857 # Per bank write bursts -system.physmem.perBankWrBursts::0 74634 # Per bank write bursts -system.physmem.perBankWrBursts::1 80843 # Per bank write bursts -system.physmem.perBankWrBursts::2 76779 # Per bank write bursts -system.physmem.perBankWrBursts::3 81501 # Per bank write bursts -system.physmem.perBankWrBursts::4 79021 # Per bank write bursts -system.physmem.perBankWrBursts::5 86869 # Per bank write bursts -system.physmem.perBankWrBursts::6 77167 # Per bank write bursts -system.physmem.perBankWrBursts::7 78926 # Per bank write bursts -system.physmem.perBankWrBursts::8 71646 # Per bank write bursts -system.physmem.perBankWrBursts::9 75252 # Per bank write bursts -system.physmem.perBankWrBursts::10 73334 # Per bank write bursts -system.physmem.perBankWrBursts::11 76259 # Per bank write bursts -system.physmem.perBankWrBursts::12 74746 # Per bank write bursts -system.physmem.perBankWrBursts::13 79667 # Per bank write bursts -system.physmem.perBankWrBursts::14 75302 # Per bank write bursts -system.physmem.perBankWrBursts::15 78217 # Per bank write bursts +system.physmem.perBankRdBursts::0 52312 # Per bank write bursts +system.physmem.perBankRdBursts::1 66235 # Per bank write bursts +system.physmem.perBankRdBursts::2 59334 # Per bank write bursts +system.physmem.perBankRdBursts::3 65978 # Per bank write bursts +system.physmem.perBankRdBursts::4 61446 # Per bank write bursts +system.physmem.perBankRdBursts::5 69476 # Per bank write bursts +system.physmem.perBankRdBursts::6 59128 # Per bank write bursts +system.physmem.perBankRdBursts::7 60480 # Per bank write bursts +system.physmem.perBankRdBursts::8 57677 # Per bank write bursts +system.physmem.perBankRdBursts::9 110303 # Per bank write bursts +system.physmem.perBankRdBursts::10 51521 # Per bank write bursts +system.physmem.perBankRdBursts::11 60498 # Per bank write bursts +system.physmem.perBankRdBursts::12 54125 # Per bank write bursts +system.physmem.perBankRdBursts::13 57278 # Per bank write bursts +system.physmem.perBankRdBursts::14 58648 # Per bank write bursts +system.physmem.perBankRdBursts::15 57420 # Per bank write bursts +system.physmem.perBankWrBursts::0 71344 # Per bank write bursts +system.physmem.perBankWrBursts::1 78863 # Per bank write bursts +system.physmem.perBankWrBursts::2 73221 # Per bank write bursts +system.physmem.perBankWrBursts::3 79189 # Per bank write bursts +system.physmem.perBankWrBursts::4 75543 # Per bank write bursts +system.physmem.perBankWrBursts::5 82829 # Per bank write bursts +system.physmem.perBankWrBursts::6 74512 # Per bank write bursts +system.physmem.perBankWrBursts::7 77237 # Per bank write bursts +system.physmem.perBankWrBursts::8 71961 # Per bank write bursts +system.physmem.perBankWrBursts::9 73593 # Per bank write bursts +system.physmem.perBankWrBursts::10 69363 # Per bank write bursts +system.physmem.perBankWrBursts::11 76682 # Per bank write bursts +system.physmem.perBankWrBursts::12 71227 # Per bank write bursts +system.physmem.perBankWrBursts::13 74509 # Per bank write bursts +system.physmem.perBankWrBursts::14 73049 # Per bank write bursts +system.physmem.perBankWrBursts::15 74267 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 64 # Number of times write queue was full causing retry -system.physmem.totGap 47461932782500 # Total gap between requests +system.physmem.numWrRetry 57 # Number of times write queue was full causing retry +system.physmem.totGap 47496135919500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1561985 # Read request sizes (log2) +system.physmem.readPktSize::6 1002298 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1239858 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 973357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 368872 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 48939 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 35383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 30040 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 27781 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 24940 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 22435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 19175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 910 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 290 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1197090 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 675393 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 118123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 43619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 29137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 27086 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 24475 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 22026 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1664 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 985 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 727 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 286 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see @@ -188,169 +188,168 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 20126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 23872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 45415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 64128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 66477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 70043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 73662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 76578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 77244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 79843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 84567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 82434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 83310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 91239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 81410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 76067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 73611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 150 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 991222 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 180.892514 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 111.543893 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 240.536828 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 614355 61.98% 61.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 184510 18.61% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 61267 6.18% 86.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 32396 3.27% 90.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 21556 2.17% 92.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13955 1.41% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9658 0.97% 94.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9476 0.96% 95.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 44049 4.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 991222 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 69967 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.317164 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 326.421262 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 69964 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::81920-86015 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 69967 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 69967 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.724970 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.179434 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.169336 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 65865 94.14% 94.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 2036 2.91% 97.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 254 0.36% 97.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 187 0.27% 97.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 141 0.20% 97.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 122 0.17% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 214 0.31% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 78 0.11% 98.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 271 0.39% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 64 0.09% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 34 0.05% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 49 0.07% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 243 0.35% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 32 0.05% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 40 0.06% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 104 0.15% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 171 0.24% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 14 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::15 31163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 38080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 51935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 55190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 60170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 65836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 70016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 72724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 73495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 74816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 77871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 75261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 76182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 84001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 74766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 69103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 66691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 167 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 993836 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 141.624332 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 96.550200 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 190.035765 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 676204 68.04% 68.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 192250 19.34% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44807 4.51% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21137 2.13% 94.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15251 1.53% 95.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9933 1.00% 96.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5714 0.57% 97.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4523 0.46% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24017 2.42% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 993836 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 62276 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.086984 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 158.174793 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 62273 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 62276 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 62276 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.227134 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.463029 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.016188 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 49891 80.11% 80.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 5512 8.85% 88.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 3034 4.87% 93.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1650 2.65% 96.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 463 0.74% 97.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 302 0.48% 97.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 265 0.43% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 82 0.13% 98.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 283 0.45% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 77 0.12% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 32 0.05% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 49 0.08% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 248 0.40% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 39 0.06% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 31 0.05% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 106 0.17% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 143 0.23% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 4 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 5 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 12 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 11 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 69967 # Writes before turning the bus around for reads -system.physmem.totQLat 43176438588 # Total ticks spent queuing -system.physmem.totMemAccLat 72454226088 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 7807410000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27650.94 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 62276 # Writes before turning the bus around for reads +system.physmem.totQLat 32552700191 # Total ticks spent queuing +system.physmem.totMemAccLat 51337556441 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5009295000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32492.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46400.94 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.67 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.11 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.67 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 51242.30 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.35 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.61 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.35 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.61 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.42 # Average write queue length when enqueuing -system.physmem.readRowHits 1247973 # Number of row buffer hits during reads -system.physmem.writeRowHits 562447 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.92 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 45.35 # Row buffer hit rate for writes -system.physmem.avgGap 16923811.64 # Average gap between requests -system.physmem.pageHitRate 64.62 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3897081720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2126383875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6119692800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4119595200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3099982404480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1216381568355 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27410155454250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31742782180680 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.805156 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45598728268843 # Time in different power states -system.physmem_0.memoryStateTime::REF 1584858080000 # Time in different power states +system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.36 # Average write queue length when enqueuing +system.physmem.readRowHits 748874 # Number of row buffer hits during reads +system.physmem.writeRowHits 456536 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.75 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.13 # Row buffer hit rate for writes +system.physmem.avgGap 21569622.38 # Average gap between requests +system.physmem.pageHitRate 54.81 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3877765920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2115844500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3856171800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3970542240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3102216508560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1199773763640 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27445246701750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31761057298410 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.708277 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45657180846254 # Time in different power states +system.physmem_0.memoryStateTime::REF 1586000260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 278346651157 # Time in different power states +system.physmem_0.memoryStateTime::ACT 252951953746 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3596556600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1962406875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6059788800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3916661040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3099982404480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1207691479170 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27417778331250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31740987628215 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.767346 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45611421903472 # Time in different power states -system.physmem_1.memoryStateTime::REF 1584858080000 # Time in different power states +system.physmem_1.actEnergy 3635634240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1983729000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3958266000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3788538480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3102216508560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1194664304160 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27449728675500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31759975655940 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.685504 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45664625089280 # Time in different power states +system.physmem_1.memoryStateTime::REF 1586000260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 265649419028 # Time in different power states +system.physmem_1.memoryStateTime::ACT 245507696970 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -384,15 +383,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1674 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 141158417 # Number of BP lookups -system.cpu0.branchPred.condPredicted 100207840 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6289341 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 105574499 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 76948344 # Number of BTB hits +system.cpu0.branchPred.lookups 138061860 # Number of BP lookups +system.cpu0.branchPred.condPredicted 98120507 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6229967 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 103103324 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 75422199 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.885351 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 16552897 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1094870 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 73.152054 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 16055942 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1103312 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -423,63 +422,62 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 283140 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 283140 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9717 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79661 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 283140 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 283140 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 283140 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 89378 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 23531.797534 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21398.159545 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 20518.573843 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 88174 98.65% 98.65% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 214 0.24% 98.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 839 0.94% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 33 0.04% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 38 0.04% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 25 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 35 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 287097 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 287097 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9253 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79328 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 287097 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 287097 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 287097 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 88581 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23354.082704 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21377.049680 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 19303.806083 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 87487 98.76% 98.76% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 212 0.24% 99.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 756 0.85% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 30 0.03% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 31 0.03% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 29 0.03% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 89378 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 88581 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 79661 89.13% 89.13% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 9717 10.87% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 89378 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 283140 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 79328 89.55% 89.55% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 9253 10.45% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 88581 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 287097 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 283140 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 89378 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 287097 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 88581 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 89378 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 372518 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 88581 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 375678 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 90921588 # DTB read hits -system.cpu0.dtb.read_misses 233548 # DTB read misses -system.cpu0.dtb.write_hits 80603054 # DTB write hits -system.cpu0.dtb.write_misses 49592 # DTB write misses +system.cpu0.dtb.read_hits 87655759 # DTB read hits +system.cpu0.dtb.read_misses 237615 # DTB read misses +system.cpu0.dtb.write_hits 78096829 # DTB write hits +system.cpu0.dtb.write_misses 49482 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 38267 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2134 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9015 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 42183 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 36184 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2196 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9698 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 11497 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 91155136 # DTB read accesses -system.cpu0.dtb.write_accesses 80652646 # DTB write accesses +system.cpu0.dtb.perms_faults 11726 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 87893374 # DTB read accesses +system.cpu0.dtb.write_accesses 78146311 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 171524642 # DTB hits -system.cpu0.dtb.misses 283140 # DTB misses -system.cpu0.dtb.accesses 171807782 # DTB accesses +system.cpu0.dtb.hits 165752588 # DTB hits +system.cpu0.dtb.misses 287097 # DTB misses +system.cpu0.dtb.accesses 166039685 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -509,187 +507,187 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 66290 # Table walker walks requested -system.cpu0.itb.walker.walksLong 66290 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 665 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 56612 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 66290 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 66290 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 66290 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 57277 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 26707.997975 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23913.035188 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 23204.196076 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 56118 97.98% 97.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 13 0.02% 98.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 1037 1.81% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 26 0.05% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 46 0.08% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 23 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 11 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 66101 # Table walker walks requested +system.cpu0.itb.walker.walksLong 66101 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 650 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 56681 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 66101 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 66101 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 66101 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 57331 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26460.544906 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23886.492389 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 21943.926110 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 56305 98.21% 98.21% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 11 0.02% 98.23% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 903 1.58% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 44 0.08% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 42 0.07% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 57277 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 57331 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 56612 98.84% 98.84% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 665 1.16% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 57277 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 56681 98.87% 98.87% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 650 1.13% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 57331 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66290 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66290 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66101 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66101 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57277 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57277 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 123567 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 252665762 # ITB inst hits -system.cpu0.itb.inst_misses 66290 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57331 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57331 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 123432 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 246672238 # ITB inst hits +system.cpu0.itb.inst_misses 66101 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 27416 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 42183 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 25870 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 203450 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 211969 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 252732052 # ITB inst accesses -system.cpu0.itb.hits 252665762 # DTB hits -system.cpu0.itb.misses 66290 # DTB misses -system.cpu0.itb.accesses 252732052 # DTB accesses -system.cpu0.numCycles 1081051562 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 246738339 # ITB inst accesses +system.cpu0.itb.hits 246672238 # DTB hits +system.cpu0.itb.misses 66101 # DTB misses +system.cpu0.itb.accesses 246738339 # DTB accesses +system.cpu0.numCycles 1042581150 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 468741146 # Number of instructions committed -system.cpu0.committedOps 550955855 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 47157402 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 5078 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93843643871 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.306287 # CPI: cycles per instruction -system.cpu0.ipc 0.433597 # IPC: instructions per cycle +system.cpu0.committedInsts 455270721 # Number of instructions committed +system.cpu0.committedOps 534899361 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 47095692 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4288 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93950410811 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.290025 # CPI: cycles per instruction +system.cpu0.ipc 0.436677 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5324 # number of quiesce instructions executed -system.cpu0.tickCycles 755067683 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 325983879 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5850262 # number of replacements -system.cpu0.dcache.tags.tagsinuse 501.214442 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 162710873 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5850774 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.810145 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 13221 # number of quiesce instructions executed +system.cpu0.tickCycles 736979138 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 305602012 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5679788 # number of replacements +system.cpu0.dcache.tags.tagsinuse 503.382728 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 157129733 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5680300 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.662224 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.214442 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978934 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.978934 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.382728 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983169 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.983169 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 332 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 439 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 346062459 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 346062459 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 83268986 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 83268986 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 74755135 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 74755135 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 273368 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 273368 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 183787 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 183787 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1841830 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1841830 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1806426 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1806426 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 158024121 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 158024121 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 158297489 # number of overall hits -system.cpu0.dcache.overall_hits::total 158297489 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3569470 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3569470 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2481271 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2481271 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 690957 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 690957 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 806074 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 806074 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173924 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 173924 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 207838 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 207838 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 6050741 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 6050741 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6741698 # number of overall misses -system.cpu0.dcache.overall_misses::total 6741698 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 62945089000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 62945089000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 62898003000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 62898003000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 71296883500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 71296883500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2825966000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2825966000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5775275000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5775275000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4714000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4714000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 125843092000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 125843092000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 125843092000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 125843092000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 86838456 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 86838456 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 77236406 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 77236406 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 964325 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 964325 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 989861 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 989861 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2015754 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2015754 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2014264 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2014264 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 164074862 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 164074862 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 165039187 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 165039187 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041105 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.041105 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032126 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.032126 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.716519 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.716519 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.814330 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.814330 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086282 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086282 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.103183 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.103183 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036878 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.036878 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040849 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.040849 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17634.295568 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 17634.295568 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25349.106567 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 25349.106567 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 88449.551158 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 88449.551158 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16248.280858 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16248.280858 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27787.387292 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27787.387292 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 334387337 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 334387337 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 80268736 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 80268736 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72233903 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 72233903 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 277349 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 277349 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 251788 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 251788 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1785654 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1785654 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1744754 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1744754 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 152502639 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 152502639 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 152779988 # number of overall hits +system.cpu0.dcache.overall_hits::total 152779988 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3412741 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3412741 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2489296 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2489296 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 686937 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 686937 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 801634 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 801634 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 154902 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 154902 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194385 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 194385 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5902037 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5902037 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 6588974 # number of overall misses +system.cpu0.dcache.overall_misses::total 6588974 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 58848858500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 58848858500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 63605542500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 63605542500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 48599001500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 48599001500 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2502004000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2502004000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5451875000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 5451875000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 6380500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 6380500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 122454401000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 122454401000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 122454401000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 122454401000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 83681477 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 83681477 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74723199 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 74723199 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 964286 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 964286 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1053422 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1053422 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1940556 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1940556 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1939139 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1939139 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 158404676 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 158404676 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 159368962 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 159368962 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040783 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.040783 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033314 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.033314 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.712379 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.712379 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760981 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760981 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079824 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079824 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100243 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100243 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037259 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.037259 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041344 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.041344 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17243.868931 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 17243.868931 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25551.618811 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 25551.618811 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 60624.925465 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 60624.925465 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16152.173632 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16152.173632 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28046.788590 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28046.788590 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20797.963754 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 20797.963754 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18666.379301 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18666.379301 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20747.819948 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20747.819948 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18584.744909 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18584.744909 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -698,161 +696,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 5850286 # number of writebacks -system.cpu0.dcache.writebacks::total 5850286 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 444097 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 444097 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1026850 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1026850 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 104 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 104 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44524 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44524 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 32 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 32 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1470947 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1470947 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1470947 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1470947 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3125373 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3125373 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1454421 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1454421 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 689314 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 689314 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 805970 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 805970 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 129400 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 129400 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 207806 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 207806 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4579794 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4579794 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5269108 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5269108 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 19530 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 19530 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 21048 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 21048 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 40578 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 40578 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 49230560000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 49230560000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 36276054500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 36276054500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18434925500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18434925500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 70481228500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 70481228500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1893845500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1893845500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5565229000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5565229000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4561000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4561000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 85506614500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 85506614500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103941540000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 103941540000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3800939500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3800939500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3971667500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3971667500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7772607000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7772607000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035991 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035991 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018831 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018831 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.714815 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.714815 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.814225 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.814225 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064194 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064194 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.103167 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.103167 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027913 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027913 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031926 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031926 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15751.899053 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15751.899053 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24941.921562 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24941.921562 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26743.872169 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26743.872169 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 87448.947852 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 87448.947852 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14635.591190 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14635.591190 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26780.886981 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26780.886981 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5679821 # number of writebacks +system.cpu0.dcache.writebacks::total 5679821 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 423726 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 423726 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1038452 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1038452 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 85 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 85 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41327 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41327 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 43 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 43 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1462178 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1462178 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1462178 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1462178 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2989015 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2989015 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1450844 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1450844 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 685285 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 685285 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 801549 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 801549 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 113575 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 113575 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194342 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 194342 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4439859 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4439859 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5125144 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5125144 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32143 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32143 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31553 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31553 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 63696 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 63696 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 46000579500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 46000579500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 36719986000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 36719986000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17989395000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17989395000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 47789065000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 47789065000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1631247500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1631247500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5254690500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5254690500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 6005000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 6005000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 82720565500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 82720565500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 100709960500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 100709960500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6124425500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6124425500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5931269500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5931269500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12055695000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12055695000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035719 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035719 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019416 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019416 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.710666 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.710666 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.760900 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.760900 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058527 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058527 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.100221 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.100221 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028029 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028029 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032159 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032159 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15389.879107 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15389.879107 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25309.396462 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25309.396462 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26250.968575 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26250.968575 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 59620.890301 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 59620.890301 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14362.733876 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14362.733876 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27038.367929 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.367929 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18670.406245 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18670.406245 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19726.591294 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19726.591294 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194620.558116 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194620.558116 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 188695.719308 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188695.719308 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 191547.316280 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191547.316280 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18631.349667 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18631.349667 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19650.171878 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19650.171878 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190536.835392 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190536.835392 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187977.989415 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187977.989415 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189269.263376 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 189269.263376 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 9594128 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.890921 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 242861120 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 9594640 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 25.312166 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 40343615000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890921 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999787 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999787 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 9549530 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.897064 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 236903550 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 9550042 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 24.806545 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 33055106000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.897064 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999799 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999799 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 247 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 514506190 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 514506190 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 242861120 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 242861120 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 242861120 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 242861120 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 242861120 # number of overall hits -system.cpu0.icache.overall_hits::total 242861120 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9594650 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9594650 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9594650 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9594650 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9594650 # number of overall misses -system.cpu0.icache.overall_misses::total 9594650 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 102613134000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 102613134000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 102613134000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 102613134000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 102613134000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 102613134000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 252455770 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 252455770 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 252455770 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 252455770 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 252455770 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 252455770 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038005 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.038005 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038005 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.038005 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038005 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.038005 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10694.828264 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10694.828264 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10694.828264 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10694.828264 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10694.828264 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10694.828264 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 502457255 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 502457255 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 236903550 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 236903550 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 236903550 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 236903550 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 236903550 # number of overall hits +system.cpu0.icache.overall_hits::total 236903550 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9550052 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9550052 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9550052 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9550052 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9550052 # number of overall misses +system.cpu0.icache.overall_misses::total 9550052 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 101421985500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 101421985500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 101421985500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 101421985500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 101421985500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 101421985500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 246453602 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 246453602 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 246453602 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 246453602 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 246453602 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 246453602 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038750 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.038750 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038750 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.038750 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038750 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.038750 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10620.045367 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10620.045367 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10620.045367 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10620.045367 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10620.045367 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10620.045367 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -861,257 +859,260 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 9594128 # number of writebacks -system.cpu0.icache.writebacks::total 9594128 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9594650 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 9594650 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 9594650 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 9594650 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 9594650 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 9594650 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 9549530 # number of writebacks +system.cpu0.icache.writebacks::total 9549530 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9550052 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 9550052 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 9550052 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 9550052 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 9550052 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 9550052 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 97815809000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 97815809000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 97815809000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 97815809000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 97815809000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 97815809000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 96646960000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 96646960000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 96646960000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 96646960000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 96646960000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 96646960000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7414627000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7414627000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038005 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038005 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038005 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.038005 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038005 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.038005 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10194.828264 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10194.828264 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10194.828264 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10194.828264 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10194.828264 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10194.828264 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038750 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038750 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038750 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.038750 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038750 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.038750 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10120.045420 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10120.045420 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10120.045420 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10120.045420 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10120.045420 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10120.045420 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8065650 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8066797 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 1004 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7772165 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7773534 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 1208 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1049003 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2949800 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16165.081558 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 23810069 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2965603 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 8.028745 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 9049945000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15191.178363 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 63.510017 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 64.560721 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 845.832457 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.927196 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003876 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003940 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.051626 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.986638 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1186 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14549 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 43 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 162 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 909 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 72 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 45 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 19 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # 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Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 60.779936 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 54.474522 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 783.950672 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.932816 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003710 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003325 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.047849 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.987700 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1265 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 55 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14897 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 23 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 535 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 649 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 58 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 45 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1135 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5291 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7937 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 458 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.077209 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.909241 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 513878817 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 513878817 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 534301 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 171000 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 705301 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 3781367 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 3781367 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 11445215 # 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number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 171000 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 8796749 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3657940 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 13159990 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 534301 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 171000 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 8796749 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3657940 # number of overall hits +system.cpu0.l2cache.overall_hits::total 13159990 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12394 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8896 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 21290 # 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mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11561613000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 18557768000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022671 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049440 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.029298 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses +system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses +system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998145 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998145 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998376 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998376 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.239883 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.239883 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.080799 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.080799 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270086 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270086 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.755217 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.755217 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.023171 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049164 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080799 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.263055 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.139040 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.023171 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049164 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080799 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.263055 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.241743 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.241743 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.078878 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.078878 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270773 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270773 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.745871 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.745871 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022671 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049440 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.078878 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.263805 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.136913 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022671 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049440 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078878 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.263805 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.191643 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 38403.644793 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 42771.255519 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 40211.136619 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55167.381577 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55167.381577 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29321.577271 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29321.577271 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19259.373331 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19259.373331 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 460833.111111 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 460833.111111 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55367.435521 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55367.435521 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32928.322934 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32928.322934 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35777.482886 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35777.482886 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 105717.827108 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 105717.827108 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 38403.644793 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 42771.255519 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32928.322934 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39935.975810 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37410.526173 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 38403.644793 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 42771.255519 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32928.322934 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39935.975810 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55167.381577 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42284.528463 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.189379 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 37816.241730 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 39677.704070 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38593.949643 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59689.287295 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59689.287295 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29753.284535 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29753.284535 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19514.559909 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19514.559909 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 782714.142857 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 782714.142857 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55350.794047 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55350.794047 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32787.400786 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32787.400786 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 34527.480263 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34527.480263 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69680.907566 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69680.907566 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 37816.241730 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 39677.704070 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32787.400786 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39107.955826 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36823.924881 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 37816.241730 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 39677.704070 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32787.400786 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39107.955826 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59689.287295 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43158.674848 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186612.391193 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148118.640293 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181193.272520 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181193.272520 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182530.348754 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152314.071899 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 180475.390613 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 180475.390613 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183801.468776 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 155613.282806 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181512.386963 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 159973.863196 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 31782914 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16244108 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2495 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 2292721 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2292254 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 467 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 871142 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 14502039 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 21048 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 21048 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5574338 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 11577498 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 3160606 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1056652 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 471328 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 370548 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 537517 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 70 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1276044 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1205760 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9594650 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5010763 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 810566 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 803776 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28888045 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18933308 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 377591 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1141314 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 49340258 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1231429504 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 710021103 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1437320 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4319512 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1947207439 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 7690219 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 24350841 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.107639 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.309986 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 31336515 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16003499 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2764 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 2238925 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2238443 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 482 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 888197 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 14329408 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31554 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 31553 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5463883 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 11447979 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 3030252 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1046563 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 472775 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352055 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 529438 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 135 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1230630 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1206068 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9550052 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4850843 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 854414 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 799200 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28754250 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18474160 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 377323 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1153011 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 48758744 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1225720896 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 689935275 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1439168 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4373560 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1921468899 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 7541383 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 23989921 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.106643 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.308724 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 21730213 89.24% 89.24% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2620161 10.76% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 467 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 21432051 89.34% 89.34% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2557388 10.66% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 482 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 24350841 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 31629791489 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 23989921 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 31215182485 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 184209930 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 206081920 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 14474040275 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 14406948660 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8384067550 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8156637515 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 198003844 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 197502349 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 601473802 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 606443243 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 133924240 # Number of BP lookups -system.cpu1.branchPred.condPredicted 95730476 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5982653 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 100302023 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 73831862 # Number of BTB hits +system.cpu1.branchPred.lookups 134798362 # Number of BP lookups +system.cpu1.branchPred.condPredicted 95816419 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6051956 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 100961028 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 73848042 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.609544 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 15419194 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 1021732 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.145097 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 15861028 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 1023147 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1389,63 +1391,63 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 293746 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 293746 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11413 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 90757 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 293746 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 293746 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 293746 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 102170 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23413.986493 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21412.179846 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 20342.964000 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 100862 98.72% 98.72% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 167 0.16% 98.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 952 0.93% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 45 0.04% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 52 0.05% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 35 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 35 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 12 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 102170 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 527505760 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 527505760 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 527505760 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 90757 88.83% 88.83% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 11413 11.17% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 102170 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 293746 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 282723 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 282723 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10766 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86594 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 282723 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 282723 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 282723 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 97360 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23363.804437 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21328.911362 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 20585.456118 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 96095 98.70% 98.70% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 182 0.19% 98.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 912 0.94% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 29 0.03% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 42 0.04% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 31 0.03% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 49 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 15 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 97360 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1788277352 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1788277352 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1788277352 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 86594 88.94% 88.94% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 10766 11.06% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 97360 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 282723 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 293746 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 102170 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 282723 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97360 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 102170 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 395916 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97360 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 380083 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 86040245 # DTB read hits -system.cpu1.dtb.read_misses 244355 # DTB read misses -system.cpu1.dtb.write_hits 75067998 # DTB write hits -system.cpu1.dtb.write_misses 49391 # DTB write misses +system.cpu1.dtb.read_hits 88221750 # DTB read hits +system.cpu1.dtb.read_misses 234611 # DTB read misses +system.cpu1.dtb.write_hits 76459163 # DTB write hits +system.cpu1.dtb.write_misses 48112 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 37937 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1338 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 8312 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 42183 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 39871 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1240 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 8073 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11189 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 86284600 # DTB read accesses -system.cpu1.dtb.write_accesses 75117389 # DTB write accesses +system.cpu1.dtb.perms_faults 11018 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 88456361 # DTB read accesses +system.cpu1.dtb.write_accesses 76507275 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 161108243 # DTB hits -system.cpu1.dtb.misses 293746 # DTB misses -system.cpu1.dtb.accesses 161401989 # DTB accesses +system.cpu1.dtb.hits 164680913 # DTB hits +system.cpu1.dtb.misses 282723 # DTB misses +system.cpu1.dtb.accesses 164963636 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1475,188 +1477,188 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 65124 # Table walker walks requested -system.cpu1.itb.walker.walksLong 65124 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 508 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55766 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 65124 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 65124 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 65124 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 56274 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 26926.564666 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23857.779953 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 24945.648372 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 54940 97.63% 97.63% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 10 0.02% 97.65% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 1199 2.13% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 37 0.07% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 49 0.09% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 24 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 56274 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 526611260 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 526611260 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 526611260 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 55766 99.10% 99.10% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 508 0.90% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 56274 # Table walker page sizes translated +system.cpu1.itb.walker.walks 64693 # Table walker walks requested +system.cpu1.itb.walker.walksLong 64693 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 526 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55247 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 64693 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 64693 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 64693 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 55773 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26679.495455 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23706.173761 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 24561.580376 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 54531 97.77% 97.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 9 0.02% 97.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 1101 1.97% 99.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 35 0.06% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 52 0.09% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 31 0.06% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 55773 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1787261852 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1787261852 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1787261852 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 55247 99.06% 99.06% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 526 0.94% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 55773 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 65124 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 65124 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64693 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64693 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56274 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56274 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 121398 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 239249458 # ITB inst hits -system.cpu1.itb.inst_misses 65124 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55773 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55773 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 120466 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 241355329 # ITB inst hits +system.cpu1.itb.inst_misses 64693 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26970 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 42183 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 28782 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 220780 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 214506 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 239314582 # ITB inst accesses -system.cpu1.itb.hits 239249458 # DTB hits -system.cpu1.itb.misses 65124 # DTB misses -system.cpu1.itb.accesses 239314582 # DTB accesses -system.cpu1.numCycles 947127317 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 241420022 # ITB inst accesses +system.cpu1.itb.hits 241355329 # DTB hits +system.cpu1.itb.misses 64693 # DTB misses +system.cpu1.itb.accesses 241420022 # DTB accesses +system.cpu1.numCycles 943222184 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 437680583 # Number of instructions committed -system.cpu1.committedOps 515109454 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 47548266 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 4998 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93977493591 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.163969 # CPI: cycles per instruction -system.cpu1.ipc 0.462114 # IPC: instructions per cycle +system.cpu1.committedInsts 444939071 # Number of instructions committed +system.cpu1.committedOps 523893431 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 46484386 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5697 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 94049904755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.119891 # CPI: cycles per instruction +system.cpu1.ipc 0.471722 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13761 # number of quiesce instructions executed -system.cpu1.tickCycles 715510770 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 231616547 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 5225400 # number of replacements -system.cpu1.dcache.tags.tagsinuse 442.020428 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 153149767 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5225912 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.305845 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8545383120500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 442.020428 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.863321 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.863321 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 324837482 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 324837482 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 78835589 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 78835589 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 69932856 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 69932856 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 235045 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 235045 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 136840 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 136840 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1777859 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1777859 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1734680 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1734680 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 148768445 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 148768445 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 149003490 # number of overall hits -system.cpu1.dcache.overall_hits::total 149003490 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3368921 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3368921 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2278073 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2278073 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 647676 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 647676 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 450910 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 450910 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 159516 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 159516 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 201171 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 201171 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5646994 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5646994 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6294670 # number of overall misses -system.cpu1.dcache.overall_misses::total 6294670 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 55794276000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 55794276000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 51841670500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 51841670500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 21264976000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 21264976000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2730537500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2730537500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5515974000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5515974000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4942500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4942500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 107635946500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 107635946500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 107635946500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 107635946500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 82204510 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 82204510 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 72210929 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 72210929 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 882721 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 882721 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 587750 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 587750 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1937375 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1937375 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1935851 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1935851 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 154415439 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 154415439 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 155298160 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 155298160 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040982 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.040982 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.031547 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.031547 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.733727 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.733727 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.767180 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.767180 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082336 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.082336 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103919 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103919 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036570 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.036570 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040533 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.040533 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16561.467603 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16561.467603 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22756.808276 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22756.808276 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 47160.133951 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 47160.133951 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17117.640237 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17117.640237 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27419.329824 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27419.329824 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 5760 # number of quiesce instructions executed +system.cpu1.tickCycles 722277565 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 220944619 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 5315264 # number of replacements +system.cpu1.dcache.tags.tagsinuse 430.485039 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 156623393 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5315774 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.463892 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8391021559000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.485039 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.840791 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.840791 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 332053228 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 332053228 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 80890555 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 80890555 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 71395384 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 71395384 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 230003 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 230003 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 70856 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 70856 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1784180 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1784180 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1762697 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1762697 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 152285939 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 152285939 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 152515942 # number of overall hits +system.cpu1.dcache.overall_hits::total 152515942 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3470383 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3470383 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2256465 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2256465 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 629037 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 629037 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 454847 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 454847 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 178965 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 178965 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 198846 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 198846 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5726848 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5726848 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6355885 # number of overall misses +system.cpu1.dcache.overall_misses::total 6355885 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 57691506500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 57691506500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 50161466000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 50161466000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 17158564500 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 17158564500 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2980004000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2980004000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5546868500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5546868500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5779500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5779500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 107852972500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 107852972500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 107852972500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 107852972500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 84360938 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 84360938 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 73651849 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 73651849 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 859040 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 859040 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 525703 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 525703 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1963145 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1963145 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1961543 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1961543 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 158012787 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 158012787 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 158871827 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 158871827 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041137 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.041137 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030637 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030637 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.732256 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.732256 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.865217 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.865217 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091162 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091162 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101372 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101372 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036243 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.036243 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040006 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.040006 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16623.959517 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16623.959517 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22230.110372 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22230.110372 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 37723.815921 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 37723.815921 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16651.322884 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16651.322884 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27895.298372 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27895.298372 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19060.750994 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19060.750994 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17099.537625 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17099.537625 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18832.868010 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18832.868010 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16968.993696 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16968.993696 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1665,161 +1667,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 5225429 # number of writebacks -system.cpu1.dcache.writebacks::total 5225429 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 382545 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 382545 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 937825 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 937825 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # 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number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44483005500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 30789351000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 30789351000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15729879000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15729879000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20808027500 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20808027500 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1765421000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1765421000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5312775000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5312775000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4745500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4745500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 75272356500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 75272356500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 91002235500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 91002235500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3151598000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3151598000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2962839500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2962839500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 6114437500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 6114437500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036329 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036329 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018560 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018560 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.733407 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.733407 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.767081 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.767081 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060875 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060875 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103901 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103901 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028019 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028019 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032029 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032029 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14895.313082 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14895.313082 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22972.875916 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22972.875916 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24297.227036 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24297.227036 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 46152.678706 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 46152.678706 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14969.060015 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14969.060015 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26413.713041 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26413.713041 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5315289 # number of writebacks +system.cpu1.dcache.writebacks::total 5315289 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 392143 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 392143 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 920496 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 920496 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 60 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 60 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44592 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44592 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 44 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 44 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1312639 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1312639 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1312639 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1312639 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3078240 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3078240 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1335969 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1335969 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 628734 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 628734 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 454787 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 454787 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 134373 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 134373 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 198802 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 198802 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4414209 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4414209 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5042943 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5042943 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6731 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6731 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7202 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7202 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 13933 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 13933 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 46218671000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 46218671000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 29907223500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 29907223500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14916352500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14916352500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 16698306500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 16698306500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1935752000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1935752000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5344630000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5344630000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5479500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5479500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 76125894500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 76125894500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 91042247000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 91042247000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 839317500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 839317500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1016449500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1016449500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1855767000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1855767000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036489 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036489 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018139 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018139 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.731903 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.731903 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.865103 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.865103 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068448 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068448 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101350 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101350 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027936 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027936 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031742 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031742 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15014.641808 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15014.641808 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22386.165772 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22386.165772 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23724.424796 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23724.424796 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 36716.763012 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 36716.763012 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14405.810691 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14405.810691 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26884.186276 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26884.186276 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17397.480461 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17397.480461 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18295.517929 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18295.517929 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164754.979351 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 164754.979351 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169624.978531 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169624.978531 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 167079.393923 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 167079.393923 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17245.647975 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17245.647975 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18053.396003 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18053.396003 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 124694.324766 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 124694.324766 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 141134.337684 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 141134.337684 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 133192.205555 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 133192.205555 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 9231311 # number of replacements -system.cpu1.icache.tags.tagsinuse 506.694166 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 229790487 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 9231823 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 24.891128 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8386495264000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.694166 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989637 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.989637 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 9419212 # number of replacements +system.cpu1.icache.tags.tagsinuse 506.776997 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 231714815 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 9419724 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 24.598896 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8379179578000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.776997 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989799 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.989799 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 76 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 487276445 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 487276445 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 229790487 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 229790487 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 229790487 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 229790487 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 229790487 # number of overall hits -system.cpu1.icache.overall_hits::total 229790487 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 9231824 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 9231824 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 9231824 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 9231824 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 9231824 # number of overall misses -system.cpu1.icache.overall_misses::total 9231824 # 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average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10238.978018 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10238.978018 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 491688802 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 491688802 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 231714815 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 231714815 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 231714815 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 231714815 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 231714815 # number of overall hits +system.cpu1.icache.overall_hits::total 231714815 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 9419724 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 9419724 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 9419724 # 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average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10210.759094 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10210.759094 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10210.759094 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10210.759094 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10210.759094 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1828,257 +1830,256 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # 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number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 89908531500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 89908531500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 89908531500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 89908531500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 89908531500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 89908531500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12950500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 12950500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 12950500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 12950500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038623 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038623 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038623 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.038623 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038623 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.038623 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9738.978072 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9738.978072 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9738.978072 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9738.978072 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9738.978072 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9738.978072 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140766.304348 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140766.304348 # average overall mshr uncacheable latency +system.cpu1.icache.writebacks::writebacks 9419212 # number of writebacks +system.cpu1.icache.writebacks::total 9419212 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9419724 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 9419724 # 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average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140655.913978 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140655.913978 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140655.913978 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7101301 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7101636 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 296 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7256046 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7256259 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 183 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 867300 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2326720 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13467.956369 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 23154784 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2342909 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 9.882921 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9860254327500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12598.584174 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 60.491814 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 58.201363 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 750.679017 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.768957 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003692 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003552 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.045818 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.822019 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1395 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14742 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 404 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 859 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 122 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 31 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1149 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5193 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7319 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 995 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.085144 # 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number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3648745 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 12938711 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 576439 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 168221 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 8545306 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3648745 # number of overall hits -system.cpu1.l2cache.overall_hits::total 12938711 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12346 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8532 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 20878 # number of ReadReq misses +system.cpu1.l2cache.prefetcher.pfSpanPage 925773 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2304751 # 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Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003538 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.043762 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.821221 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1043 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 71 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14722 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 319 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 650 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 71 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 45 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 24 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5507 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8143 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 659 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.063660 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004333 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.898560 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 496871809 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 496871809 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 551874 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 166024 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 717898 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 3295376 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 3295376 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 11437109 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 11437109 # number of WritebackClean hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 567 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 567 # number of UpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 865133 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 865133 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8732847 # 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mshr miss rate for WritebackDirty accesses system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997432 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997432 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997463 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997463 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.217571 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.217571 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.074364 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.074364 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.258364 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.258364 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.595469 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.595469 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020969 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048259 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.074364 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.248992 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.129144 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020969 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048259 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.074364 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.248992 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.217724 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.217724 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.072919 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.072919 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.251698 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.251698 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.578401 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.578401 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021224 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048333 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.072919 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.244056 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.126821 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021224 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048333 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.072919 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.244056 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.180069 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 42550.745181 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 47939.449004 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 44752.586702 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59843.308887 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 59843.308887 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31713.378069 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31713.378069 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18893.060279 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18893.060279 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 857499.800000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 857499.800000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 49248.958770 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 49248.958770 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29602.674527 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29602.674527 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33120.767364 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33120.767364 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 64362.331558 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 64362.331558 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 42550.745181 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 47939.449004 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29602.674527 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36358.697069 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34034.379570 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 42550.745181 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 47939.449004 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29602.674527 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36358.697069 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59843.308887 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 41333.361365 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 156750.379006 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156635.580875 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162122.831625 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162122.831625 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 159314.610886 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 159248.037505 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.174889 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 39824.768112 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 45791.982922 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 42291.337811 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53304.865332 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 53304.865332 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31396.571949 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31396.571949 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19362.414921 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19362.414921 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 998200 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 998200 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47276.636115 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47276.636115 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29777.775756 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29777.775756 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33589.328536 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33589.328536 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 49894.194371 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 49894.194371 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 39824.768112 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 45791.982922 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29777.775756 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36335.678304 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34048.993127 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 39824.768112 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 45791.982922 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29777.775756 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36335.678304 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53304.865332 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 39341.423766 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116683.405140 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 116901.084408 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133624.618162 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 133624.618162 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 125440.357425 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 125488.200485 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 29757775 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15206900 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2197 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 2096240 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2095918 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 322 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 863744 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 13939008 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 17467 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 17467 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4436321 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 11191891 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2888082 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 986942 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 436269 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 365311 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 490098 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1199193 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1126648 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9231824 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4839539 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 455831 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 448771 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27695142 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16951918 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 371352 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1238709 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 46257121 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1181646464 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 652642726 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1414024 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4710280 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1840413494 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 6842316 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 22455736 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.107935 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.310344 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 30305906 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15477606 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2013 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 2090955 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2090626 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 329 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 826390 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 14176907 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 7202 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 7202 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4434109 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 11439122 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2886028 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 940232 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 438079 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 353355 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 486110 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 135 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1143505 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1120857 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9419724 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4894979 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 500608 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 453070 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 28258846 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17165188 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 367696 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1190168 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 46981898 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1205697856 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 663528133 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1395656 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4510728 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1875132373 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 6705692 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 22548909 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.107052 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.309227 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 20032307 89.21% 89.21% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2423107 10.79% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 322 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 20135326 89.30% 89.30% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2413254 10.70% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 329 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 22455736 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 29622476486 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 22548909 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 30147553476 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 182393833 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 176219861 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 13851399924 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 14133264904 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7774596662 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7885730738 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 194664868 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 193298381 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 650073200 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 626482687 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40417 # Transaction distribution -system.iobus.trans_dist::ReadResp 40417 # Transaction distribution -system.iobus.trans_dist::WriteReq 136988 # Transaction distribution -system.iobus.trans_dist::WriteResp 136988 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47856 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40387 # Transaction distribution +system.iobus.trans_dist::ReadResp 40387 # Transaction distribution +system.iobus.trans_dist::WriteReq 136979 # Transaction distribution +system.iobus.trans_dist::WriteResp 136979 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47868 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2332,15 +2332,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122998 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231732 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231732 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231694 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231694 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354810 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47876 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354732 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2351,103 +2351,103 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156013 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7355280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155996 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355128 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7355128 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7513379 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 47192501 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7513210 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 47188500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 327500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 26190001 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 26264003 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36429000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36399000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 568769538 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568799211 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92997000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92966000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148172000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148134000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115847 # number of replacements -system.iocache.tags.tagsinuse 11.301670 # Cycle average of tags in use +system.iocache.tags.replacements 115828 # number of replacements +system.iocache.tags.tagsinuse 11.305227 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115863 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115844 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9145489939000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.832621 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.469049 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239539 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466816 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706354 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9138950806000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.834041 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.471186 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239628 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466949 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706577 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1043151 # Number of tag accesses -system.iocache.tags.data_accesses 1043151 # Number of data accesses +system.iocache.tags.tag_accesses 1042980 # Number of tag accesses +system.iocache.tags.data_accesses 1042980 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8882 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8919 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8863 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8900 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8882 # number of demand (read+write) misses -system.iocache.demand_misses::total 8922 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8863 # number of demand (read+write) misses +system.iocache.demand_misses::total 8903 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8882 # number of overall misses -system.iocache.overall_misses::total 8922 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1701700997 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1706898997 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8863 # number of overall misses +system.iocache.overall_misses::total 8903 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5197000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1710789963 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1715986963 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13567134541 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13567134541 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1701700997 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1707267997 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1701700997 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1707267997 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13562248248 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13562248248 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5566000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1710789963 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1716355963 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5566000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1710789963 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1716355963 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8882 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8919 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8863 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8900 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8882 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8922 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8863 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8903 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8882 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8922 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8863 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8903 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2461,55 +2461,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 191589.844292 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 191377.844714 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140459.459459 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 193026.059235 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 192807.523933 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126814.612849 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126814.612849 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 191589.844292 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 191354.852836 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 191589.844292 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 191354.852836 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34809 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126768.939729 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126768.939729 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139150 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 193026.059235 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 192784.001236 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139150 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 193026.059235 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 192784.001236 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 35587 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3501 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3530 # 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Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3331.837675 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6323.626930 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9108.802265 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.329693 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002501 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003407 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.086512 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.098577 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.148456 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002492 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003120 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 6019.423287 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 241.036337 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 317.216521 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3872.812023 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 8822.287754 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 12306.009376 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.331223 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001568 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.001770 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.075778 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.076202 # 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Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 3377 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 6697 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 10 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 176 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2228 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 13666 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 34520 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.155884 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.002853 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.773956 # 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mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.258222 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.318577 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.069989 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.173219 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.394945 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.203607 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.760748 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.475780 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.675195 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.204779 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.223960 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.096122 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.229928 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.417793 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.258222 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.318577 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.069989 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.217274 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.394945 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.222974 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.204779 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.223960 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.096122 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.229928 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.417793 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.258222 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.318577 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.069989 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.217274 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.394945 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.222974 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70784.132277 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70454.459731 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70622.002003 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73717.496713 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73474.839400 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73596.297820 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128263.872968 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124633.215096 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 126819.155867 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130520.146102 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131240.563101 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124649.624738 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130514.541956 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 165200.841671 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129302.324337 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130311.227058 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124535.368286 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129696.244873 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156795.883680 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 146076.538245 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69978.879648 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69612.317690 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69901.332925 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130520.146102 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131240.563101 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124649.624738 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 129665.397702 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 165200.841671 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129302.324337 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130311.227058 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124535.368286 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 128141.349774 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156795.883680 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 143389.033978 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130520.146102 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131240.563101 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124649.624738 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 129665.397702 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 165200.841671 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129302.324337 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130311.227058 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124535.368286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 128141.349774 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156795.883680 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 143389.033978 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168601.820174 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 138760.548387 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 130189.676437 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164179.590555 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145115.792122 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155533.936466 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164525.170581 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 98704.194085 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 129944.590793 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163469.575571 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 116608.102749 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154761.116604 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 166307.988812 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 141794.024977 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 137723.145408 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164002.261932 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 107960.094609 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 137341.128933 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 91058 # Transaction distribution -system.membus.trans_dist::ReadResp 962815 # Transaction distribution -system.membus.trans_dist::WriteReq 38515 # Transaction distribution -system.membus.trans_dist::WriteResp 38515 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1239858 # Transaction distribution -system.membus.trans_dist::CleanEvict 269903 # Transaction distribution -system.membus.trans_dist::UpgradeReq 432314 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 322959 # Transaction distribution +system.membus.trans_dist::ReadReq 91274 # Transaction distribution +system.membus.trans_dist::ReadResp 916539 # Transaction distribution +system.membus.trans_dist::WriteReq 38755 # Transaction distribution +system.membus.trans_dist::WriteResp 38755 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1197090 # Transaction distribution +system.membus.trans_dist::CleanEvict 262945 # Transaction distribution +system.membus.trans_dist::UpgradeReq 440993 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 308067 # Transaction distribution system.membus.trans_dist::UpgradeResp 23 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 660243 # Transaction distribution -system.membus.trans_dist::ReadExResp 640684 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 871757 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106984 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122998 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 144406 # Transaction distribution +system.membus.trans_dist::ReadExResp 127298 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 825265 # Transaction distribution +system.membus.trans_dist::InvalidateReq 666679 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122958 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26126 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5285035 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5434211 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238560 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238560 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5672771 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156013 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27076 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4666640 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4816726 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238694 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238694 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5055420 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155996 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52252 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 172058368 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 172267957 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7280448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7280448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 179548405 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 621430 # Total snoops (count) -system.membus.snoop_fanout::samples 4033661 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 133490240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 133701712 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7291456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7291456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 140993168 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 609728 # Total snoops (count) +system.membus.snoop_fanout::samples 3975535 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4033661 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3975535 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4033661 # Request fanout histogram -system.membus.reqLayer0.occupancy 110232498 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3975535 # Request fanout histogram +system.membus.reqLayer0.occupancy 110272997 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21930998 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22907496 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8790771874 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8443265855 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8289711005 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5364054651 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45511990 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45386996 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3191,52 +3215,54 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 12834320 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6946519 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2149909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 154845 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 139190 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 15655 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 91060 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4987176 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38515 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38515 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 4108038 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 3110241 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 736356 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 408827 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1145183 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 116 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1157626 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1157626 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4903350 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 106984 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10442900 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8319786 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 18762686 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 296101599 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 218919254 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 515020853 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3228731 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9024232 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.357725 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.482936 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 12590063 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6816351 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2112405 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 136080 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 123352 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 12728 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 91276 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4889046 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38755 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38755 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 4006843 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 3033326 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 740212 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 393009 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1133221 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 135 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 135 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 301958 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 301958 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4804997 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 940884 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 833900 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10292862 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8190937 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 18483799 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255537947 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 200300853 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 455838800 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3066288 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8826957 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.357421 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.482240 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5811691 64.40% 64.40% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3196886 35.43% 99.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 15655 0.17% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5684742 64.40% 64.40% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3129487 35.45% 99.86% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 12728 0.14% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9024232 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9776043593 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8826957 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9586281743 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2607881 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2585661 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 5412935477 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4723415116 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4393187885 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4064152578 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 1a67ea010..6b3e79c96 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.667476 # Number of seconds simulated -sim_ticks 51667476471000 # Number of ticks simulated -final_tick 51667476471000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.660643 # Number of seconds simulated +sim_ticks 51660642512000 # Number of ticks simulated +final_tick 51660642512000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 274767 # Simulator instruction rate (inst/s) -host_op_rate 322852 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15389929524 # Simulator tick rate (ticks/s) -host_mem_usage 683068 # Number of bytes of host memory used -host_seconds 3357.23 # Real time elapsed on the host -sim_insts 922453344 # Number of instructions simulated -sim_ops 1083887959 # Number of ops (including micro ops) simulated +host_inst_rate 304990 # Simulator instruction rate (inst/s) +host_op_rate 358371 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16937149026 # Simulator tick rate (ticks/s) +host_mem_usage 683404 # Number of bytes of host memory used +host_seconds 3050.14 # Real time elapsed on the host +sim_insts 930261902 # Number of instructions simulated +sim_ops 1093080704 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 349632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 295488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10205120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 93689288 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 408000 # Number of bytes read from this memory -system.physmem.bytes_read::total 104947528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10205120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10205120 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 87402048 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 377280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10274880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 61682056 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 384384 # Number of bytes read from this memory +system.physmem.bytes_read::total 73038600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10274880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10274880 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 89590976 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 87422628 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 5463 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 4617 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 159455 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1463908 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6375 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1639818 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1365657 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 89611556 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 5895 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5000 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 160545 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 963795 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6006 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1141241 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1399859 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1368230 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 6767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 5719 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 197515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1813313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2031211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197515 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197515 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1691626 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1402432 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 7303 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 6194 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 198892 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1193985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1413815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 198892 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 198892 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1734221 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1692024 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1691626 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 6767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 5719 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1813711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3723235 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1639818 # Number of read requests accepted -system.physmem.writeReqs 1368230 # Number of write requests accepted -system.physmem.readBursts 1639818 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1368230 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 104895040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 53312 # Total number of bytes read from write queue -system.physmem.bytesWritten 87421376 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 104947528 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 87422628 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 833 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2255 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1734619 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1734221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 7303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 6194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 198892 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1194384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3148435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1141241 # Number of read requests accepted +system.physmem.writeReqs 1402432 # Number of write requests accepted +system.physmem.readBursts 1141241 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1402432 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 72981760 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 57664 # Total number of bytes read from write queue +system.physmem.bytesWritten 89610624 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 73038600 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 89611556 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 901 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 99403 # Per bank write bursts -system.physmem.perBankRdBursts::1 105228 # Per bank write bursts -system.physmem.perBankRdBursts::2 100047 # Per bank write bursts -system.physmem.perBankRdBursts::3 95494 # Per bank write bursts -system.physmem.perBankRdBursts::4 102929 # Per bank write bursts -system.physmem.perBankRdBursts::5 111535 # Per bank write bursts -system.physmem.perBankRdBursts::6 97078 # Per bank write bursts -system.physmem.perBankRdBursts::7 98055 # Per bank write bursts -system.physmem.perBankRdBursts::8 92724 # Per bank write bursts -system.physmem.perBankRdBursts::9 154002 # Per bank write bursts -system.physmem.perBankRdBursts::10 99475 # Per bank write bursts -system.physmem.perBankRdBursts::11 105000 # Per bank write bursts -system.physmem.perBankRdBursts::12 94287 # Per bank write bursts -system.physmem.perBankRdBursts::13 95690 # Per bank write bursts -system.physmem.perBankRdBursts::14 90913 # Per bank write bursts -system.physmem.perBankRdBursts::15 97125 # Per bank write bursts -system.physmem.perBankWrBursts::0 83951 # Per bank write bursts -system.physmem.perBankWrBursts::1 87043 # Per bank write bursts -system.physmem.perBankWrBursts::2 85245 # Per bank write bursts -system.physmem.perBankWrBursts::3 83208 # Per bank write bursts -system.physmem.perBankWrBursts::4 88814 # Per bank write bursts -system.physmem.perBankWrBursts::5 93904 # Per bank write bursts -system.physmem.perBankWrBursts::6 83820 # Per bank write bursts -system.physmem.perBankWrBursts::7 85248 # Per bank write bursts -system.physmem.perBankWrBursts::8 81467 # Per bank write bursts -system.physmem.perBankWrBursts::9 88240 # Per bank write bursts -system.physmem.perBankWrBursts::10 85354 # Per bank write bursts -system.physmem.perBankWrBursts::11 89463 # Per bank write bursts -system.physmem.perBankWrBursts::12 82403 # Per bank write bursts -system.physmem.perBankWrBursts::13 83577 # Per bank write bursts -system.physmem.perBankWrBursts::14 80367 # Per bank write bursts -system.physmem.perBankWrBursts::15 83855 # Per bank write bursts +system.physmem.perBankRdBursts::0 67748 # Per bank write bursts +system.physmem.perBankRdBursts::1 75024 # Per bank write bursts +system.physmem.perBankRdBursts::2 69908 # Per bank write bursts +system.physmem.perBankRdBursts::3 64252 # Per bank write bursts +system.physmem.perBankRdBursts::4 67104 # Per bank write bursts +system.physmem.perBankRdBursts::5 72834 # Per bank write bursts +system.physmem.perBankRdBursts::6 66007 # Per bank write bursts +system.physmem.perBankRdBursts::7 65201 # Per bank write bursts +system.physmem.perBankRdBursts::8 62658 # Per bank write bursts +system.physmem.perBankRdBursts::9 122060 # Per bank write bursts +system.physmem.perBankRdBursts::10 69885 # Per bank write bursts +system.physmem.perBankRdBursts::11 74467 # Per bank write bursts +system.physmem.perBankRdBursts::12 66975 # Per bank write bursts +system.physmem.perBankRdBursts::13 66087 # Per bank write bursts +system.physmem.perBankRdBursts::14 62026 # Per bank write bursts +system.physmem.perBankRdBursts::15 68104 # Per bank write bursts +system.physmem.perBankWrBursts::0 85430 # Per bank write bursts +system.physmem.perBankWrBursts::1 89554 # Per bank write bursts +system.physmem.perBankWrBursts::2 89147 # Per bank write bursts +system.physmem.perBankWrBursts::3 85797 # Per bank write bursts +system.physmem.perBankWrBursts::4 87375 # Per bank write bursts +system.physmem.perBankWrBursts::5 90488 # Per bank write bursts +system.physmem.perBankWrBursts::6 83025 # Per bank write bursts +system.physmem.perBankWrBursts::7 85134 # Per bank write bursts +system.physmem.perBankWrBursts::8 84926 # Per bank write bursts +system.physmem.perBankWrBursts::9 90963 # Per bank write bursts +system.physmem.perBankWrBursts::10 87836 # Per bank write bursts +system.physmem.perBankWrBursts::11 92829 # Per bank write bursts +system.physmem.perBankWrBursts::12 87557 # Per bank write bursts +system.physmem.perBankWrBursts::13 87424 # Per bank write bursts +system.physmem.perBankWrBursts::14 84847 # Per bank write bursts +system.physmem.perBankWrBursts::15 87834 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 37 # Number of times write queue was full causing retry -system.physmem.totGap 51667474307000 # Total gap between requests +system.physmem.numWrRetry 50 # Number of times write queue was full causing retry +system.physmem.totGap 51660640624000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1639803 # Read request sizes (log2) +system.physmem.readPktSize::6 1141226 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1365657 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1314237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 318417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 918 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1399859 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1072907 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61649 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 723 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 530 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 676 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 362 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 95 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 53 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 449 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 532 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -159,167 +159,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 14698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 18189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 67736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 80790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 82454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 81257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 81296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 82033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 83039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 82637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 83634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 86681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 83517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 83880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 94578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 83323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 84131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 81331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 109 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 646147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 297.635603 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 173.901229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.036577 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 253673 39.26% 39.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 155474 24.06% 63.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 60360 9.34% 72.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 34960 5.41% 78.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 25496 3.95% 82.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 18768 2.90% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 14047 2.17% 87.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 13088 2.03% 89.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 70281 10.88% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 646147 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 79019 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.741467 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 283.796699 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 79016 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 79019 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 79019 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.286463 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.794878 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.949851 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 76956 97.39% 97.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 330 0.42% 97.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 47 0.06% 97.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 101 0.13% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 35 0.04% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 85 0.11% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 245 0.31% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 21 0.03% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 324 0.41% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 69 0.09% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 26 0.03% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 53 0.07% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 312 0.39% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 39 0.05% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 28 0.04% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 118 0.15% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 171 0.22% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::15 34167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 39504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 78543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 80306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 82649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 80800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 81768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 85658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 85076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 81194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 82459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 85799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 82823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 82988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 84778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 80804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 79640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 79007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 132 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 648089 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 250.879123 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 152.008733 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 285.888919 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 280289 43.25% 43.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 166837 25.74% 68.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 60882 9.39% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 33521 5.17% 83.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 23050 3.56% 87.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 16307 2.52% 89.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 11522 1.78% 91.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9570 1.48% 92.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 46111 7.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 648089 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 76765 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.854530 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 142.199486 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 76763 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 76765 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 76765 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.239640 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.683114 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.179019 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 64873 84.51% 84.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 9480 12.35% 96.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 455 0.59% 97.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 326 0.42% 97.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 60 0.08% 97.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 114 0.15% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 230 0.30% 98.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 35 0.05% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 294 0.38% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 75 0.10% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 27 0.04% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 50 0.07% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 318 0.41% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 35 0.05% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 31 0.04% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 111 0.14% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 179 0.23% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 5 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 5 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 6 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 16 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 14 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-163 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 7 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 79019 # Writes before turning the bus around for reads -system.physmem.totQLat 26490910104 # Total ticks spent queuing -system.physmem.totMemAccLat 57221878854 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8194925000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16163.00 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 76765 # Writes before turning the bus around for reads +system.physmem.totQLat 16541565713 # Total ticks spent queuing +system.physmem.totMemAccLat 37922940713 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5701700000 # Total ticks spent in databus transfers +system.physmem.avgQLat 14505.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34913.00 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.03 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.69 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.03 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.69 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 33255.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.41 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.73 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.57 # Average write queue length when enqueuing -system.physmem.readRowHits 1332864 # Number of row buffer hits during reads -system.physmem.writeRowHits 1025932 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.32 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.11 # Row buffer hit rate for writes -system.physmem.avgGap 17176412.85 # Average gap between requests -system.physmem.pageHitRate 78.50 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2496243960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1362037875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6316198200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4479189840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3374668374480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1323055672425 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29839910639250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34552288356030 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.743489 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49640417958020 # Time in different power states -system.physmem_0.memoryStateTime::REF 1725290580000 # Time in different power states +system.physmem.avgWrQLen 25.35 # Average write queue length when enqueuing +system.physmem.readRowHits 872320 # Number of row buffer hits during reads +system.physmem.writeRowHits 1020096 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.85 # Row buffer hit rate for writes +system.physmem.avgGap 20309466.12 # Average gap between requests +system.physmem.pageHitRate 74.49 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2456674920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1340447625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4274961600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4509756000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3374221858800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1317434781870 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29840739448500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34544977929315 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.690476 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49641970693393 # Time in different power states +system.physmem_0.memoryStateTime::REF 1725062300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 301767793230 # Time in different power states +system.physmem_0.memoryStateTime::ACT 293608746107 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2388627360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1303318500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6467877000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4372224480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3374668374480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1316624734350 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29845551821250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34551376977420 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.725849 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49649780004526 # Time in different power states -system.physmem_1.memoryStateTime::REF 1725290580000 # Time in different power states +system.physmem_1.actEnergy 2442877920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1332919500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4619643600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4563319680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3374221858800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1319027164650 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29839342629750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34545550413900 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.701557 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49639611346782 # Time in different power states +system.physmem_1.memoryStateTime::REF 1725062300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 292405760474 # Time in different power states +system.physmem_1.memoryStateTime::ACT 295966370718 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -343,15 +340,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 252598760 # Number of BP lookups -system.cpu.branchPred.condPredicted 176508431 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 11957032 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 185598793 # Number of BTB lookups -system.cpu.branchPred.BTBHits 131565493 # Number of BTB hits +system.cpu.branchPred.lookups 254908438 # Number of BP lookups +system.cpu.branchPred.condPredicted 178242351 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12005241 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 187385958 # Number of BTB lookups +system.cpu.branchPred.BTBHits 132827814 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.887041 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 30959293 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2131771 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 70.884615 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31213174 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2144347 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -382,63 +379,64 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 560635 # Table walker walks requested -system.cpu.dtb.walker.walksLong 560635 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20884 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 178593 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 560635 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 560635 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 560635 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 199477 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 26985.070961 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 22842.355807 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 20873.513445 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 197251 98.88% 98.88% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 98.89% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 1888 0.95% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 57 0.03% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 109 0.05% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 46 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 97 0.05% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 13 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 567320 # Table walker walks requested +system.cpu.dtb.walker.walksLong 567320 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20723 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 182198 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 567320 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 567320 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 567320 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 202921 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 27429.733739 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 23186.871186 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 21494.309968 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 200464 98.79% 98.79% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 14 0.01% 98.80% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 2073 1.02% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 61 0.03% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 133 0.07% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 52 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 92 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 15 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 9 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 199477 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 202921 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples -1569959592 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 -1569959592 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total -1569959592 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 178594 89.53% 89.53% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 20884 10.47% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 199478 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 560635 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 182199 89.79% 89.79% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 20723 10.21% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 202922 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 567320 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 560635 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 199478 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 567320 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 202922 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 199478 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 760113 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 202922 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 770242 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 178339564 # DTB read hits -system.cpu.dtb.read_misses 462901 # DTB read misses -system.cpu.dtb.write_hits 158016400 # DTB write hits -system.cpu.dtb.write_misses 97734 # DTB write misses +system.cpu.dtb.read_hits 179769202 # DTB read hits +system.cpu.dtb.read_misses 468572 # DTB read misses +system.cpu.dtb.write_hits 159383411 # DTB write hits +system.cpu.dtb.write_misses 98748 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 45299 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 78401 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1394 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 14946 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 45817 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 78846 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1354 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 15815 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23063 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 178802465 # DTB read accesses -system.cpu.dtb.write_accesses 158114134 # DTB write accesses +system.cpu.dtb.perms_faults 23199 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 180237774 # DTB read accesses +system.cpu.dtb.write_accesses 159482159 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 336355964 # DTB hits -system.cpu.dtb.misses 560635 # DTB misses -system.cpu.dtb.accesses 336916599 # DTB accesses +system.cpu.dtb.hits 339152613 # DTB hits +system.cpu.dtb.misses 567320 # DTB misses +system.cpu.dtb.accesses 339719933 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -468,189 +466,184 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 134932 # Table walker walks requested -system.cpu.itb.walker.walksLong 134932 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1079 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 117658 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 134932 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 134932 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 134932 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 118737 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 30245.892182 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 25862.614601 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 23195.505917 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-32767 58684 49.42% 49.42% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-65535 57510 48.43% 97.86% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-98303 2 0.00% 97.86% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::98304-131071 7 0.01% 97.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-163839 1905 1.60% 99.47% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::163840-196607 424 0.36% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-229375 23 0.02% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::229376-262143 17 0.01% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-294911 94 0.08% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::294912-327679 21 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-360447 17 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::360448-393215 8 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-425983 17 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::425984-458751 8 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 118737 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 135719 # Table walker walks requested +system.cpu.itb.walker.walksLong 135719 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1067 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 118398 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 135719 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 135719 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 135719 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 119465 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 30823.412715 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 26220.565528 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 24055.511247 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 116639 97.63% 97.63% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 7 0.01% 97.64% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 2565 2.15% 99.79% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 80 0.07% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 132 0.11% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 26 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 13 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 119465 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples -1570990092 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 -1570990092 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total -1570990092 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 117658 99.09% 99.09% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1079 0.91% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 118737 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 118398 99.11% 99.11% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1067 0.89% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 119465 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 134932 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 134932 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 135719 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 135719 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118737 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 118737 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 253669 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 439091546 # ITB inst hits -system.cpu.itb.inst_misses 134932 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119465 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 119465 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 255184 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 443155891 # ITB inst hits +system.cpu.itb.inst_misses 135719 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 45299 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 56478 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 45817 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 56716 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 354973 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 363456 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 439226478 # ITB inst accesses -system.cpu.itb.hits 439091546 # DTB hits -system.cpu.itb.misses 134932 # DTB misses -system.cpu.itb.accesses 439226478 # DTB accesses -system.cpu.numCycles 2564620605 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 443291610 # ITB inst accesses +system.cpu.itb.hits 443155891 # DTB hits +system.cpu.itb.misses 135719 # DTB misses +system.cpu.itb.accesses 443291610 # DTB accesses +system.cpu.numCycles 2560430377 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 922453344 # Number of instructions committed -system.cpu.committedOps 1083887959 # Number of ops (including micro ops) committed -system.cpu.discardedOps 92875630 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7622 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100771468164 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.780217 # CPI: cycles per instruction -system.cpu.ipc 0.359684 # IPC: instructions per cycle +system.cpu.committedInsts 930261902 # Number of instructions committed +system.cpu.committedOps 1093080704 # Number of ops (including micro ops) committed +system.cpu.discardedOps 94082781 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7654 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100762000477 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.752376 # CPI: cycles per instruction +system.cpu.ipc 0.363322 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16482 # number of quiesce instructions executed -system.cpu.tickCycles 1741581813 # Number of cycles that the object actually ticked -system.cpu.idleCycles 823038792 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 10731841 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.930081 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 320513038 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 10732353 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.864191 # Average number of references to valid blocks. +system.cpu.kern.inst.quiesce 16514 # number of quiesce instructions executed +system.cpu.tickCycles 1756892100 # Number of cycles that the object actually ticked +system.cpu.idleCycles 803538277 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 10835760 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.930073 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 323161698 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10836272 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.822221 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 7087675500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.930081 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.930073 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 393 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 381 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1346389769 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1346389769 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 164045150 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 164045150 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 147553918 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 147553918 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 512343 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 512343 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 335860 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 335860 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3854660 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3854660 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4163151 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4163151 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 311599068 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 311599068 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 312111411 # number of overall hits -system.cpu.dcache.overall_hits::total 312111411 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6370722 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6370722 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4130704 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4130704 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1398816 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1398816 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1238819 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1238819 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 310200 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 310200 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 10501426 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10501426 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 11900242 # number of overall misses -system.cpu.dcache.overall_misses::total 11900242 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 117402431000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 117402431000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 199951337000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 199951337000 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 84556806000 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 84556806000 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5139718000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5139718000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 317353768000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 317353768000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 317353768000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 317353768000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 170415872 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 170415872 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 151684622 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 151684622 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1911159 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1911159 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1574679 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1574679 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4164860 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4164860 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4163152 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4163152 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 322100494 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 322100494 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 324011653 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 324011653 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037383 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.037383 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027232 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027232 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.731920 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.731920 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786712 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.786712 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.074480 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.074480 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032603 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032603 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036728 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18428.434171 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18428.434171 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48406.116003 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48406.116003 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 68255.980898 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 68255.980898 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16569.045777 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16569.045777 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30220.064208 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30220.064208 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26667.841545 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26667.841545 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 1357625936 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1357625936 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 165326360 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 165326360 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148822242 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148822242 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 515783 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 515783 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 336254 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 336254 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3901835 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3901835 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4210707 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4210707 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 314148602 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 314148602 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 314664385 # number of overall hits +system.cpu.dcache.overall_hits::total 314664385 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6435963 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6435963 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4178110 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4178110 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1419320 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1419320 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1240241 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1240241 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 310588 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 310588 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # 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number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5170357500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 245500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 245500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 325831586000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 325831586000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 325831586000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 325831586000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 171762323 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 171762323 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 153000352 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 153000352 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1935103 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1935103 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1576495 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1576495 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4212423 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4212423 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4210710 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4210710 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 324762675 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 324762675 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 326697778 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 326697778 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037470 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.037470 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027308 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027308 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.733460 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.733460 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786708 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.786708 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073731 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073731 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032683 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032683 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036833 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036833 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18534.839775 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18534.839775 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49434.323893 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 49434.323893 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 43056.634960 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 43056.634960 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16646.996986 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16646.996986 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 81833.333333 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 81833.333333 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30698.072832 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30698.072832 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27077.282858 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27077.282858 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -659,155 +652,155 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 8243774 # number of writebacks -system.cpu.dcache.writebacks::total 8243774 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 770626 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 770626 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1821654 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1821654 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 153 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 153 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 68982 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 68982 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2592280 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2592280 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2592280 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2592280 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5600096 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5600096 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2309050 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2309050 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1391260 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1391260 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1238666 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1238666 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 241218 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 241218 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 7909146 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 7909146 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9300406 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9300406 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 8326510 # number of writebacks +system.cpu.dcache.writebacks::total 8326510 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 781266 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 781266 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1841490 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1841490 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 148 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 148 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69021 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 69021 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2622756 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2622756 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2622756 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2622756 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5654697 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5654697 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2336620 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2336620 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1411789 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1411789 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1240093 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1240093 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 241567 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 241567 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 3 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 7991317 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 7991317 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9403106 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9403106 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 96067975500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 96067975500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 106000226500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 106000226500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26589323500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26589323500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 83310681500 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 83310681500 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3491728500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3491728500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 202068202000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 202068202000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 228657525500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 228657525500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197287500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197287500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6207449000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6207449000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12404736500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 12404736500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032861 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032861 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015223 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015223 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.727967 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.727967 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786615 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786615 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057917 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057917 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024555 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024555 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028704 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028704 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17154.701544 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17154.701544 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45906.423204 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45906.423204 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19111.685451 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19111.685451 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 67258.390478 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 67258.390478 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14475.406064 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14475.406064 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25548.675167 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25548.675167 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24585.757385 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24585.757385 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183912.143514 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183912.143514 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184164.510770 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184164.510770 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184038.343991 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184038.343991 # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 97635804500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 97635804500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109449194500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 109449194500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26743318000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26743318000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 52153246000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 52153246000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3514198000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3514198000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 242500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 242500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207084999000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 207084999000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 233828317000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 233828317000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197367000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197367000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6207571500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6207571500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12404938500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 12404938500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032922 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032922 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015272 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015272 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.729568 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.729568 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786614 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786614 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057346 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057346 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024607 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024607 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028782 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028782 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17266.319398 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17266.319398 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46840.819004 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46840.819004 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18942.857608 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18942.857608 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 42055.915161 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 42055.915161 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14547.508559 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14547.508559 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80833.333333 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80833.333333 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25913.751013 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25913.751013 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24867.136136 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24867.136136 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183914.502775 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183914.502775 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184168.145137 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184168.145137 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184041.340890 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184041.340890 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 24176986 # number of replacements -system.cpu.icache.tags.tagsinuse 511.872408 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 414546703 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24177498 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.145972 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 39504620500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.872408 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999751 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999751 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 24282731 # number of replacements +system.cpu.icache.tags.tagsinuse 511.885324 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 418496927 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24283243 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.233980 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 32778398500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.885324 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999776 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999776 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 462901718 # Number of tag accesses -system.cpu.icache.tags.data_accesses 462901718 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 414546703 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 414546703 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 414546703 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 414546703 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 414546703 # number of overall hits -system.cpu.icache.overall_hits::total 414546703 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 24177508 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 24177508 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 24177508 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 24177508 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 24177508 # number of overall misses -system.cpu.icache.overall_misses::total 24177508 # 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number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 442780180 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 442780180 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 442780180 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 442780180 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054843 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.054843 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.054843 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.054843 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.054843 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.054843 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13553.630397 # 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number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 24283253 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 24283253 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 24283253 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 24283253 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303422579000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 303422579000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303422579000 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7867.228358 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 19562.014919 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.565520 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004933 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006095 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.120044 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.298493 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995085 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 237 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 63396 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 236 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 513 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2438 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5534 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54861 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003616 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.967346 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 573646968 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 573646968 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 914477 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 280144 # 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mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.274155 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.274155 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004433 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004433 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043440 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043440 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.428844 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.428844 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.005938 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.016214 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004433 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.098396 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.030147 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.005938 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.016214 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004433 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.098396 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.030147 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127444.169870 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126572.233052 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127044.791667 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68012.494333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68012.494333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122649.023309 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122649.023309 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122367.838615 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122367.838615 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124789.860331 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124789.860331 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128850.667834 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128850.667834 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127444.169870 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126572.233052 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122367.838615 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123369.027344 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123302.213926 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127444.169870 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126572.233052 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122367.838615 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123369.027344 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123302.213926 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.281746 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.281746 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004458 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004458 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043831 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043831 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.432301 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.432301 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006266 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.017228 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004458 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.100566 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.030880 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006266 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.017228 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004458 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.100566 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.030880 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127309.414758 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126926.900000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127133.868747 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68015.362686 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68015.362686 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69333.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69333.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122751.847678 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122751.847678 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122519.268728 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122519.268728 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125017.660953 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125017.660953 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69662.957429 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69662.957429 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127309.414758 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126926.900000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122519.268728 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123503.885757 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123442.045334 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127309.414758 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126926.900000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122519.268728 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123503.885757 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123442.045334 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171410.437131 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136177.609702 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172646.576277 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172646.576277 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171412.648010 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136178.475920 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172650.477660 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172650.477660 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172028.589232 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146445.778201 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172031.645476 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146447.498998 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 70561172 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 35651281 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4392 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2272 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2272 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 70987580 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 35868028 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4400 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2259 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2259 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 1729330 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 33139930 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 1747427 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 33339280 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 9609467 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 24176986 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2728127 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 47900 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 47901 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2261407 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2261407 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 24177508 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7241194 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1345330 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1238666 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72636616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32428005 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 687897 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2160128 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 107912646 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3098035136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1135439954 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2278088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7359520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 4243112698 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2160696 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 38442129 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018241 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.133822 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 9726418 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 24282731 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2753122 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 48457 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 48460 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2288395 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2288395 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 24283253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7316706 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1346757 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1240093 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72953851 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32740884 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 695726 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2196697 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 108587158 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3111570496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1147294802 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2321736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7526280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 4268713314 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2190531 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 38708484 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018284 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.133976 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 37740909 98.18% 98.18% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 701220 1.82% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 38000745 98.17% 98.17% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 707739 1.83% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 38442129 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 68252447493 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 38708484 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 68659919994 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1464392 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1469394 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 36351871671 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 36510728693 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14935181922 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 15090009225 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 403175920 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 405546924 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1240232910 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1255965393 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40322 # Transaction distribution -system.iobus.trans_dist::ReadResp 40322 # Transaction distribution +system.iobus.trans_dist::ReadReq 40330 # Transaction distribution +system.iobus.trans_dist::ReadResp 40330 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1264,11 +1256,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231002 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231002 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231018 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231018 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353786 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353802 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1283,16 +1275,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334440 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334440 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334504 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334504 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492360 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42165000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492424 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42214500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 332500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 333500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1306,77 +1298,77 @@ system.iobus.reqLayer14.occupancy 9500 # La system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25683500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25698500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 34144500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 34147500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 567247076 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 566993946 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147762000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147778000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115483 # number of replacements -system.iocache.tags.tagsinuse 10.440004 # Cycle average of tags in use +system.iocache.tags.replacements 115490 # number of replacements +system.iocache.tags.tagsinuse 10.441254 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115499 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115506 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13160148727000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.520843 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.919161 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.220053 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.432448 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.652500 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13153331095000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.521304 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.919950 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.220081 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.432497 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652578 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039866 # Number of tag accesses -system.iocache.tags.data_accesses 1039866 # Number of data accesses +system.iocache.tags.tag_accesses 1039938 # Number of tag accesses +system.iocache.tags.data_accesses 1039938 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8837 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8874 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8845 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8882 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8837 # number of demand (read+write) misses -system.iocache.demand_misses::total 8877 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8845 # number of demand (read+write) misses +system.iocache.demand_misses::total 8885 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8837 # number of overall misses -system.iocache.overall_misses::total 8877 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5069500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1647976559 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1653046059 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8845 # number of overall misses +system.iocache.overall_misses::total 8885 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1624796190 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1629882190 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13408898017 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13408898017 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5420500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1647976559 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1653397059 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5420500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1647976559 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1653397059 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13412464756 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13412464756 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1624796190 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1630233190 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1624796190 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1630233190 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8837 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8874 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8845 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8882 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8837 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8877 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8845 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8885 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8837 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8877 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8845 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8885 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1390,55 +1382,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 186485.974765 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 186279.700135 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 183696.573205 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 183503.961946 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125711.561698 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125711.561698 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 186485.974765 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 186256.286921 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 186485.974765 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 186256.286921 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33362 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125745.000713 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125745.000713 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 183696.573205 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183481.507034 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 183696.573205 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183481.507034 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31904 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3432 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3290 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.720862 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.697264 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106631 # number of writebacks -system.iocache.writebacks::total 106631 # number of writebacks +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8837 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8845 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8882 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8837 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8877 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8845 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8885 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8837 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8877 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1206126559 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1209346059 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8845 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8885 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1182546190 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1185782190 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8070540171 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8070540171 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3420500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1206126559 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1209547059 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3420500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1206126559 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1209547059 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8074127324 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8074127324 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1182546190 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1185983190 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1182546190 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1185983190 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1452,72 +1444,72 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136485.974765 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 136279.700135 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133696.573205 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 133503.961946 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75663.205683 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75663.205683 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 136485.974765 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 136256.286921 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 136485.974765 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 136256.286921 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75696.836083 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75696.836083 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 133696.573205 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 133481.507034 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 133696.573205 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 133481.507034 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 86006 # Transaction distribution -system.membus.trans_dist::ReadResp 526304 # Transaction distribution +system.membus.trans_dist::ReadResp 534352 # Transaction distribution system.membus.trans_dist::WriteReq 33706 # Transaction distribution system.membus.trans_dist::WriteResp 33706 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1365657 # Transaction distribution -system.membus.trans_dist::CleanEvict 238956 # Transaction distribution -system.membus.trans_dist::UpgradeReq 38308 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 1150364 # Transaction distribution -system.membus.trans_dist::ReadExResp 1150364 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 440298 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1399859 # Transaction distribution +system.membus.trans_dist::CleanEvict 242769 # Transaction distribution +system.membus.trans_dist::UpgradeReq 38707 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 644117 # Transaction distribution +system.membus.trans_dist::ReadExResp 644117 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 448346 # Transaction distribution +system.membus.trans_dist::InvalidateReq 642566 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4800126 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4929778 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237399 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237399 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5167177 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4378022 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4507674 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237045 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237045 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4744719 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 185137772 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 185308178 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7232384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7232384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 192540562 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3164 # Total snoops (count) -system.membus.snoop_fanout::samples 3459998 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 155441452 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 155611858 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7208704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7208704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 162820562 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3543 # Total snoops (count) +system.membus.snoop_fanout::samples 3536130 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3459998 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3536130 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3459998 # Request fanout histogram -system.membus.reqLayer0.occupancy 102421000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3536130 # Request fanout histogram +system.membus.reqLayer0.occupancy 102490000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5498500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5501500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9252697708 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9311720798 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8691723530 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6129482304 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44915426 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44955070 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt index d62e25962..4faaeac69 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt @@ -1,141 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.331525 # Number of seconds simulated -sim_ticks 51331524771000 # Number of ticks simulated -final_tick 51331524771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.327140 # Number of seconds simulated +sim_ticks 51327140089000 # Number of ticks simulated +final_tick 51327140089000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146792 # Simulator instruction rate (inst/s) -host_op_rate 172478 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8901142339 # Simulator tick rate (ticks/s) -host_mem_usage 687432 # Number of bytes of host memory used -host_seconds 5766.85 # Real time elapsed on the host -sim_insts 846524467 # Number of instructions simulated -sim_ops 994654061 # Number of ops (including micro ops) simulated +host_inst_rate 155840 # Simulator instruction rate (inst/s) +host_op_rate 183117 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9430836418 # Simulator tick rate (ticks/s) +host_mem_usage 687516 # Number of bytes of host memory used +host_seconds 5442.48 # Real time elapsed on the host +sim_insts 848158120 # Number of instructions simulated +sim_ops 996609834 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 205568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 197440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5696288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 72187912 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 428288 # Number of bytes read from this memory -system.physmem.bytes_read::total 78715496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5696288 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5696288 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67280640 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 211968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 207872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5637664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 41611720 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 447104 # Number of bytes read from this memory +system.physmem.bytes_read::total 48116328 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5637664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5637664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 68318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 67301220 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3212 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3085 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 104957 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1127949 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6692 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1245895 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1051260 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 68338916 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3312 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3248 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 104041 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 650196 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6986 # Number of read requests responded to by this memory +system.physmem.num_reads::total 767783 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1067474 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1053833 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 4005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 3846 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 110971 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1406308 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1533473 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 110971 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 110971 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1310708 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1070047 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 4130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 4050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 109838 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 810716 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 937444 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 109838 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 109838 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1331037 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1311109 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1310708 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 3846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 110971 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1406708 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2844582 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1245895 # Number of read requests accepted -system.physmem.writeReqs 1053833 # Number of write requests accepted -system.physmem.readBursts 1245895 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1053833 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 79684928 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 52352 # Total number of bytes read from write queue -system.physmem.bytesWritten 67299776 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 78715496 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 67301220 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 818 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1331438 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1331037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4130 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 4050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 109838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 811117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2268882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 767783 # Number of read requests accepted +system.physmem.writeReqs 1070047 # Number of write requests accepted +system.physmem.readBursts 767783 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1070047 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 49097152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 40960 # Total number of bytes read from write queue +system.physmem.bytesWritten 68336896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 48116328 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 68338916 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 640 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2264 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 74822 # Per bank write bursts -system.physmem.perBankRdBursts::1 82180 # Per bank write bursts -system.physmem.perBankRdBursts::2 80987 # Per bank write bursts -system.physmem.perBankRdBursts::3 75462 # Per bank write bursts -system.physmem.perBankRdBursts::4 75477 # Per bank write bursts -system.physmem.perBankRdBursts::5 80130 # Per bank write bursts -system.physmem.perBankRdBursts::6 74577 # Per bank write bursts -system.physmem.perBankRdBursts::7 72890 # Per bank write bursts -system.physmem.perBankRdBursts::8 72311 # Per bank write bursts -system.physmem.perBankRdBursts::9 102827 # Per bank write bursts -system.physmem.perBankRdBursts::10 78128 # Per bank write bursts -system.physmem.perBankRdBursts::11 79408 # Per bank write bursts -system.physmem.perBankRdBursts::12 72963 # Per bank write bursts -system.physmem.perBankRdBursts::13 76387 # Per bank write bursts -system.physmem.perBankRdBursts::14 73944 # Per bank write bursts -system.physmem.perBankRdBursts::15 72584 # Per bank write bursts -system.physmem.perBankWrBursts::0 62047 # Per bank write bursts -system.physmem.perBankWrBursts::1 68427 # Per bank write bursts -system.physmem.perBankWrBursts::2 68519 # Per bank write bursts -system.physmem.perBankWrBursts::3 66050 # Per bank write bursts -system.physmem.perBankWrBursts::4 65357 # Per bank write bursts -system.physmem.perBankWrBursts::5 67435 # Per bank write bursts -system.physmem.perBankWrBursts::6 63960 # Per bank write bursts -system.physmem.perBankWrBursts::7 63937 # Per bank write bursts -system.physmem.perBankWrBursts::8 63039 # Per bank write bursts -system.physmem.perBankWrBursts::9 70105 # Per bank write bursts -system.physmem.perBankWrBursts::10 66227 # Per bank write bursts -system.physmem.perBankWrBursts::11 68082 # Per bank write bursts -system.physmem.perBankWrBursts::12 64306 # Per bank write bursts -system.physmem.perBankWrBursts::13 66291 # Per bank write bursts -system.physmem.perBankWrBursts::14 64522 # Per bank write bursts -system.physmem.perBankWrBursts::15 63255 # Per bank write bursts +system.physmem.perBankRdBursts::0 44980 # Per bank write bursts +system.physmem.perBankRdBursts::1 51602 # Per bank write bursts +system.physmem.perBankRdBursts::2 47368 # Per bank write bursts +system.physmem.perBankRdBursts::3 43602 # Per bank write bursts +system.physmem.perBankRdBursts::4 45132 # Per bank write bursts +system.physmem.perBankRdBursts::5 50541 # Per bank write bursts +system.physmem.perBankRdBursts::6 45264 # Per bank write bursts +system.physmem.perBankRdBursts::7 48215 # Per bank write bursts +system.physmem.perBankRdBursts::8 45181 # Per bank write bursts +system.physmem.perBankRdBursts::9 71916 # Per bank write bursts +system.physmem.perBankRdBursts::10 43746 # Per bank write bursts +system.physmem.perBankRdBursts::11 51986 # Per bank write bursts +system.physmem.perBankRdBursts::12 43936 # Per bank write bursts +system.physmem.perBankRdBursts::13 46943 # Per bank write bursts +system.physmem.perBankRdBursts::14 42923 # Per bank write bursts +system.physmem.perBankRdBursts::15 43808 # Per bank write bursts +system.physmem.perBankWrBursts::0 64378 # Per bank write bursts +system.physmem.perBankWrBursts::1 68822 # Per bank write bursts +system.physmem.perBankWrBursts::2 67360 # Per bank write bursts +system.physmem.perBankWrBursts::3 65401 # Per bank write bursts +system.physmem.perBankWrBursts::4 67058 # Per bank write bursts +system.physmem.perBankWrBursts::5 69359 # Per bank write bursts +system.physmem.perBankWrBursts::6 64813 # Per bank write bursts +system.physmem.perBankWrBursts::7 68136 # Per bank write bursts +system.physmem.perBankWrBursts::8 65855 # Per bank write bursts +system.physmem.perBankWrBursts::9 70723 # Per bank write bursts +system.physmem.perBankWrBursts::10 64194 # Per bank write bursts +system.physmem.perBankWrBursts::11 71056 # Per bank write bursts +system.physmem.perBankWrBursts::12 64787 # Per bank write bursts +system.physmem.perBankWrBursts::13 67120 # Per bank write bursts +system.physmem.perBankWrBursts::14 64460 # Per bank write bursts +system.physmem.perBankWrBursts::15 64242 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 38 # Number of times write queue was full causing retry -system.physmem.totGap 51331523357500 # Total gap between requests +system.physmem.numWrRetry 33 # Number of times write queue was full causing retry +system.physmem.totGap 51327138675500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1224610 # Read request sizes (log2) +system.physmem.readPktSize::6 746498 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1051260 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 635913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 326498 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 150136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 126962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 653 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 332 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 170 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 71 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1067474 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 514277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 203743 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 584 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 567 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1290 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 814 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 357 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 141 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 138 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -159,168 +159,168 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 11720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 15352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 33279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 54389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 62052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 63406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 64510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 63581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 65005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 68339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 65443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 80751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 86913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 66052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 69586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 62814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 93 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 477001 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 308.142583 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 177.284446 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 336.100691 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 186993 39.20% 39.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 111432 23.36% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 45372 9.51% 72.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23464 4.92% 76.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18197 3.81% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11652 2.44% 83.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10522 2.21% 85.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8218 1.72% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 61151 12.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 477001 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59594 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.891952 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 270.280066 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 59591 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59594 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59594 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.645384 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.994879 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.954134 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 56960 95.58% 95.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 905 1.52% 97.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 37 0.06% 97.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 115 0.19% 97.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 18 0.03% 97.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 110 0.18% 97.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 195 0.33% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 24 0.04% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 355 0.60% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 71 0.12% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 24 0.04% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 56 0.09% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 280 0.47% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 26 0.04% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 33 0.06% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 125 0.21% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 203 0.34% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 8 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 11 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::15 26644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 32364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 54414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 60551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 69991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 63900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 76806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 64795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 68451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 60364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 58974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 57166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 80 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 471185 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 249.230345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 149.487407 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 290.645433 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 207601 44.06% 44.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 122052 25.90% 69.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 43152 9.16% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 22522 4.78% 83.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14798 3.14% 87.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9568 2.03% 89.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7612 1.62% 90.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6084 1.29% 91.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 37796 8.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 471185 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 54136 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.170570 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 76.787361 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 54130 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 54136 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 54136 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.723733 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.769647 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.988954 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 40635 75.06% 75.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 4496 8.31% 83.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 5195 9.60% 92.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1325 2.45% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 409 0.76% 96.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 232 0.43% 96.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 326 0.60% 97.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 142 0.26% 97.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 398 0.74% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 127 0.23% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 56 0.10% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 67 0.12% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 319 0.59% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 37 0.07% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 24 0.04% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 111 0.21% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 168 0.31% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 5 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 17 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59594 # Writes before turning the bus around for reads -system.physmem.totQLat 31834686171 # Total ticks spent queuing -system.physmem.totMemAccLat 55179879921 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6225385000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25568.45 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 54136 # Writes before turning the bus around for reads +system.physmem.totQLat 15242803686 # Total ticks spent queuing +system.physmem.totMemAccLat 29626734936 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3835715000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19869.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44318.45 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.55 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.31 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.53 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.31 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38619.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.96 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.33 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.33 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.63 # Average write queue length when enqueuing -system.physmem.readRowHits 1023243 # Number of row buffer hits during reads -system.physmem.writeRowHits 796390 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.73 # Row buffer hit rate for writes -system.physmem.avgGap 22320693.30 # Average gap between requests -system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1817907840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 991914000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4808848200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3406743360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3352725536160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1236862065645 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29713947077250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34314560092455 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.489031 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49431665045810 # Time in different power states -system.physmem_0.memoryStateTime::REF 1714072360000 # Time in different power states +system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.33 # Average write queue length when enqueuing +system.physmem.readRowHits 579803 # Number of row buffer hits during reads +system.physmem.writeRowHits 783916 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.42 # Row buffer hit rate for writes +system.physmem.avgGap 27928121.03 # Average gap between requests +system.physmem.pageHitRate 74.32 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1791077400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 977274375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2938244400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3468841200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1235175473835 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29712796340250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34309586468340 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.449224 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49429866192554 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713925980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 185786732190 # Time in different power states +system.physmem_0.memoryStateTime::ACT 183347171196 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1788219720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 975715125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4902705600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3407358960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3352725536160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1238749464465 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29712291456000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34314840456030 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.494493 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49428877758086 # Time in different power states -system.physmem_1.memoryStateTime::REF 1714072360000 # Time in different power states +system.physmem_1.actEnergy 1771020720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 966330750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3045424200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3450165840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1235608843410 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29712416191500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34309697193300 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.451381 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49429214230967 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713925980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 188572884414 # Time in different power states +system.physmem_1.memoryStateTime::ACT 183999255033 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -344,15 +344,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 223870317 # Number of BP lookups -system.cpu.branchPred.condPredicted 149571742 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12183866 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157933845 # Number of BTB lookups -system.cpu.branchPred.BTBHits 103250874 # Number of BTB hits +system.cpu.branchPred.lookups 224297572 # Number of BP lookups +system.cpu.branchPred.condPredicted 149902957 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12193787 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 158452721 # Number of BTB lookups +system.cpu.branchPred.BTBHits 103491021 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.376028 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 30780710 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 342883 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.313502 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 30817326 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 343319 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -383,45 +383,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.walks 196101 # Table walker walks requested -system.cpu.checker.dtb.walker.walksLong 196101 # Table walker walks initiated with long descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 196101 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 196101 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 196101 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walks 197812 # Table walker walks requested +system.cpu.checker.dtb.walker.walksLong 197812 # Table walker walks initiated with long descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 197812 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 197812 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 197812 # Table walker wait (enqueue to first request) latency system.cpu.checker.dtb.walker.walksPending::samples -1584953796 # Table walker pending requests distribution system.cpu.checker.dtb.walker.walksPending::0 -1584953796 100.00% 100.00% # Table walker pending requests distribution system.cpu.checker.dtb.walker.walksPending::total -1584953796 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 153300 91.91% 91.91% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::2M 13495 8.09% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 166795 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 196101 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkPageSizes::4K 154082 91.53% 91.53% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::2M 14256 8.47% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 168338 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 197812 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 196101 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 166795 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 197812 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 168338 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 166795 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 362896 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 168338 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 366150 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 159296881 # DTB read hits -system.cpu.checker.dtb.read_misses 146556 # DTB read misses -system.cpu.checker.dtb.write_hits 144479663 # DTB write hits -system.cpu.checker.dtb.write_misses 49545 # DTB write misses +system.cpu.checker.dtb.read_hits 159555068 # DTB read hits +system.cpu.checker.dtb.read_misses 147115 # DTB read misses +system.cpu.checker.dtb.write_hits 144752666 # DTB write hits +system.cpu.checker.dtb.write_misses 50697 # DTB write misses system.cpu.checker.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 78302 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 2034 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 71585 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dtb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID +system.cpu.checker.dtb.flush_entries 71773 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 7067 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 6971 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 18958 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 159443437 # DTB read accesses -system.cpu.checker.dtb.write_accesses 144529208 # DTB write accesses +system.cpu.checker.dtb.perms_faults 19053 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dtb.read_accesses 159702183 # DTB read accesses +system.cpu.checker.dtb.write_accesses 144803363 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 303776544 # DTB hits -system.cpu.checker.dtb.misses 196101 # DTB misses -system.cpu.checker.dtb.accesses 303972645 # DTB accesses +system.cpu.checker.dtb.hits 304307734 # DTB hits +system.cpu.checker.dtb.misses 197812 # DTB misses +system.cpu.checker.dtb.accesses 304505546 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -451,46 +451,46 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.walks 119784 # Table walker walks requested -system.cpu.checker.itb.walker.walksLong 119784 # Table walker walks initiated with long descriptors -system.cpu.checker.itb.walker.walkWaitTime::samples 119784 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::0 119784 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::total 119784 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walks 119797 # Table walker walks requested +system.cpu.checker.itb.walker.walksLong 119797 # Table walker walks initiated with long descriptors +system.cpu.checker.itb.walker.walkWaitTime::samples 119797 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::0 119797 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::total 119797 # Table walker wait (enqueue to first request) latency system.cpu.checker.itb.walker.walksPending::samples -1586149296 # Table walker pending requests distribution system.cpu.checker.itb.walker.walksPending::0 -1586149296 100.00% 100.00% # Table walker pending requests distribution system.cpu.checker.itb.walker.walksPending::total -1586149296 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walkPageSizes::4K 107945 98.82% 98.82% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::2M 1286 1.18% 100.00% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::total 109231 # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::4K 107938 98.83% 98.83% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::2M 1280 1.17% 100.00% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::total 109218 # Table walker page sizes translated system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 119784 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 119784 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 119797 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 119797 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109231 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109231 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109218 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109218 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin::total 229015 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 846929544 # ITB inst hits -system.cpu.checker.itb.inst_misses 119784 # ITB inst misses +system.cpu.checker.itb.inst_hits 848564500 # ITB inst hits +system.cpu.checker.itb.inst_misses 119797 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses system.cpu.checker.itb.write_hits 0 # DTB write hits system.cpu.checker.itb.write_misses 0 # DTB write misses system.cpu.checker.itb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 78302 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 2034 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 51594 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.itb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID +system.cpu.checker.itb.flush_entries 51743 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 847049328 # ITB inst accesses -system.cpu.checker.itb.hits 846929544 # DTB hits -system.cpu.checker.itb.misses 119784 # DTB misses -system.cpu.checker.itb.accesses 847049328 # DTB accesses -system.cpu.checker.numCycles 995222047 # number of cpu cycles simulated +system.cpu.checker.itb.inst_accesses 848684297 # ITB inst accesses +system.cpu.checker.itb.hits 848564500 # DTB hits +system.cpu.checker.itb.misses 119797 # DTB misses +system.cpu.checker.itb.accesses 848684297 # DTB accesses +system.cpu.checker.numCycles 997179136 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -522,85 +522,85 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 937088 # Table walker walks requested -system.cpu.dtb.walker.walksLong 937088 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15029 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 154587 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 427394 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 509694 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2223.932399 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 14616.246492 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 506310 99.34% 99.34% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 1920 0.38% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 988 0.19% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 199 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 148 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 28 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 46 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 49 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 509694 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 474748 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 23018.407660 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 18045.301329 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 20477.097679 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 463839 97.70% 97.70% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 7714 1.62% 99.33% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 2286 0.48% 99.81% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 175 0.04% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 504 0.11% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 86 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 94 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 30 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 8 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 474748 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 784053971876 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.725342 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.519550 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 781854829876 99.72% 99.72% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 1175747000 0.15% 99.87% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 476309500 0.06% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 200437500 0.03% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 146602500 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 120332500 0.02% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 25999000 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 51086000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2628000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 784053971876 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 154588 91.14% 91.14% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 15029 8.86% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 169617 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 937088 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 949838 # Table walker walks requested +system.cpu.dtb.walker.walksLong 949838 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15818 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155419 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 436827 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 513011 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2225.817770 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 14567.134273 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 509618 99.34% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 1930 0.38% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 987 0.19% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 197 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 149 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 32 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 53 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 41 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 513011 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 485512 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 23036.801356 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 18084.539614 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 20755.830536 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 474265 97.68% 97.68% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 7843 1.62% 99.30% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 2427 0.50% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 166 0.03% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 551 0.11% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 105 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 109 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 26 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 485512 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 779669132376 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.722626 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.523315 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 777439658376 99.71% 99.71% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 1176099000 0.15% 99.86% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 488850000 0.06% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 205535000 0.03% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 152105500 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 121751500 0.02% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 29187500 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 53249500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2696000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 779669132376 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 155420 90.76% 90.76% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 15818 9.24% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 171238 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 949838 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 937088 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 169617 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 949838 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171238 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 169617 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1106705 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171238 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1121076 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 169133397 # DTB read hits -system.cpu.dtb.read_misses 670096 # DTB read misses -system.cpu.dtb.write_hits 147221017 # DTB write hits -system.cpu.dtb.write_misses 266992 # DTB write misses +system.cpu.dtb.read_hits 169331819 # DTB read hits +system.cpu.dtb.read_misses 674131 # DTB read misses +system.cpu.dtb.write_hits 147501461 # DTB write hits +system.cpu.dtb.write_misses 275707 # DTB write misses system.cpu.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 78302 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 2034 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 71818 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 99 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9972 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 72020 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 117 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 10130 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 69741 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 169803493 # DTB read accesses -system.cpu.dtb.write_accesses 147488009 # DTB write accesses +system.cpu.dtb.perms_faults 69829 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 170005950 # DTB read accesses +system.cpu.dtb.write_accesses 147777168 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 316354414 # DTB hits -system.cpu.dtb.misses 937088 # DTB misses -system.cpu.dtb.accesses 317291502 # DTB accesses +system.cpu.dtb.hits 316833280 # DTB hits +system.cpu.dtb.misses 949838 # DTB misses +system.cpu.dtb.accesses 317783118 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -630,328 +630,325 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 160983 # Table walker walks requested -system.cpu.itb.walker.walksLong 160983 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1438 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 121478 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17520 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 143463 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1273.722144 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 9463.659088 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 142472 99.31% 99.31% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 574 0.40% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 44 0.03% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 82 0.06% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 231 0.16% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 26 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 161333 # Table walker walks requested +system.cpu.itb.walker.walksLong 161333 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1433 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 121604 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 17607 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 143726 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1329.870726 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 9693.373994 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 142645 99.25% 99.25% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 592 0.41% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 67 0.05% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 93 0.06% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 270 0.19% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 24 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::262144-294911 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::294912-327679 5 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::393216-425983 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 143463 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 140436 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 29061.341109 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24320.215707 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 22395.663440 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 137485 97.90% 97.90% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 845 0.60% 98.50% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 1830 1.30% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 92 0.07% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 113 0.08% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 31 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 34 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkWaitTime::294912-327679 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::360448-393215 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 143726 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 140644 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 29101.756918 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24236.740283 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 22905.442201 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 137486 97.75% 97.75% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 886 0.63% 98.38% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 1961 1.39% 99.78% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 124 0.09% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 124 0.09% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 33 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 20 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 140436 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 672381692680 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.944059 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.230149 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 37665306856 5.60% 5.60% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 634665708824 94.39% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 49644500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 1013500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 19000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 672381692680 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 121478 98.83% 98.83% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1438 1.17% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 122916 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 140644 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 672291747976 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.944017 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.230261 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 37693655356 5.61% 5.61% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 634541752620 94.38% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 55651000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 688000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 1000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 672291747976 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 121604 98.84% 98.84% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1433 1.16% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 123037 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 160983 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 160983 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161333 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 161333 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 122916 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 122916 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 283899 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 355891670 # ITB inst hits -system.cpu.itb.inst_misses 160983 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123037 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 123037 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 284370 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 356599136 # ITB inst hits +system.cpu.itb.inst_misses 161333 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 78302 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 2034 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 52900 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53042 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 368990 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 369633 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 356052653 # ITB inst accesses -system.cpu.itb.hits 355891670 # DTB hits -system.cpu.itb.misses 160983 # DTB misses -system.cpu.itb.accesses 356052653 # DTB accesses -system.cpu.numCycles 1641618102 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 356760469 # ITB inst accesses +system.cpu.itb.hits 356599136 # DTB hits +system.cpu.itb.misses 161333 # DTB misses +system.cpu.itb.accesses 356760469 # DTB accesses +system.cpu.numCycles 1628081885 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 643295277 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 998912988 # Number of instructions fetch has processed -system.cpu.fetch.Branches 223870317 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 134031584 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 911548920 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26021190 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3814569 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 28072 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9294541 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1045994 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 928 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 355505947 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6091455 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 48555 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1582038896 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.739816 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.145969 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 644023121 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1000825975 # Number of instructions fetch has processed +system.cpu.fetch.Branches 224297572 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 134308347 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 897356081 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26042356 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3815311 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 27434 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9297529 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1037208 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 977 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 356212596 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6096332 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 48851 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1568578839 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.747604 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.149571 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1026150412 64.86% 64.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 213368743 13.49% 78.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70509493 4.46% 82.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 272010248 17.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1011708684 64.50% 64.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 213717515 13.62% 78.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 70499052 4.49% 82.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 272653588 17.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1582038896 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.136372 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.608493 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 523526038 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 567332242 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 432225078 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 49743606 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9211932 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33585206 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3858658 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1082487330 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 28953315 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9211932 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 568013928 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 68659821 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 370106883 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 437449183 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 128597149 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1062778939 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6765759 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 5100330 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 330196 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 669001 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 77613497 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 20248 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1010589647 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1636490834 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1256895335 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1474103 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 945145868 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 65443776 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 26770566 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23114475 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 102068123 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 173157157 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 150776419 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9868164 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9014634 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1027918827 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27065451 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1043272281 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3272960 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60330213 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33600804 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 313388 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1582038896 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.659448 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.917899 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1568578839 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.137768 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.614727 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 523834599 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 552751170 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 433009950 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 49764409 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9218711 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33629126 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3862659 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1084582874 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 28977480 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9218711 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 568372766 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 66217937 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 371830406 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 438295981 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 114643038 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1064838864 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6775021 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 5115924 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 336846 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 638712 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 63601510 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 20546 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1012729668 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1640391275 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1259385666 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1476745 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 947192806 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 65536859 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 26910765 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23247835 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 101832167 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 173436334 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 151069277 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9864131 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8951241 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1029826470 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27204925 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1045231227 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3279121 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60421557 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33664917 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 313528 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1568578839 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.666356 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.920348 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 936232713 59.18% 59.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 333194737 21.06% 80.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234236353 14.81% 95.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 71914703 4.55% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6441221 0.41% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19169 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 921654762 58.76% 58.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 333747896 21.28% 80.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234544221 14.95% 94.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72152324 4.60% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6460263 0.41% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19373 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1582038896 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1568578839 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57633129 35.05% 35.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 100179 0.06% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26746 0.02% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 783 0.00% 35.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44218992 26.89% 62.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 62461837 37.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 57742950 35.03% 35.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 99825 0.06% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26740 0.02% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 625 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44231739 26.83% 61.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 62727458 38.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 21 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 718385578 68.86% 68.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2533352 0.24% 69.10% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 122770 0.01% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 382 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 121248 0.01% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 173007895 16.58% 85.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 149100989 14.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 719843938 68.87% 68.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2535420 0.24% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 122954 0.01% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 380 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 121377 0.01% 69.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 173211987 16.57% 85.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 149395124 14.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1043272281 # Type of FU issued -system.cpu.iq.rate 0.635515 # Inst issue rate -system.cpu.iq.fu_busy_cnt 164441666 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157621 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3833820592 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1114508942 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1025374913 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2477491 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 947894 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 909947 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1206157308 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1556618 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4301219 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1045231227 # Type of FU issued +system.cpu.iq.rate 0.642002 # Inst issue rate +system.cpu.iq.fu_busy_cnt 164829337 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157697 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3824665950 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1116644145 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1027372601 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2483800 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 950168 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 912054 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1208499896 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1560667 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4304106 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13765356 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14482 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 143653 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6293913 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13785862 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14456 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 142604 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6312817 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2526650 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1543650 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2532139 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1442341 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9211932 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6884950 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9078435 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1055205514 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9218711 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 7060342 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6923682 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1057253447 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 173157157 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 150776419 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22691259 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 56491 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8949926 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 143653 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3653003 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5096400 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8749403 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1032130630 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 169121119 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10215406 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 173436334 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 151069277 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22822922 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 57401 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6792645 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 142604 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3655399 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5100784 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8756183 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1034064574 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 169319677 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10227871 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221236 # number of nop insts executed -system.cpu.iew.exec_refs 316337352 # number of memory reference insts executed -system.cpu.iew.exec_branches 195829859 # Number of branches executed -system.cpu.iew.exec_stores 147216233 # Number of stores executed -system.cpu.iew.exec_rate 0.628728 # Inst execution rate -system.cpu.iew.wb_sent 1027090277 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1026284860 # cumulative count of insts written-back -system.cpu.iew.wb_producers 436833707 # num instructions producing a value -system.cpu.iew.wb_consumers 706462159 # num instructions consuming a value -system.cpu.iew.wb_rate 0.625167 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.618340 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 51246502 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 26752063 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8385203 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1570087734 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.633502 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.269814 # Number of insts commited each cycle +system.cpu.iew.exec_nop 222052 # number of nop insts executed +system.cpu.iew.exec_refs 316816486 # number of memory reference insts executed +system.cpu.iew.exec_branches 196206176 # Number of branches executed +system.cpu.iew.exec_stores 147496809 # Number of stores executed +system.cpu.iew.exec_rate 0.635143 # Inst execution rate +system.cpu.iew.wb_sent 1029092840 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1028284655 # cumulative count of insts written-back +system.cpu.iew.wb_producers 437786008 # num instructions producing a value +system.cpu.iew.wb_consumers 708231099 # num instructions consuming a value +system.cpu.iew.wb_rate 0.631593 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.618140 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 51332329 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 26891397 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8391320 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1556613982 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.640242 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.274821 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1059518127 67.48% 67.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 287046411 18.28% 85.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 120236472 7.66% 93.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36451838 2.32% 95.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28385212 1.81% 97.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13987217 0.89% 98.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8615612 0.55% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4166173 0.27% 99.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11680672 0.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1044975044 67.13% 67.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 287768132 18.49% 85.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 120346121 7.73% 93.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36551788 2.35% 95.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28453995 1.83% 97.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14010396 0.90% 98.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8635881 0.55% 98.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4170150 0.27% 99.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11702475 0.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1570087734 # Number of insts commited each cycle -system.cpu.commit.committedInsts 846524467 # Number of instructions committed -system.cpu.commit.committedOps 994654061 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1556613982 # Number of insts commited each cycle +system.cpu.commit.committedInsts 848158120 # Number of instructions committed +system.cpu.commit.committedOps 996609834 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 303874306 # Number of memory references committed -system.cpu.commit.loads 159391800 # Number of loads committed -system.cpu.commit.membars 6909679 # Number of memory barriers committed -system.cpu.commit.branches 188935778 # Number of branches committed -system.cpu.commit.fp_insts 896706 # Number of committed floating point instructions. -system.cpu.commit.int_insts 913907111 # Number of committed integer instructions. -system.cpu.commit.function_calls 25250179 # Number of function calls committed. +system.cpu.commit.refs 304406931 # Number of memory references committed +system.cpu.commit.loads 159650471 # Number of loads committed +system.cpu.commit.membars 6926449 # Number of memory barriers committed +system.cpu.commit.branches 189300112 # Number of branches committed +system.cpu.commit.fp_insts 898776 # Number of committed floating point instructions. +system.cpu.commit.int_insts 915651780 # Number of committed integer instructions. +system.cpu.commit.function_calls 25280403 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 688421836 69.21% 69.21% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2147861 0.22% 69.43% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98019 0.01% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 689842559 69.22% 69.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2150231 0.22% 69.43% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98139 0.01% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction @@ -974,540 +971,541 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.44% # system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 111997 0.01% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 159391800 16.02% 85.47% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 144482506 14.53% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 111932 0.01% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 159650471 16.02% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 144756460 14.52% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 994654061 # Class of committed instruction -system.cpu.commit.bw_lim_events 11680672 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2596784081 # The number of ROB reads -system.cpu.rob.rob_writes 2103659595 # The number of ROB writes -system.cpu.timesIdled 8144337 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59579206 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101021431570 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 846524467 # Number of Instructions Simulated -system.cpu.committedOps 994654061 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.939245 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.939245 # CPI: Total CPI of All Threads -system.cpu.ipc 0.515665 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.515665 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1221742987 # number of integer regfile reads -system.cpu.int_regfile_writes 729786547 # number of integer regfile writes -system.cpu.fp_regfile_reads 1462559 # number of floating regfile reads -system.cpu.fp_regfile_writes 782552 # number of floating regfile writes -system.cpu.cc_regfile_reads 224594796 # number of cc regfile reads -system.cpu.cc_regfile_writes 225242859 # number of cc regfile writes -system.cpu.misc_regfile_reads 2567204891 # number of misc regfile reads -system.cpu.misc_regfile_writes 26785378 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9653571 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.972798 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 282643774 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9654083 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.277123 # Average number of references to valid blocks. +system.cpu.commit.op_class_0::total 996609834 # Class of committed instruction +system.cpu.commit.bw_lim_events 11702475 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2585312705 # The number of ROB reads +system.cpu.rob.rob_writes 2107755396 # The number of ROB writes +system.cpu.timesIdled 8146940 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59503046 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101026198411 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 848158120 # Number of Instructions Simulated +system.cpu.committedOps 996609834 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.919550 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.919550 # CPI: Total CPI of All Threads +system.cpu.ipc 0.520955 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.520955 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1224113620 # number of integer regfile reads +system.cpu.int_regfile_writes 731134071 # number of integer regfile writes +system.cpu.fp_regfile_reads 1465257 # number of floating regfile reads +system.cpu.fp_regfile_writes 785096 # number of floating regfile writes +system.cpu.cc_regfile_reads 225210240 # number of cc regfile reads +system.cpu.cc_regfile_writes 225863400 # number of cc regfile writes +system.cpu.misc_regfile_reads 2555640420 # number of misc regfile reads +system.cpu.misc_regfile_writes 26930775 # number of misc regfile writes +system.cpu.dcache.tags.replacements 9682749 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 283083620 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9683261 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.234327 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.972798 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.972800 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 381 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1234280358 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1234280358 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 146896386 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146896386 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128038519 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128038519 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 377527 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 377527 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 324244 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 324244 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3284324 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3284324 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3679077 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3679077 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 274934905 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 274934905 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 275312432 # number of overall hits -system.cpu.dcache.overall_hits::total 275312432 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9519580 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9519580 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11197407 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11197407 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1162034 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1162034 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1231431 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1231431 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 446029 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 446029 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 20716987 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20716987 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21879021 # number of overall misses -system.cpu.dcache.overall_misses::total 21879021 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 166239076000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 166239076000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 434694643757 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 434694643757 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 89167821376 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 89167821376 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6826466500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 6826466500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 272500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 272500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 600933719757 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 600933719757 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 600933719757 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 600933719757 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 156415966 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 156415966 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 139235926 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 139235926 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1539561 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1539561 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1555675 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1555675 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3730353 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3730353 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3679082 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3679082 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 295651892 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 295651892 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 297191453 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 297191453 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060861 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.060861 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080420 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080420 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.754783 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.754783 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791573 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.791573 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119568 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119568 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.070072 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.070072 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.073619 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.073619 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17462.858235 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17462.858235 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38821.009521 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38821.009521 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 72409.920959 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 72409.920959 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15304.983532 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15304.983532 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 54500 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 54500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29006.810679 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29006.810679 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27466.207001 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27466.207001 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 49612844 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 1236470793 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1236470793 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 147113779 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 147113779 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128236098 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128236098 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 377977 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 377977 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 323653 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 323653 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3296961 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3296961 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3691090 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3691090 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 275349877 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 275349877 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 275727854 # number of overall hits +system.cpu.dcache.overall_hits::total 275727854 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9547222 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9547222 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 11260039 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 11260039 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1170114 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1170114 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1233803 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1233803 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 446138 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 446138 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 6 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 20807261 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20807261 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21977375 # number of overall misses +system.cpu.dcache.overall_misses::total 21977375 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 168019956500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 168019956500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 444932022751 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 444932022751 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 52262346938 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 52262346938 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6889431000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 6889431000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 285500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 285500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 612951979251 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 612951979251 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 612951979251 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 612951979251 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 156661001 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 156661001 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 139496137 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 139496137 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1548091 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1548091 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1557456 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1557456 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3743099 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3743099 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3691096 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3691096 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 296157138 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 296157138 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 297705229 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 297705229 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060942 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.060942 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080719 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080719 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.755843 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.755843 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.792191 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.792191 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119189 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119189 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.070258 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.070258 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.073823 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.073823 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17598.832048 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17598.832048 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39514.252371 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39514.252371 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42358.745228 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42358.745228 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15442.376574 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15442.376574 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 47583.333333 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 47583.333333 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29458.561569 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29458.561569 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27890.136072 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27890.136072 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32144751 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1593346 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1600072 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.137521 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.089565 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7472245 # number of writebacks -system.cpu.dcache.writebacks::total 7472245 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4426093 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4426093 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9200570 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9200570 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7004 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 7004 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 218758 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 218758 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 13626663 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 13626663 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 13626663 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 13626663 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5093487 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5093487 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1996837 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1996837 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1155229 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1155229 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1224427 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1224427 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 227271 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 227271 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 7090324 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 7090324 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 8245553 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 8245553 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 7504258 # number of writebacks +system.cpu.dcache.writebacks::total 7504258 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4442516 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4442516 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9255736 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9255736 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7058 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 7058 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 218425 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 218425 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 13698252 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 13698252 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 13698252 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 13698252 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5104706 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5104706 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2004303 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2004303 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1163297 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1163297 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226745 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1226745 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 227713 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 227713 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 6 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 7109009 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 7109009 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 8272306 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 8272306 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84024978000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 84024978000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76144562086 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 76144562086 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 22952152500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 22952152500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 87564866876 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 87564866876 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3184481000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3184481000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 267500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 267500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160169540086 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 160169540086 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 183121692586 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 183121692586 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6191871000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6191871000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6228308464 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228308464 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12420179464 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 12420179464 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032564 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032564 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014341 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014341 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.750363 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.750363 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787071 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787071 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060925 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060925 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023982 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.023982 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027745 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027745 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16496.552951 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16496.552951 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38132.587730 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38132.587730 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19868.054299 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19868.054299 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 71514.975475 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 71514.975475 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14011.822890 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14011.822890 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 53500 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 53500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22589.876018 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22589.876018 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22208.539874 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22208.539874 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183855.068591 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183855.068591 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184838.214150 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184838.214150 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184346.772702 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184346.772702 # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84710979000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 84710979000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77672671390 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77672671390 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23648689000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23648689000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 50594844438 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 50594844438 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3209583500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3209583500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 279500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 279500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162383650390 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 162383650390 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186032339390 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 186032339390 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6191842000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6191842000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6228406964 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228406964 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12420248964 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 12420248964 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032584 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032584 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014368 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014368 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751440 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751440 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787659 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787659 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060835 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060835 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024004 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024004 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027787 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027787 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16594.683220 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16594.683220 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38752.958704 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38752.958704 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20329.020878 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20329.020878 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41243.163362 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41243.163362 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14094.862832 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14094.862832 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 46583.333333 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 46583.333333 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22841.953132 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22841.953132 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22488.570828 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22488.570828 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183854.207495 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183854.207495 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184841.137346 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184841.137346 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184347.804257 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184347.804257 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 15015869 # number of replacements -system.cpu.icache.tags.tagsinuse 511.916858 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 339700335 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15016381 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22.621984 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 24730722500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.916858 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999838 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999838 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 15019267 # number of replacements +system.cpu.icache.tags.tagsinuse 511.928693 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 340404778 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15019779 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22.663767 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 20448016500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.928693 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999861 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 370501257 # Number of tag accesses -system.cpu.icache.tags.data_accesses 370501257 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 339700335 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 339700335 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 339700335 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 339700335 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 339700335 # 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number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 340404778 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 340404778 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 340404778 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 340404778 # number of overall hits +system.cpu.icache.overall_hits::total 340404778 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15786521 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15786521 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15786521 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15786521 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15786521 # number of overall misses +system.cpu.icache.overall_misses::total 15786521 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 213423777380 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 213423777380 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 213423777380 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 213423777380 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 213423777380 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 213423777380 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 356191299 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 356191299 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 356191299 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 356191299 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 356191299 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 356191299 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044320 # 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average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 24648 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1429 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1434 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 16.440168 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 17.188285 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 15015869 # number of writebacks -system.cpu.icache.writebacks::total 15015869 # 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number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 15019267 # number of writebacks +system.cpu.icache.writebacks::total 15019267 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 766515 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 766515 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 766515 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 766515 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 766515 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 766515 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15020006 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15020006 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15020006 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15020006 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15020006 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15020006 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191214569892 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 191214569892 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191214569892 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 191214569892 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191214569892 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 191214569892 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191135995392 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 191135995392 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191135995392 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 191135995392 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191135995392 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 191135995392 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2684938000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 2684938000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 2684938000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 2684938000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.042243 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.042243 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.042243 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.042243 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.042243 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.042243 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12733.541114 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12733.541114 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12733.541114 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12733.541114 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12733.541114 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12733.541114 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.042168 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.042168 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.042168 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.042168 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.042168 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.042168 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 19490.411179 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.567542 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004448 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006439 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.120398 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.297400 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996227 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 288 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 61244 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 288 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 554 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2686 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5116 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52825 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.934509 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 408147650 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 408147650 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 779679 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 299256 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1078935 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 7472245 # 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number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5836278000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5836278000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5770678500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8189441500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5836379500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5836379500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2418763000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607013500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 14025776500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004103 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010204 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.005802 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607058000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 14025821000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004222 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010790 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.006044 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.784102 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.784102 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.197685 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.197685 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005574 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005574 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.038376 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.038376 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.403563 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.403563 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004103 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010204 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005574 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.075357 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.029564 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004103 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010204 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005574 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.075357 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.029564 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127646.793587 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128088.816856 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127863.347785 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68011.600757 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68011.600757 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783097 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783097 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.201314 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.201314 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005512 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005512 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039436 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039436 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.405812 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.405812 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004222 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010790 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005512 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.077035 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.030160 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004222 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010790 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005512 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.077035 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.030160 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126647.937192 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127169.056402 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68010.437463 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68010.437463 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69666.666667 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69666.666667 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128655.026050 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128655.026050 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124605.160034 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124605.160034 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 128886.233897 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 128886.233897 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145023.125375 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145023.125375 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127646.793587 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128088.816856 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124605.160034 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 128745.436731 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128259.937845 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127646.793587 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128088.816856 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124605.160034 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 128745.436731 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128259.937845 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129465.449687 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129465.449687 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124519.613263 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124519.613263 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129612.133934 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129612.133934 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69897.425416 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69897.425416 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126647.937192 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124519.613263 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129523.100498 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128943.104737 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126647.937192 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124519.613263 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129523.100498 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128943.104737 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171350.302868 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148975.814960 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173203.881766 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173203.881766 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171348.610369 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148974.778069 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173206.893993 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173206.893993 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172277.339923 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.070555 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172278.000416 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.572427 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 50072876 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 25402191 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3486 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2165 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2165 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 50149666 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 25446406 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2163 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2163 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 1616472 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23106705 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 1624231 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23137410 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8523542 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 15015869 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2370764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43153 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43158 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1956829 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1956829 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15016606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6481683 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1331091 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1224427 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45091458 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29183621 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 729593 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1917139 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 76921811 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1922405600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1017963166 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2418728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6263128 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2949050622 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1833494 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 27720270 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.025088 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.156393 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 8571764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 15019267 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2370936 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 43503 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1964146 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1964146 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15020006 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6501231 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1333409 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1226745 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45101659 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29271837 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 729068 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1925616 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 77028180 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1922840864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1021731230 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2408256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6275144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2953255494 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1860303 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 27780180 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.025443 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.157467 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 27024822 97.49% 97.49% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 695448 2.51% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 27073367 97.46% 97.46% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 706813 2.54% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 27720270 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 48021701496 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 27780180 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 48093772959 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1471889 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1496382 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22555136481 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22560257433 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13331758520 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13373462829 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 427610263 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 428394234 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1134604242 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1141603196 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40281 # Transaction distribution -system.iobus.trans_dist::ReadResp 40281 # Transaction distribution +system.iobus.trans_dist::ReadReq 40297 # Transaction distribution +system.iobus.trans_dist::ReadResp 40297 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1727,11 +1729,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230920 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230920 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353736 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1746,16 +1748,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334112 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334112 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492032 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 41869500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41874500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 342000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 342500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1769,77 +1771,77 @@ system.iobus.reqLayer14.occupancy 9500 # La system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25153000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25162500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36496500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36499500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 567170357 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 567349755 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147680000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147712000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115446 # number of replacements -system.iocache.tags.tagsinuse 10.422236 # Cycle average of tags in use +system.iocache.tags.replacements 115457 # number of replacements +system.iocache.tags.tagsinuse 10.423127 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115462 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13103145496000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 5.903254 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 4.518982 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.368953 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.282436 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651390 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13098803375000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544202 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.878925 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221513 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429933 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651445 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039497 # Number of tag accesses -system.iocache.tags.data_accesses 1039497 # Number of data accesses +system.iocache.tags.tag_accesses 1039641 # Number of tag accesses +system.iocache.tags.data_accesses 1039641 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8796 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8833 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8796 # number of demand (read+write) misses -system.iocache.demand_misses::total 8836 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8812 # number of demand (read+write) misses +system.iocache.demand_misses::total 8852 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8796 # number of overall misses -system.iocache.overall_misses::total 8836 # number of overall misses +system.iocache.overall_misses::realview.ide 8812 # number of overall misses +system.iocache.overall_misses::total 8852 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5069500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1678447047 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1683516547 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1683110232 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1688179732 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13410212810 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13410212810 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13415109023 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13415109023 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5420500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1678447047 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1683867547 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1683110232 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1688530732 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5420500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1678447047 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1683867547 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1683110232 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1688530732 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8796 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8833 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8796 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8836 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8812 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8852 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8796 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8836 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8812 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8852 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1854,54 +1856,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 190819.355048 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 190593.971131 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 191002.068997 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 190776.328625 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125723.888191 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125723.888191 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125769.791335 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125769.791335 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 190819.355048 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 190568.984495 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 191002.068997 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 190751.325350 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 190819.355048 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 190568.984495 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34452 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 191002.068997 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 190751.325350 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34444 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3448 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3506 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.991879 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.824301 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8796 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8833 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8812 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8849 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8796 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8836 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8812 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8852 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8796 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8836 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8812 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8852 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1238647047 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1241866547 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1242510232 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1245729732 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8071956842 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8071956842 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8076836456 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8076836456 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3420500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1238647047 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1242067547 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1242510232 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1245930732 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3420500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1238647047 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1242067547 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1242510232 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1245930732 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1916,71 +1918,71 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140819.355048 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 140593.971131 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141002.068997 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 140776.328625 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75676.487306 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75676.487306 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75722.234831 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75722.234831 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 140819.355048 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 140568.984495 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 141002.068997 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 140751.325350 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 140819.355048 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 140568.984495 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 141002.068997 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 140751.325350 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 54972 # Transaction distribution -system.membus.trans_dist::ReadResp 402203 # Transaction distribution +system.membus.trans_dist::ReadResp 409202 # Transaction distribution system.membus.trans_dist::WriteReq 33696 # Transaction distribution system.membus.trans_dist::WriteResp 33696 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1051260 # Transaction distribution -system.membus.trans_dist::CleanEvict 188377 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34626 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1067474 # Transaction distribution +system.membus.trans_dist::CleanEvict 191385 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34855 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 880179 # Transaction distribution -system.membus.trans_dist::ReadExResp 880179 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 347231 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution +system.membus.trans_dist::ReadExReq 394790 # Transaction distribution +system.membus.trans_dist::ReadExResp 394790 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 354230 # Transaction distribution +system.membus.trans_dist::InvalidateReq 604321 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3643028 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3772648 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237638 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237638 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4010286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3203313 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3332933 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237959 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237959 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3570892 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 138764108 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 138934078 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7252608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7252608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 146186686 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2808 # Total snoops (count) -system.membus.snoop_fanout::samples 2697046 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 109183820 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 109353790 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7271424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7271424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 116625214 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2530 # Total snoops (count) +system.membus.snoop_fanout::samples 2735759 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2697046 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2735759 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2697046 # Request fanout histogram -system.membus.reqLayer0.occupancy 103954500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2735759 # Request fanout histogram +system.membus.reqLayer0.occupancy 103971500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 32000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5466500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5468000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7139670905 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7155774176 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6571001988 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4068025704 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44720417 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44802062 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2035,6 +2037,6 @@ system.realview.mcc.osc_mcc.clock 20000 # Cl system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16102 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 16114 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 6b53e6579..87961def1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,172 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.354243 # Number of seconds simulated -sim_ticks 47354242877000 # Number of ticks simulated -final_tick 47354242877000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.389788 # Number of seconds simulated +sim_ticks 47389787812000 # Number of ticks simulated +final_tick 47389787812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 195342 # Simulator instruction rate (inst/s) -host_op_rate 229691 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10034841905 # Simulator tick rate (ticks/s) -host_mem_usage 778832 # Number of bytes of host memory used -host_seconds 4718.98 # Real time elapsed on the host -sim_insts 921815819 # Number of instructions simulated -sim_ops 1083910027 # Number of ops (including micro ops) simulated +host_inst_rate 198747 # Simulator instruction rate (inst/s) +host_op_rate 233711 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10002045644 # Simulator tick rate (ticks/s) +host_mem_usage 770464 # Number of bytes of host memory used +host_seconds 4738.01 # Real time elapsed on the host +sim_insts 941666991 # Number of instructions simulated +sim_ops 1107326086 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 202368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 196224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4450144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 45350984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 22283904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 113792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 85504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2862048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 13865872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 12452160 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 439808 # Number of bytes read from this memory -system.physmem.bytes_read::total 102302808 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4450144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2862048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7312192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 85371072 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 242048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 235072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4481952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 17644744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 24714560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 130176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 100480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2927520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 10373200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 13817664 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 418560 # Number of bytes read from this memory +system.physmem.bytes_read::total 75085976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4481952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2927520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7409472 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 91336640 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 85391656 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3162 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3066 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 85486 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 708622 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 348186 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1778 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1336 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 44763 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 216667 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 194565 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6872 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1614503 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1333923 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 91357224 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3782 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3673 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 85983 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 275712 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 386165 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2034 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1570 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 45786 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 162094 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 215901 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6540 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1189240 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1427135 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1336497 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 4273 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 4144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 93976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 957696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 470579 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2403 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1806 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 60439 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 292812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 262958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2160373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 93976 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 60439 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 154415 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1802818 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1429709 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 5108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 4960 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 94576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 372332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 521517 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2120 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 61775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 218891 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 291575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8832 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1584434 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 94576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 61775 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 156352 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1927349 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1803252 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1802818 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 4273 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 4144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 93976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 958131 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 470579 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1806 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 60439 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 292812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 262958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3963625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1614503 # Number of read requests accepted -system.physmem.writeReqs 1336497 # Number of write requests accepted -system.physmem.readBursts 1614503 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1336497 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 103293760 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 34432 # Total number of bytes read from write queue -system.physmem.bytesWritten 85390720 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 102302808 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 85391656 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 538 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1927783 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1927349 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 5108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 4960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 94576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 372766 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 521517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 61775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 218891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 291575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8832 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3512217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1189240 # Number of read requests accepted +system.physmem.writeReqs 1429709 # Number of write requests accepted +system.physmem.readBursts 1189240 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1429709 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 76085248 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 26112 # Total number of bytes read from write queue +system.physmem.bytesWritten 91355968 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 75085976 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 91357224 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 408 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 97103 # Per bank write bursts -system.physmem.perBankRdBursts::1 99552 # Per bank write bursts -system.physmem.perBankRdBursts::2 98906 # Per bank write bursts -system.physmem.perBankRdBursts::3 103577 # Per bank write bursts -system.physmem.perBankRdBursts::4 99773 # Per bank write bursts -system.physmem.perBankRdBursts::5 105983 # Per bank write bursts -system.physmem.perBankRdBursts::6 104785 # Per bank write bursts -system.physmem.perBankRdBursts::7 101396 # Per bank write bursts -system.physmem.perBankRdBursts::8 95400 # Per bank write bursts -system.physmem.perBankRdBursts::9 122614 # Per bank write bursts -system.physmem.perBankRdBursts::10 95999 # Per bank write bursts -system.physmem.perBankRdBursts::11 101585 # Per bank write bursts -system.physmem.perBankRdBursts::12 99838 # Per bank write bursts -system.physmem.perBankRdBursts::13 98462 # Per bank write bursts -system.physmem.perBankRdBursts::14 93633 # Per bank write bursts -system.physmem.perBankRdBursts::15 95359 # Per bank write bursts -system.physmem.perBankWrBursts::0 80772 # Per bank write bursts -system.physmem.perBankWrBursts::1 85062 # Per bank write bursts -system.physmem.perBankWrBursts::2 82679 # Per bank write bursts -system.physmem.perBankWrBursts::3 85393 # Per bank write bursts -system.physmem.perBankWrBursts::4 84018 # Per bank write bursts -system.physmem.perBankWrBursts::5 87943 # Per bank write bursts -system.physmem.perBankWrBursts::6 87092 # Per bank write bursts -system.physmem.perBankWrBursts::7 86427 # Per bank write bursts -system.physmem.perBankWrBursts::8 80096 # Per bank write bursts -system.physmem.perBankWrBursts::9 84617 # Per bank write bursts -system.physmem.perBankWrBursts::10 79653 # Per bank write bursts -system.physmem.perBankWrBursts::11 85236 # Per bank write bursts -system.physmem.perBankWrBursts::12 82895 # Per bank write bursts -system.physmem.perBankWrBursts::13 82853 # Per bank write bursts -system.physmem.perBankWrBursts::14 78695 # Per bank write bursts -system.physmem.perBankWrBursts::15 80799 # Per bank write bursts +system.physmem.perBankRdBursts::0 75559 # Per bank write bursts +system.physmem.perBankRdBursts::1 80347 # Per bank write bursts +system.physmem.perBankRdBursts::2 72779 # Per bank write bursts +system.physmem.perBankRdBursts::3 76774 # Per bank write bursts +system.physmem.perBankRdBursts::4 67339 # Per bank write bursts +system.physmem.perBankRdBursts::5 74455 # Per bank write bursts +system.physmem.perBankRdBursts::6 73080 # Per bank write bursts +system.physmem.perBankRdBursts::7 76470 # Per bank write bursts +system.physmem.perBankRdBursts::8 66258 # Per bank write bursts +system.physmem.perBankRdBursts::9 90024 # Per bank write bursts +system.physmem.perBankRdBursts::10 66637 # Per bank write bursts +system.physmem.perBankRdBursts::11 75253 # Per bank write bursts +system.physmem.perBankRdBursts::12 70442 # Per bank write bursts +system.physmem.perBankRdBursts::13 75330 # Per bank write bursts +system.physmem.perBankRdBursts::14 75010 # Per bank write bursts +system.physmem.perBankRdBursts::15 73075 # Per bank write bursts +system.physmem.perBankWrBursts::0 90501 # Per bank write bursts +system.physmem.perBankWrBursts::1 95401 # Per bank write bursts +system.physmem.perBankWrBursts::2 90023 # Per bank write bursts +system.physmem.perBankWrBursts::3 92589 # Per bank write bursts +system.physmem.perBankWrBursts::4 84855 # Per bank write bursts +system.physmem.perBankWrBursts::5 90903 # Per bank write bursts +system.physmem.perBankWrBursts::6 89246 # Per bank write bursts +system.physmem.perBankWrBursts::7 91287 # Per bank write bursts +system.physmem.perBankWrBursts::8 85201 # Per bank write bursts +system.physmem.perBankWrBursts::9 88427 # Per bank write bursts +system.physmem.perBankWrBursts::10 83204 # Per bank write bursts +system.physmem.perBankWrBursts::11 90055 # Per bank write bursts +system.physmem.perBankWrBursts::12 88087 # Per bank write bursts +system.physmem.perBankWrBursts::13 89545 # Per bank write bursts +system.physmem.perBankWrBursts::14 89641 # Per bank write bursts +system.physmem.perBankWrBursts::15 88472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 46 # Number of times write queue was full causing retry -system.physmem.totGap 47354241269500 # Total gap between requests +system.physmem.numWrRetry 54 # Number of times write queue was full causing retry +system.physmem.totGap 47389786204500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1593145 # Read request sizes (log2) +system.physmem.readPktSize::6 1167882 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1333923 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 609512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 408742 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 165543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 158385 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 99064 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 61330 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 32974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30716 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 7850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2710 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1710 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 869 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 497 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1427135 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 517223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 309889 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 86868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 62308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 44912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 40171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 37097 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 35200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 31021 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 8620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4820 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 3062 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2092 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1731 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 973 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 612 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 91 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see @@ -188,166 +188,160 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 21385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 25204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 37704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 53566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 68935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 76299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 82207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 85573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 89148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 94653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 94373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 98828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 112387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 98640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 87955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 82141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 109 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1039142 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 181.576816 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 111.689088 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.244363 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 644376 62.01% 62.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 193180 18.59% 80.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 61698 5.94% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 33929 3.27% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 24382 2.35% 92.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13748 1.32% 93.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 13846 1.33% 94.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7628 0.73% 95.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 46355 4.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1039142 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 75311 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.430349 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 250.668355 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 75308 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::65536-69631 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 75311 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 75311 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.716270 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.189166 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.091364 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 70052 93.02% 93.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 3029 4.02% 97.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 423 0.56% 97.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 178 0.24% 97.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 138 0.18% 98.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 118 0.16% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 205 0.27% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 81 0.11% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 292 0.39% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 59 0.08% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 23 0.03% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 57 0.08% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 240 0.32% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 44 0.06% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 27 0.04% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 108 0.14% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 169 0.22% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 75311 # Writes before turning the bus around for reads -system.physmem.totQLat 70116127057 # Total ticks spent queuing -system.physmem.totMemAccLat 100377970807 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8069825000 # Total ticks spent in databus transfers -system.physmem.avgQLat 43443.40 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 27129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 32204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 45048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 50289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 57286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 67754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 74659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 80821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 85044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 90854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 96241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 95504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 100014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 112663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 99616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 90045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 84036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 13635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 10081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 6959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 5731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 4894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 154 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1166319 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 143.563495 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 97.562003 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 190.410734 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 788306 67.59% 67.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 223066 19.13% 86.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 56490 4.84% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24874 2.13% 93.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 21482 1.84% 95.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12177 1.04% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8088 0.69% 97.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4845 0.42% 97.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 26991 2.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1166319 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 68435 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 17.371564 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 68.388871 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 68432 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 68435 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 68435 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.858289 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.984573 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 74.928718 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-127 68190 99.64% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-255 151 0.22% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-383 21 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-511 14 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-639 8 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-767 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::768-895 5 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::896-1023 6 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1024-1151 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1152-1279 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1280-1407 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1536-1663 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1664-1791 4 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1792-1919 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2304-2431 4 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2432-2559 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2560-2687 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2688-2815 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2816-2943 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2944-3071 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3072-3199 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3584-3711 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3712-3839 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4096-4223 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4224-4351 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4864-4991 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5504-5631 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6656-6783 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7680-7807 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 68435 # Writes before turning the bus around for reads +system.physmem.totQLat 53856464568 # Total ticks spent queuing +system.physmem.totMemAccLat 76147064568 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5944160000 # Total ticks spent in databus transfers +system.physmem.avgQLat 45302.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 62193.40 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.80 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.80 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 64052.00 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.61 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.93 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.58 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.55 # Average write queue length when enqueuing -system.physmem.readRowHits 1298803 # Number of row buffer hits during reads -system.physmem.writeRowHits 610248 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 45.74 # Row buffer hit rate for writes -system.physmem.avgGap 16046845.57 # Average gap between requests -system.physmem.pageHitRate 64.75 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4027930200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2197779375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6326346000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4402421280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3092948511120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1180978829595 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27376595514000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31667477331570 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.735888 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45543196260914 # Time in different power states -system.physmem_0.memoryStateTime::REF 1581262020000 # Time in different power states +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.02 # Average write queue length when enqueuing +system.physmem.readRowHits 898304 # Number of row buffer hits during reads +system.physmem.writeRowHits 551645 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.56 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.65 # Row buffer hit rate for writes +system.physmem.avgGap 18094963.36 # Average gap between requests +system.physmem.pageHitRate 55.42 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4527963720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2470615125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4655063400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4696736400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3095270087520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1182204826065 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27396846617250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31690671909480 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.723752 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45576929865903 # Time in different power states +system.physmem_0.memoryStateTime::REF 1582448920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 229783905086 # Time in different power states +system.physmem_0.memoryStateTime::ACT 230401885347 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3827983320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2088681375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6262534200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4243389120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3092948511120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1177720349355 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27379453830000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31666545278490 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.716205 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45547950580913 # Time in different power states -system.physmem_1.memoryStateTime::REF 1581262020000 # Time in different power states +system.physmem_1.actEnergy 4289407920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2340450750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4617779400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4553055360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3095270087520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1179475938810 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27399240378000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31689787097760 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.705081 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45580905738073 # Time in different power states +system.physmem_1.memoryStateTime::REF 1582448920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 225030017087 # Time in different power states +system.physmem_1.memoryStateTime::ACT 226432462927 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -381,15 +375,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 149665852 # Number of BP lookups -system.cpu0.branchPred.condPredicted 99294558 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 7394871 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 104737280 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 69525721 # Number of BTB hits +system.cpu0.branchPred.lookups 148316317 # Number of BP lookups +system.cpu0.branchPred.condPredicted 98700135 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 7173487 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 104790534 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 69246034 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.381064 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 20507496 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 218312 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 66.080429 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 20257126 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 200970 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -420,86 +414,92 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 634428 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 634428 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 14162 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 100318 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 297022 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 337406 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2383.727616 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 14932.270093 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 334700 99.20% 99.20% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1380 0.41% 99.61% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 1061 0.31% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 114 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 46 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 68 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 21 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 656451 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 656451 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 15175 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 105539 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 311743 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 344708 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2528.499484 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 15542.861274 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 341657 99.11% 99.11% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1528 0.44% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 1197 0.35% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 153 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 49 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 98 0.03% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 19 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 337406 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 331422 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 21257.229454 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 17843.462773 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 23121.353715 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 326855 98.62% 98.62% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1016 0.31% 98.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 2453 0.74% 99.67% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 165 0.05% 99.72% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 627 0.19% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 136 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkWaitTime::total 344708 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 348998 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 21459.124408 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 17964.910208 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 23694.067201 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 343876 98.53% 98.53% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1141 0.33% 98.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 2753 0.79% 99.65% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 227 0.07% 99.71% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 627 0.18% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 192 0.06% 99.95% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::393216-458751 104 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 36 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 24 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 331422 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 582048251060 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.606269 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.543146 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 580572178560 99.75% 99.75% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 833055500 0.14% 99.89% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 305294500 0.05% 99.94% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 135391000 0.02% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 101845000 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 57765000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 18306500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 23753000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 653000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 9000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 582048251060 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 100318 87.63% 87.63% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 14162 12.37% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 114480 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 634428 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 60 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 15 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 348998 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 578933652396 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.598699 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.548790 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 577357711896 99.73% 99.73% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 896498000 0.15% 99.88% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 316445000 0.05% 99.94% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 146967500 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 111299500 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 56334000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 19702000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 27806500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 847500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 17500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-21 1000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::22-23 1500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-25 1500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::26-27 2500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-29 1500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::30-31 15000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 578933652396 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 105540 87.43% 87.43% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 15175 12.57% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 120715 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 656451 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 634428 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 114480 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 656451 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 120715 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 114480 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 748908 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 120715 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 777166 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 109416332 # DTB read hits -system.cpu0.dtb.read_misses 460008 # DTB read misses -system.cpu0.dtb.write_hits 89314742 # DTB write hits -system.cpu0.dtb.write_misses 174420 # DTB write misses -system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 108931388 # DTB read hits +system.cpu0.dtb.read_misses 471682 # DTB read misses +system.cpu0.dtb.write_hits 89197418 # DTB write hits +system.cpu0.dtb.write_misses 184769 # DTB write misses +system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 43796 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 708 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 7923 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 46180 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 44365 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 621 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 7762 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 42753 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 109876340 # DTB read accesses -system.cpu0.dtb.write_accesses 89489162 # DTB write accesses +system.cpu0.dtb.perms_faults 42293 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 109403070 # DTB read accesses +system.cpu0.dtb.write_accesses 89382187 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 198731074 # DTB hits -system.cpu0.dtb.misses 634428 # DTB misses -system.cpu0.dtb.accesses 199365502 # DTB accesses +system.cpu0.dtb.hits 198128806 # DTB hits +system.cpu0.dtb.misses 656451 # DTB misses +system.cpu0.dtb.accesses 198785257 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -529,1175 +529,1182 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 91298 # Table walker walks requested -system.cpu0.itb.walker.walksLong 91298 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1125 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 66671 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 10542 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 80756 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1599.144336 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 12482.430449 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-65535 80336 99.48% 99.48% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-131071 92 0.11% 99.59% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-196607 294 0.36% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-262143 14 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-327679 11 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-393215 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 80756 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 78338 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 27568.581021 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23319.178868 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 29698.501423 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 76052 97.08% 97.08% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 130 0.17% 97.25% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 1833 2.34% 99.59% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 110 0.14% 99.73% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 108 0.14% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 41 0.05% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 39 0.05% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 15 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::917504-983039 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 78338 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 423131286608 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.845297 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.361834 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 65489609660 15.48% 15.48% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 357613926448 84.52% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 25558000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 2033000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 159500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 423131286608 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 66671 98.34% 98.34% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 1125 1.66% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 67796 # Table walker page sizes translated +system.cpu0.itb.walker.walks 90363 # Table walker walks requested +system.cpu0.itb.walker.walksLong 90363 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1091 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 64708 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 10655 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 79708 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1706.014453 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 13195.811582 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 78781 98.84% 98.84% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 448 0.56% 99.40% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 48 0.06% 99.46% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 68 0.09% 99.54% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 262 0.33% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 71 0.09% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 3 0.00% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::393216-425983 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 79708 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 76454 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 28396.329819 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23477.172430 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 32204.710724 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 73773 96.49% 96.49% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 162 0.21% 96.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 2119 2.77% 99.48% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 153 0.20% 99.68% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 135 0.18% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 40 0.05% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 46 0.06% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 11 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 76454 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 441465071924 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.843066 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.363947 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 69311314608 15.70% 15.70% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 372126528316 84.29% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 24340500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 2776500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 112000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 441465071924 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 64708 98.34% 98.34% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 1091 1.66% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 65799 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 91298 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 91298 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 90363 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 90363 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 67796 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 67796 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 159094 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 236080263 # ITB inst hits -system.cpu0.itb.inst_misses 91298 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 65799 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 65799 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 156162 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 234328898 # ITB inst hits +system.cpu0.itb.inst_misses 90363 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 31862 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 46180 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 32417 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 229508 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 232055 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 236171561 # ITB inst accesses -system.cpu0.itb.hits 236080263 # DTB hits -system.cpu0.itb.misses 91298 # DTB misses -system.cpu0.itb.accesses 236171561 # DTB accesses -system.cpu0.numCycles 875332831 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 234419261 # ITB inst accesses +system.cpu0.itb.hits 234328898 # DTB hits +system.cpu0.itb.misses 90363 # DTB misses +system.cpu0.itb.accesses 234419261 # DTB accesses +system.cpu0.numCycles 866695747 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 98502478 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 662547160 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 149665852 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 90033217 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 725278481 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 15926346 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2210942 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 343253 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 6644206 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 843353 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 921483 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 235849038 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1874950 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 30072 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 842707369 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.920891 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.205357 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 96427999 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 657049317 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 148316317 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 89503160 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 718043211 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 15454228 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2249933 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 346517 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6840136 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 871998 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 916038 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 234095625 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1822748 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 30173 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 833422946 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.924189 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.205964 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 471086256 55.90% 55.90% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 144263495 17.12% 73.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 50294842 5.97% 78.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 177062776 21.01% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 464359111 55.72% 55.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 143558418 17.23% 72.94% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 49834021 5.98% 78.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 175671396 21.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 842707369 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.170982 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.756909 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 117017992 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 431286061 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 248304840 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 40439583 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5658893 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 21552813 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2348874 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 685973615 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 25548756 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5658893 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 155339909 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 68898576 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 270709645 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 249775497 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 92324849 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 667175567 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6553348 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 11928405 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 414386 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 932685 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 54388046 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 11955 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 637281036 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1029527825 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 787757309 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 900744 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 574091859 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 63189171 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 16646916 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 14438257 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 81666616 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 109512073 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 93001551 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 9792967 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 8489048 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 643441375 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 16650008 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 647817648 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2959555 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 59258512 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 38730764 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 299230 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 842707369 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.768734 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.052616 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 833422946 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.171128 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.758108 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 115740257 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 426691474 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 243999178 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 41506758 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5485279 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 21281954 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2285386 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 681861872 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 24692274 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5485279 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 154051427 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 67882232 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 271801592 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 246639237 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 87563179 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 663764828 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6318012 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 12552479 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 452890 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 885924 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 48607179 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 12032 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 634283684 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1028589268 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 784350114 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 810310 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 573100551 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 61183133 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 17365169 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 15184195 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 83196676 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 108756528 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 92814116 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 10086189 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8556855 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 639440304 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 17486234 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 645371130 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2878587 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 57563182 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 37565263 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 301808 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 833422946 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.774362 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.052683 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 489695832 58.11% 58.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 146908165 17.43% 75.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 125837037 14.93% 90.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 71836004 8.52% 99.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 8424258 1.00% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 6073 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 480257343 57.62% 57.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 149217372 17.90% 75.53% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 124187121 14.90% 90.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 71270973 8.55% 98.98% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 8484088 1.02% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 6049 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 842707369 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 833422946 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 67261039 45.56% 45.56% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 66196 0.04% 45.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 15732 0.01% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 29 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 38768633 26.26% 71.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 41521295 28.12% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 66055625 45.01% 45.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 69293 0.05% 45.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 22404 0.02% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 17 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 38927283 26.53% 71.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 41671380 28.40% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 14 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 442579425 68.32% 68.32% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1577066 0.24% 68.56% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 84316 0.01% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 83107 0.01% 68.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.59% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 112773884 17.41% 86.00% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 90719836 14.00% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 440798988 68.30% 68.30% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1592862 0.25% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 83426 0.01% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 82619 0.01% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 112232372 17.39% 85.96% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 90580861 14.04% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 647817648 # Type of FU issued -system.cpu0.iq.rate 0.740082 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 147632924 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.227893 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2287461115 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 718905040 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 629078745 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1474027 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 598009 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 548346 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 794539840 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 910718 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2963176 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 645371130 # Type of FU issued +system.cpu0.iq.rate 0.744634 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 146746002 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.227382 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2272436054 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 714094331 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 626839047 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1353741 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 552796 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 503202 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 791281833 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 835299 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 3004923 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 13511879 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 17808 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 154801 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 6318307 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 13275769 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 18782 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 159110 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 6200623 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2892844 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5122180 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2963562 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5149852 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5658893 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8725604 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 7188731 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 660220960 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5485279 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8917054 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 3122413 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 657057128 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 109512073 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 93001551 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 14147683 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 61387 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 7052032 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 154801 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2237378 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 3184169 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5421547 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 639276531 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 109409199 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7914356 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 108756528 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 92814116 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 14923426 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 69667 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2968943 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 159110 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2170447 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3075539 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5245986 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 637077586 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 108926469 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7646279 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 129577 # number of nop insts executed -system.cpu0.iew.exec_refs 198721456 # number of memory reference insts executed -system.cpu0.iew.exec_branches 120519027 # Number of branches executed -system.cpu0.iew.exec_stores 89312257 # Number of stores executed -system.cpu0.iew.exec_rate 0.730324 # Inst execution rate -system.cpu0.iew.wb_sent 630467148 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 629627091 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 306648182 # num instructions producing a value -system.cpu0.iew.wb_consumers 503078288 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.719300 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609544 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 51710398 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 16350778 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 5090591 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 832883786 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.721389 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.530255 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 130590 # number of nop insts executed +system.cpu0.iew.exec_refs 198124159 # number of memory reference insts executed +system.cpu0.iew.exec_branches 119913450 # Number of branches executed +system.cpu0.iew.exec_stores 89197690 # Number of stores executed +system.cpu0.iew.exec_rate 0.735065 # Inst execution rate +system.cpu0.iew.wb_sent 628157908 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 627342249 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 305063287 # num instructions producing a value +system.cpu0.iew.wb_consumers 500478465 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.723832 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609543 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 50300993 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 17184426 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4931652 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 823863885 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.727503 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.534838 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 570514920 68.50% 68.50% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 134700149 16.17% 84.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 59058098 7.09% 91.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 19776256 2.37% 94.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 14036208 1.69% 95.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 9662272 1.16% 96.98% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6431324 0.77% 97.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3992857 0.48% 98.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 14711702 1.77% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 560826617 68.07% 68.07% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 136759290 16.60% 84.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 58156007 7.06% 91.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 19570368 2.38% 94.11% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 13861730 1.68% 95.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 9557005 1.16% 96.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6407217 0.78% 97.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3899508 0.47% 98.20% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14826143 1.80% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 832883786 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 511876907 # Number of instructions committed -system.cpu0.commit.committedOps 600832864 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 823863885 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 510319417 # Number of instructions committed +system.cpu0.commit.committedOps 599363355 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 182683437 # Number of memory references committed -system.cpu0.commit.loads 96000193 # Number of loads committed -system.cpu0.commit.membars 3986424 # Number of memory barriers committed -system.cpu0.commit.branches 114418082 # Number of branches committed -system.cpu0.commit.fp_insts 535391 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 551244640 # Number of committed integer instructions. -system.cpu0.commit.function_calls 15252520 # Number of function calls committed. +system.cpu0.commit.refs 182094252 # Number of memory references committed +system.cpu0.commit.loads 95480759 # Number of loads committed +system.cpu0.commit.membars 4094698 # Number of memory barriers committed +system.cpu0.commit.branches 113994539 # Number of branches committed +system.cpu0.commit.fp_insts 490256 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 549724602 # Number of committed integer instructions. +system.cpu0.commit.function_calls 15118537 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 416691372 69.35% 69.35% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1318004 0.22% 69.57% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 66523 0.01% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 73528 0.01% 69.59% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.59% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.59% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.59% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 96000193 15.98% 85.57% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 86683244 14.43% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 415786848 69.37% 69.37% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1342849 0.22% 69.60% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 66347 0.01% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 73059 0.01% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 95480759 15.93% 85.55% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 86613493 14.45% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 600832864 # Class of committed instruction -system.cpu0.commit.bw_lim_events 14711702 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1466105636 # The number of ROB reads -system.cpu0.rob.rob_writes 1314872451 # The number of ROB writes -system.cpu0.timesIdled 1097159 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 32625462 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93833152963 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 511876907 # Number of Instructions Simulated -system.cpu0.committedOps 600832864 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.710046 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.710046 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.584780 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.584780 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 754446272 # number of integer regfile reads -system.cpu0.int_regfile_writes 448604038 # number of integer regfile writes -system.cpu0.fp_regfile_reads 881646 # number of floating regfile reads -system.cpu0.fp_regfile_writes 476304 # number of floating regfile writes -system.cpu0.cc_regfile_reads 139793568 # number of cc regfile reads -system.cpu0.cc_regfile_writes 140496633 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1470350924 # number of misc regfile reads -system.cpu0.misc_regfile_writes 16456285 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 6559473 # number of replacements -system.cpu0.dcache.tags.tagsinuse 490.326221 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 169584910 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6559985 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 25.851417 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 599363355 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14826143 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1454251951 # The number of ROB reads +system.cpu0.rob.rob_writes 1308847090 # The number of ROB writes +system.cpu0.timesIdled 1090671 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 33272801 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93912870328 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 510319417 # Number of Instructions Simulated +system.cpu0.committedOps 599363355 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.698340 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.698340 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.588810 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.588810 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 752522588 # number of integer regfile reads +system.cpu0.int_regfile_writes 446228364 # number of integer regfile writes +system.cpu0.fp_regfile_reads 791452 # number of floating regfile reads +system.cpu0.fp_regfile_writes 475504 # number of floating regfile writes +system.cpu0.cc_regfile_reads 139593627 # number of cc regfile reads +system.cpu0.cc_regfile_writes 140336082 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1450242581 # number of misc regfile reads +system.cpu0.misc_regfile_writes 17300190 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 6628748 # number of replacements +system.cpu0.dcache.tags.tagsinuse 507.898673 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 168544062 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6629257 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 25.424276 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 2962390000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 490.326221 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.957668 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.957668 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 382 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 36 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 379087602 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 379087602 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 89088742 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 89088742 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 75269986 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 75269986 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 228422 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 228422 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 263534 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 263534 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1920078 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1920078 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1972778 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1972778 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 164358728 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 164358728 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 164587150 # number of overall hits -system.cpu0.dcache.overall_hits::total 164587150 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 7258058 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7258058 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 8107301 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 8107301 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 768102 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 768102 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 855425 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 855425 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 287297 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 287297 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 193519 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 193519 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 15365359 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 15365359 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 16133461 # number of overall misses -system.cpu0.dcache.overall_misses::total 16133461 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 123043131500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 123043131500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 187154125822 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 187154125822 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 92776135134 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 92776135134 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4545100500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4545100500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5540857500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5540857500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 7820000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 7820000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 310197257322 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 310197257322 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 310197257322 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 310197257322 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 96346800 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 96346800 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 83377287 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 83377287 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 996524 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 996524 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1118959 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1118959 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2207375 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2207375 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2166297 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2166297 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 179724087 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 179724087 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 180720611 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 180720611 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075333 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.075333 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.097236 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.097236 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770781 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770781 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.764483 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.764483 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.130153 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.130153 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089332 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089332 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.085494 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.085494 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.089273 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.089273 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16952.624449 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 16952.624449 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23084.640107 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 23084.640107 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 108456.188601 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 108456.188601 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15820.215665 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15820.215665 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28632.111059 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28632.111059 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.898673 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.991990 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.991990 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 381 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 377708512 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 377708512 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 88226592 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 88226592 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 75029005 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 75029005 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 221757 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 221757 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 177850 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 177850 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1970217 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1970217 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2022489 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2022489 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 163255597 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 163255597 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 163477354 # number of overall hits +system.cpu0.dcache.overall_hits::total 163477354 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 7367994 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7367994 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 8340746 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 8340746 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 804684 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 804684 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 826218 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 826218 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 297937 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 297937 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 206643 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 206643 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 15708740 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 15708740 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 16513424 # number of overall misses +system.cpu0.dcache.overall_misses::total 16513424 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 129957875000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 129957875000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 197611984656 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 197611984656 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 55152577242 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 55152577242 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4832056500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 4832056500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5849414000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 5849414000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5216000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5216000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 327569859656 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 327569859656 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 327569859656 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 327569859656 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 95594586 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 95594586 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 83369751 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 83369751 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1026441 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1026441 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1004068 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1004068 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2268154 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2268154 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2229132 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2229132 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 178964337 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 178964337 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 179990778 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 179990778 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.077075 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.077075 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.100045 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.100045 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.783955 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.783955 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.822871 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.822871 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.131357 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.131357 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.092701 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.092701 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.087776 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.087776 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.091746 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.091746 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17638.162436 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 17638.162436 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23692.363328 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 23692.363328 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 66753.056992 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 66753.056992 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16218.383417 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16218.383417 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28306.857721 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28306.857721 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20188.090452 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 20188.090452 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19226.950579 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 19226.950579 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 29213495 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 28830141 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 790800 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 799061 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 36.941698 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 36.080025 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20852.713818 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20852.713818 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19836.580206 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 19836.580206 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 17065024 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 30777617 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 770223 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 827793 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 22.155952 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 37.180330 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 6559531 # number of writebacks -system.cpu0.dcache.writebacks::total 6559531 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3685333 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3685333 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6510101 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 6510101 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4620 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 4620 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 146516 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 146516 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 10195434 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 10195434 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 10195434 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 10195434 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3572725 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3572725 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1597200 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1597200 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 761247 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 761247 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 850805 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 850805 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 140781 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 140781 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 193511 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 193511 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5169925 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5169925 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5931172 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5931172 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32878 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32878 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32941 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32941 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65819 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65819 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 56556979500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 56556979500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 42701336905 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 42701336905 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18998780500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18998780500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 91672230134 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 91672230134 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2014552000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2014552000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5347454500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5347454500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 7712000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 7712000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99258316405 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 99258316405 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 118257096905 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 118257096905 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6293183000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6293183000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 6230446500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6230446500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12523629500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12523629500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037082 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037082 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019156 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019156 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.763902 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.763902 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.760354 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.760354 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063778 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063778 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089328 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089328 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028766 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028766 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032820 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032820 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15830.207895 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15830.207895 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26735.122029 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26735.122029 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24957.445481 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24957.445481 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 107747.639158 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 107747.639158 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14309.828741 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14309.828741 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27633.852856 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27633.852856 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 6628874 # number of writebacks +system.cpu0.dcache.writebacks::total 6628874 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3770079 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3770079 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6700876 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6700876 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4178 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 4178 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 152938 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 152938 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 10470955 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 10470955 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 10470955 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 10470955 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3597915 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3597915 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1639870 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1639870 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 797671 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 797671 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 822040 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 822040 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 144999 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 144999 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 206643 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 206643 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5237785 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5237785 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 6035456 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 6035456 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 19715 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 19715 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 21606 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 21606 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 41321 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 41321 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 58751059000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 58751059000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 44752175448 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 44752175448 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 21047920500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 21047920500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 54096896242 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 54096896242 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2128355000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2128355000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5642835000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5642835000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5152000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5152000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 103503234448 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 103503234448 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 124551154948 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 124551154948 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3829698500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3829698500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4085083000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4085083000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7914781500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7914781500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037637 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037637 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019670 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019670 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.777123 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.777123 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.818709 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.818709 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063928 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063928 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092701 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092701 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029267 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029267 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.033532 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033532 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16329.195937 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16329.195937 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27290.075096 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27290.075096 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26386.718961 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26386.718961 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 65808.106956 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 65808.106956 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14678.411575 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14678.411575 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27307.167434 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27307.167434 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19199.179177 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19199.179177 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19938.234282 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19938.234282 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191410.152686 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191410.152686 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189139.567712 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189139.567712 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190273.773530 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190273.773530 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19760.878778 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19760.878778 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20636.577410 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20636.577410 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194253.030687 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194253.030687 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189071.693048 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189071.693048 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 191543.803393 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191543.803393 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 6707377 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.936942 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 228724396 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6707889 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.097821 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 21622819000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.936942 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999877 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999877 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 6540239 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.944561 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 227144563 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6540751 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 34.727597 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 18012149000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.944561 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999892 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999892 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 478348155 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 478348155 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 228724396 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 228724396 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 228724396 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 228724396 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 228724396 # number of overall hits -system.cpu0.icache.overall_hits::total 228724396 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 7095721 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 7095721 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 7095721 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 7095721 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 7095721 # number of overall misses -system.cpu0.icache.overall_misses::total 7095721 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 79714633751 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 79714633751 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 79714633751 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 79714633751 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 79714633751 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 79714633751 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 235820117 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 235820117 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 235820117 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 235820117 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 235820117 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 235820117 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.030090 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.030090 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.030090 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.030090 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.030090 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.030090 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11234.183778 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 11234.183778 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11234.183778 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 11234.183778 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11234.183778 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 11234.183778 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 12261513 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1787 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 839174 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.611407 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 127.642857 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 474674738 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 474674738 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 227144563 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 227144563 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 227144563 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 227144563 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 227144563 # number of overall hits +system.cpu0.icache.overall_hits::total 227144563 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6922414 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6922414 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6922414 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6922414 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6922414 # 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number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 234066977 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 234066977 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029575 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.029575 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029575 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.029575 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029575 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.029575 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11385.580767 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 11385.580767 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11385.580767 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 11385.580767 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11385.580767 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 11385.580767 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 12205805 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1929 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 815036 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.975786 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 148.384615 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 6707377 # number of writebacks -system.cpu0.icache.writebacks::total 6707377 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 387800 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 387800 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 387800 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 387800 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 387800 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 387800 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6707921 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 6707921 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6707921 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 6707921 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6707921 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 6707921 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 6540239 # number of writebacks +system.cpu0.icache.writebacks::total 6540239 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 381630 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 381630 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 381630 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 381630 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 381630 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 381630 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6540784 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6540784 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6540784 # 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number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939780998 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939780998 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028445 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028445 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028445 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028445 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028445 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028445 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10697.205151 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10697.205151 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10697.205151 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10697.205151 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10697.205151 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10697.205151 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027944 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027944 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027944 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.027944 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027944 # 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average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.260132 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8921966 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8932201 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 9178 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 9036202 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 9047325 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 9983 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1125087 # 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number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 209837 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 6087853 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 4378244 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 11327123 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 651189 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 209837 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 6087853 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 4378244 # number of overall hits -system.cpu0.l2cache.overall_hits::total 11327123 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13609 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10441 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 24050 # 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number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 21505748998 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 21505748998 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 45049566980 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 45049566980 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 46970391994 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 46970391994 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 744149500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 659971500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 21505748998 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 63788753480 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 86698623478 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 744149500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 659971500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 21505748998 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 63788753480 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 78126139116 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 164824762594 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780082500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6029953000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8810035500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5977560967 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5977560967 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3671826500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6451909000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3917316467 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3917316467 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 2780082500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 12007513967 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14787596467 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020463 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.046591 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.026966 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7589142967 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10369225467 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021200 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049050 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027893 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.996989 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.996989 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.996400 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.996400 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999995 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.216228 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.216228 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092435 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092435 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.238746 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.238746 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.751086 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.751086 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.020463 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046591 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092435 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.233555 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.149300 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.020463 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046591 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092435 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.233555 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.214746 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.214746 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.096749 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096749 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.250243 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250243 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.786538 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.786538 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021200 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049050 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.096749 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242026 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.156382 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021200 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049050 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.096749 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242026 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.218494 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 47721.258453 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 55768.098996 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 51181.463946 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 73680.499500 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 73680.499500 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29805.846010 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29805.846010 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20120.704683 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20120.704683 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 530768.923077 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 530768.923077 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 61287.090469 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 61287.090469 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33985.476098 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33985.476098 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38663.373624 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38663.373624 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 131960.143226 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 131960.143226 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 47721.258453 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 55768.098996 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33985.476098 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43491.886454 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40638.435405 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 47721.258453 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 55768.098996 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33985.476098 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43491.886454 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 73680.499500 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 51102.429562 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226418 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 51345.442627 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62214.507919 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 55938.847058 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83589.820557 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83589.820557 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29056.933822 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29056.933822 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19793.131376 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19793.131376 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 778666.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 778666.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 63841.657979 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 63841.657979 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33984.259220 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33984.259220 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39674.714397 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39674.714397 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 72830.330151 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 72830.330151 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 51345.442627 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 62214.507919 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33984.259220 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 44638.767053 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 41543.916967 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 51345.442627 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 62214.507919 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33984.259220 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 44638.767053 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83589.820557 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 54549.702469 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183403.887098 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162633.798527 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181462.644334 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181462.644334 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186245.320822 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 157332.935037 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181306.880820 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181306.880820 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 182432.336666 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 169753.839505 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183663.100288 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 165605.542962 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 27467007 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 14098216 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2397 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 2174971 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2174417 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 554 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 1027741 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 12311555 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 32941 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 32941 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 6114023 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 8970970 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2853143 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1178619 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 8 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 489036 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 343853 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 531725 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 106 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 201 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1422561 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1350501 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6707921 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5424362 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 856015 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 848782 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20165788 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21120167 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 459340 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1399304 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 43144599 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 858918672 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 799305801 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1762224 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5318384 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1665305081 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 7537626 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 22154436 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.115021 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.319126 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 27325930 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 14061042 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2043 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 2238708 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2238208 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 500 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 1035490 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 12208665 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 21607 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 21606 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 6237038 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 8831409 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2977562 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1194066 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 497340 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 368088 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 556890 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 118 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1397051 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1373685 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6540784 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5522441 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 877204 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 819959 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19664376 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21309678 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 452328 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1442065 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 42868447 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 837525072 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 808748037 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1730136 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5469168 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1653472413 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 7780555 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 22331081 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.118319 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.323054 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 19606761 88.50% 88.50% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2547121 11.50% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 554 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 19689398 88.17% 88.17% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2641183 11.83% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 500 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 22154436 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 27362140922 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 22331081 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 27171038408 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 207113536 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 185981894 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 10089828109 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9839167037 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 9431575123 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9551310776 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 239573965 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 236496624 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 735155181 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 759104112 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 119891525 # Number of BP lookups -system.cpu1.branchPred.condPredicted 80198528 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5904198 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 84182887 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 54925615 # Number of BTB hits +system.cpu1.branchPred.lookups 126248667 # Number of BP lookups +system.cpu1.branchPred.condPredicted 84543955 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6151855 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 88859655 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 57842551 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 65.245583 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16054982 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 157154 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 65.094278 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16827370 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 172583 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1727,87 +1734,83 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 523591 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 523591 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9887 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 82113 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 242894 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 280697 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2503.193835 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 14937.525211 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 278494 99.22% 99.22% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1255 0.45% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 659 0.23% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 166 0.06% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 38 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 57 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 13 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::589824-655359 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 280697 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 263545 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 19785.484452 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17259.480271 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 16001.974136 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 261738 99.31% 99.31% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 658 0.25% 99.56% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 820 0.31% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 79 0.03% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 151 0.06% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 47 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 31 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 263545 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 427419381904 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.550644 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.560610 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 426298998404 99.74% 99.74% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 579725500 0.14% 99.87% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 235009500 0.05% 99.93% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 123480000 0.03% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 88192000 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 51481500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 16753000 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 25205500 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 518000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 18500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 427419381904 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 82114 89.25% 89.25% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 9887 10.75% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 92001 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 523591 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 548057 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 548057 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11885 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 88263 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 254796 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 293261 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2461.776370 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 15099.601662 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-131071 292248 99.65% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-262143 874 0.30% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-393215 111 0.04% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-524287 22 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::655360-786431 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::917504-1.04858e+06 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::1.04858e+06-1.17965e+06 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 293261 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 284367 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 20156.804411 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17511.621467 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 17128.200610 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 282098 99.20% 99.20% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 636 0.22% 99.43% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1232 0.43% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 88 0.03% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 184 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 74 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 33 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 13 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 284367 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 458679401608 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.570209 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.555852 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 457501852108 99.74% 99.74% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 610883500 0.13% 99.88% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 255647500 0.06% 99.93% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 124159500 0.03% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 89499500 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 56037000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 17511000 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 23464500 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 345500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 458679401608 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 88263 88.13% 88.13% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 11885 11.87% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 100148 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 548057 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 523591 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92001 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 548057 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 100148 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92001 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 615592 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 100148 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 648205 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 88459625 # DTB read hits -system.cpu1.dtb.read_misses 355289 # DTB read misses -system.cpu1.dtb.write_hits 73058314 # DTB write hits -system.cpu1.dtb.write_misses 168302 # DTB write misses -system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 92943696 # DTB read hits +system.cpu1.dtb.read_misses 375200 # DTB read misses +system.cpu1.dtb.write_hits 76575759 # DTB write hits +system.cpu1.dtb.write_misses 172857 # DTB write misses +system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 34429 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 243 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 5558 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 46180 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 35565 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 273 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6009 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 38457 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 88814914 # DTB read accesses -system.cpu1.dtb.write_accesses 73226616 # DTB write accesses +system.cpu1.dtb.perms_faults 39938 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 93318896 # DTB read accesses +system.cpu1.dtb.write_accesses 76748616 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 161517939 # DTB hits -system.cpu1.dtb.misses 523591 # DTB misses -system.cpu1.dtb.accesses 162041530 # DTB accesses +system.cpu1.dtb.hits 169519455 # DTB hits +system.cpu1.dtb.misses 548057 # DTB misses +system.cpu1.dtb.accesses 170067512 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1837,1156 +1840,1175 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 79238 # Table walker walks requested -system.cpu1.itb.walker.walksLong 79238 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 670 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55768 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 9704 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 69534 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1362.196911 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 10189.827482 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 68875 99.05% 99.05% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 429 0.62% 99.67% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 22 0.03% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 45 0.06% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 97 0.14% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 46 0.07% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 81693 # Table walker walks requested +system.cpu1.itb.walker.walksLong 81693 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 804 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 58754 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 9814 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 71879 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1351.430877 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 10594.939676 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 71238 99.11% 99.11% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 384 0.53% 99.64% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 26 0.04% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 48 0.07% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 113 0.16% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 53 0.07% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 3 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 69534 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 66142 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 24972.294457 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 22450.763423 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 20128.243900 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 65282 98.70% 98.70% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 106 0.16% 98.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 635 0.96% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 41 0.06% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 34 0.05% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 18 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 18 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 66142 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 405913969924 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.852777 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.354498 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 59781305300 14.73% 14.73% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 346114009624 85.27% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 16127000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 2369500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 82500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 76000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 405913969924 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 55768 98.81% 98.81% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 670 1.19% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 56438 # Table walker page sizes translated +system.cpu1.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::458752-491519 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 71879 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 69372 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 25253.272214 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22467.195437 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 22091.390725 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 68357 98.54% 98.54% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 80 0.12% 98.65% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 757 1.09% 99.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 76 0.11% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 55 0.08% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 15 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 11 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 69372 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 407136400556 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.838375 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.368280 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 65826877124 16.17% 16.17% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 341288268432 83.83% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 19212000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 1863000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 150500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 29500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 407136400556 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 58754 98.65% 98.65% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 804 1.35% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 59558 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 79238 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 79238 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 81693 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 81693 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56438 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56438 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 135676 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 188743149 # ITB inst hits -system.cpu1.itb.inst_misses 79238 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 59558 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 59558 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 141251 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 198485673 # ITB inst hits +system.cpu1.itb.inst_misses 81693 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 24595 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 46180 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25168 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 203696 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 206844 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 188822387 # ITB inst accesses -system.cpu1.itb.hits 188743149 # DTB hits -system.cpu1.itb.misses 79238 # DTB misses -system.cpu1.itb.accesses 188822387 # DTB accesses -system.cpu1.numCycles 668763369 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 198567366 # ITB inst accesses +system.cpu1.itb.hits 198485673 # DTB hits +system.cpu1.itb.misses 81693 # DTB misses +system.cpu1.itb.accesses 198567366 # DTB accesses +system.cpu1.numCycles 706357244 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 76762482 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 531105996 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 119891525 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 70980597 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 555217707 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 12731518 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1797928 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 295013 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 5987179 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 752221 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 763722 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 188519405 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1489379 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 27517 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 647942011 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.963740 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.217002 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 79757859 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 558826368 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 126248667 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 74669921 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 588203471 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13287396 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1859618 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 301703 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 6107940 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 765855 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 800562 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 198257766 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1531728 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 28220 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 684440706 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.958907 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.215902 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 349005233 53.86% 53.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 116425876 17.97% 71.83% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 39511198 6.10% 77.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 142999704 22.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 370240796 54.09% 54.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 122429423 17.89% 71.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 41426108 6.05% 78.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 150344379 21.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 647942011 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.179273 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.794161 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 92682171 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 320350015 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 196661442 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 33741382 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 4507001 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 16971690 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1895430 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 551371568 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 20348682 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 4507001 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 124070698 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 47114866 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 212074227 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 198637530 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 61537689 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 536563152 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5145214 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 9840770 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 223861 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 282097 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 29934469 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 10810 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 509803663 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 829081125 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 634679636 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 600803 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 459431302 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 50372361 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 14562905 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 12854163 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 68041373 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 88476596 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 76035338 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8565835 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7285035 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 516079501 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 14870100 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 521291240 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2377203 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 47872437 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 30743352 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 257935 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 647942011 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.804534 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.061029 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 684440706 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.178732 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.791138 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 96144629 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 340788757 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 207685438 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 35085697 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4736185 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 17812454 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1944962 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 579921351 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 21338656 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4736185 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 128930138 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 49237812 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 228920665 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 209565208 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 63050698 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 564205236 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5454916 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 10256691 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 240677 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 354262 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 30213880 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 11171 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 537096625 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 872562806 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 667157366 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 686134 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 483982102 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 53114517 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15098547 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13303136 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 70645723 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 92937642 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 79702799 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8581032 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7318731 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 542982721 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15290733 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 547999845 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2492376 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 50310716 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 32527030 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 258040 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 684440706 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.800653 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.060998 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 361872507 55.85% 55.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 122353667 18.88% 74.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 99252241 15.32% 90.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 57424869 8.86% 98.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7035151 1.09% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 3576 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 384384408 56.16% 56.16% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 127393239 18.61% 74.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 104776738 15.31% 90.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 60496264 8.84% 98.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7385947 1.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 4110 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 647942011 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 684440706 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 52040674 43.67% 43.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 50092 0.04% 43.71% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 18388 0.02% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 16 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 32200400 27.02% 70.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 34865580 29.26% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 55139379 44.00% 44.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 46977 0.04% 44.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 11488 0.01% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 7 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 33502933 26.74% 70.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 36611567 29.22% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 27 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 354670500 68.04% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1183955 0.23% 68.26% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 65513 0.01% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 42657 0.01% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 91135432 17.48% 85.77% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 74193108 14.23% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 373183107 68.10% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1202540 0.22% 68.32% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 67362 0.01% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 2 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 42387 0.01% 68.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 95737452 17.47% 85.81% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 77766935 14.19% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 521291240 # Type of FU issued -system.cpu1.iq.rate 0.779485 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 119175150 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.228615 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1811086365 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 578565811 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 506287229 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 990479 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 395514 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 364516 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 639849832 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 616531 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2398408 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 547999845 # Type of FU issued +system.cpu1.iq.rate 0.775811 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 125312351 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.228672 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1907132649 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 608283649 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 532258075 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1112472 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 437179 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 408398 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 672616839 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 695346 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2459057 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 11063470 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 14436 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 140383 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5257500 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 11465284 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 14564 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 137615 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5482962 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2402216 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 3864822 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2463728 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 4019009 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 4507001 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 5849706 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 2188326 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 531063111 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4736185 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6263173 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 2375395 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 558389408 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 88476596 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 76035338 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12650539 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 60907 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2070757 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 140383 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1813068 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2483133 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4296201 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 514538937 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 88454625 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6240485 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 92937642 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 79702799 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 13061254 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 63231 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2253383 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 137615 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1902304 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2611236 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4513540 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 540870869 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 92937926 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6592838 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 113510 # number of nop insts executed -system.cpu1.iew.exec_refs 161513914 # number of memory reference insts executed -system.cpu1.iew.exec_branches 96416033 # Number of branches executed -system.cpu1.iew.exec_stores 73059289 # Number of stores executed -system.cpu1.iew.exec_rate 0.769389 # Inst execution rate -system.cpu1.iew.wb_sent 507314383 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 506651745 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 244576343 # num instructions producing a value -system.cpu1.iew.wb_consumers 400655745 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.757595 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.610440 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 41944033 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14612165 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4045440 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 639995571 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.754813 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.555930 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 115954 # number of nop insts executed +system.cpu1.iew.exec_refs 169513519 # number of memory reference insts executed +system.cpu1.iew.exec_branches 101590895 # Number of branches executed +system.cpu1.iew.exec_stores 76575593 # Number of stores executed +system.cpu1.iew.exec_rate 0.765719 # Inst execution rate +system.cpu1.iew.wb_sent 533377466 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 532666473 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 257434056 # num instructions producing a value +system.cpu1.iew.wb_consumers 422362739 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.754104 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.609509 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 44033715 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 15032693 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4244342 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 676109975 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.751302 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.553770 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 426913272 66.71% 66.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 112061055 17.51% 84.22% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 46474767 7.26% 91.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 15512784 2.42% 93.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 11149430 1.74% 95.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 7505688 1.17% 96.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5285555 0.83% 97.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3055428 0.48% 98.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 12037592 1.88% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 452513238 66.93% 66.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 117033560 17.31% 84.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 49159205 7.27% 91.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 16297256 2.41% 93.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 11766410 1.74% 95.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 7925929 1.17% 96.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5496145 0.81% 97.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3299018 0.49% 98.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12619214 1.87% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 639995571 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 409938912 # Number of instructions committed -system.cpu1.commit.committedOps 483077163 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 676109975 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 431347574 # Number of instructions committed +system.cpu1.commit.committedOps 507962731 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 148190964 # Number of memory references committed -system.cpu1.commit.loads 77413126 # Number of loads committed -system.cpu1.commit.membars 3553266 # Number of memory barriers committed -system.cpu1.commit.branches 91478423 # Number of branches committed -system.cpu1.commit.fp_insts 356192 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 443462583 # Number of committed integer instructions. -system.cpu1.commit.function_calls 11919697 # Number of function calls committed. +system.cpu1.commit.refs 155692194 # Number of memory references committed +system.cpu1.commit.loads 81472357 # Number of loads committed +system.cpu1.commit.membars 3613840 # Number of memory barriers committed +system.cpu1.commit.branches 96395557 # Number of branches committed +system.cpu1.commit.fp_insts 400161 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 466077725 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12507771 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 333838399 69.11% 69.11% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 958189 0.20% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 52064 0.01% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 37505 0.01% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 77413126 16.03% 85.35% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 70777838 14.65% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 351213617 69.14% 69.14% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 966298 0.19% 69.33% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 53161 0.01% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 37419 0.01% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 81472357 16.04% 85.39% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 74219837 14.61% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 483077163 # Class of committed instruction -system.cpu1.commit.bw_lim_events 12037592 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1149378464 # The number of ROB reads -system.cpu1.rob.rob_writes 1057951201 # The number of ROB writes -system.cpu1.timesIdled 862725 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 20821358 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94039702456 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 409938912 # Number of Instructions Simulated -system.cpu1.committedOps 483077163 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.631373 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.631373 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.612981 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.612981 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 608507800 # number of integer regfile reads -system.cpu1.int_regfile_writes 359700181 # number of integer regfile writes -system.cpu1.fp_regfile_reads 588843 # number of floating regfile reads -system.cpu1.fp_regfile_writes 298828 # number of floating regfile writes -system.cpu1.cc_regfile_reads 110183943 # number of cc regfile reads -system.cpu1.cc_regfile_writes 110950246 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1143200959 # number of misc regfile reads -system.cpu1.misc_regfile_writes 14699928 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 4943818 # number of replacements -system.cpu1.dcache.tags.tagsinuse 455.490717 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 138046990 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4944322 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.920307 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8486298300000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.490717 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.889630 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.889630 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 504 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 434 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.984375 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 307427480 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 307427480 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 71852716 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 71852716 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 61790747 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 61790747 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 162379 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 162379 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 50057 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 50057 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1706960 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1706960 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1722622 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1722622 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 133643463 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 133643463 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 133805842 # number of overall hits -system.cpu1.dcache.overall_hits::total 133805842 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 5820950 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 5820950 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 6630483 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 6630483 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 628859 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 628859 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 401328 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 401328 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 243245 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 243245 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 186259 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 186259 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 12451433 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 12451433 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 13080292 # number of overall misses -system.cpu1.dcache.overall_misses::total 13080292 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96708932500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 96708932500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 144491403356 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 144491403356 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16631824083 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 16631824083 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3760760000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 3760760000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5141971500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5141971500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6754500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 6754500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 241200335856 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 241200335856 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 241200335856 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 241200335856 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 77673666 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 77673666 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 68421230 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 68421230 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 791238 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 791238 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 451385 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 451385 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1950205 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1950205 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1908881 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1908881 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 146094896 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 146094896 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 146886134 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 146886134 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074941 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.074941 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.096907 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.096907 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.794779 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.794779 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.889104 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.889104 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124728 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124728 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097575 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097575 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085228 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.085228 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089051 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.089051 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16613.943171 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16613.943171 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21791.987606 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21791.987606 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 41441.972858 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 41441.972858 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15460.790561 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15460.790561 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27606.566663 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27606.566663 # average StoreCondReq miss latency +system.cpu1.commit.op_class_0::total 507962731 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12619214 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1211577193 # The number of ROB reads +system.cpu1.rob.rob_writes 1112287280 # The number of ROB writes +system.cpu1.timesIdled 906823 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 21916538 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94073218429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 431347574 # Number of Instructions Simulated +system.cpu1.committedOps 507962731 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.637559 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.637559 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.610665 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.610665 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 639350275 # number of integer regfile reads +system.cpu1.int_regfile_writes 378298878 # number of integer regfile writes +system.cpu1.fp_regfile_reads 675031 # number of floating regfile reads +system.cpu1.fp_regfile_writes 302028 # number of floating regfile writes +system.cpu1.cc_regfile_reads 116956107 # number of cc regfile reads +system.cpu1.cc_regfile_writes 117682636 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1203449961 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15173732 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 5181385 # number of replacements +system.cpu1.dcache.tags.tagsinuse 448.144658 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 145015910 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5181896 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.985106 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8482612216500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 448.144658 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.875283 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.875283 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 322931039 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 322931039 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 75698887 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 75698887 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 64698314 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 64698314 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 177630 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 177630 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 137318 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 137318 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1768516 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1768516 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1769874 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1769874 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 140397201 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 140397201 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 140574831 # number of overall hits +system.cpu1.dcache.overall_hits::total 140574831 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 6071314 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 6071314 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 6974888 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 6974888 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 655927 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 655927 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 434582 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 434582 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 243161 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 243161 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 198274 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 198274 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 13046202 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 13046202 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 13702129 # number of overall misses +system.cpu1.dcache.overall_misses::total 13702129 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 101097830500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 101097830500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 149656092437 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 149656092437 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16022463739 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 16022463739 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3928870000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3928870000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5496174000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5496174000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4605500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4605500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 250753922937 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 250753922937 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 250753922937 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 250753922937 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 81770201 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 81770201 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 71673202 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 71673202 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 833557 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 833557 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 571900 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 571900 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2011677 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2011677 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1968148 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1968148 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 153443403 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 153443403 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 154276960 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 154276960 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074248 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.074248 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.097315 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.097315 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.786901 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.786901 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.759892 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.759892 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120875 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120875 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100741 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100741 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085023 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.085023 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.088815 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.088815 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16651.721604 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16651.721604 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21456.415133 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21456.415133 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 36868.677808 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 36868.677808 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16157.484136 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16157.484136 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27720.094415 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27720.094415 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19371.291309 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19371.291309 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18439.980992 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18439.980992 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 4381553 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 22968096 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 326353 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 670571 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.425809 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 34.251550 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19220.453810 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19220.453810 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18300.362151 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18300.362151 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 4223664 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 23883166 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 349910 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 702949 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.070715 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 33.975674 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 4943833 # number of writebacks -system.cpu1.dcache.writebacks::total 4943833 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 2977175 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 2977175 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5355618 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 5355618 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3078 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 3078 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 125917 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 125917 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 8332793 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 8332793 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 8332793 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 8332793 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2843775 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2843775 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1274865 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1274865 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 628773 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 628773 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 398250 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 398250 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 117328 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 117328 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 186249 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 186249 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4118640 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4118640 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4747413 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4747413 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5429 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5429 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5284 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5284 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10713 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10713 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43326231000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43326231000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 30961849442 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 30961849442 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15267610500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15267610500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 16078596583 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 16078596583 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1709363500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1709363500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4955815500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4955815500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6661500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6661500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 74288080442 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 74288080442 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 89555690942 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 89555690942 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 604887500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 604887500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 670175500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 670175500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1275063000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1275063000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036612 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036612 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018633 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018633 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.794670 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.794670 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.882285 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.882285 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060162 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060162 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097570 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097570 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028192 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028192 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032320 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032320 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15235.463776 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15235.463776 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24286.374982 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24286.374982 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24281.593675 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24281.593675 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40373.123874 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 40373.123874 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14569.101152 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14569.101152 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26608.548234 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26608.548234 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5181409 # number of writebacks +system.cpu1.dcache.writebacks::total 5181409 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3107506 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3107506 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5642769 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5642769 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3498 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 3498 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 127094 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 127094 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 8750275 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 8750275 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 8750275 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 8750275 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2963808 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2963808 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1332119 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1332119 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 655846 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 655846 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 431084 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 431084 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116067 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116067 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 198274 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 198274 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4295927 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4295927 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4951773 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4951773 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 18536 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 18536 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 16538 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 16538 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 35074 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 35074 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 45006607000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 45006607000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 31827699093 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 31827699093 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16353139500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16353139500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 15385116239 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 15385116239 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1766523500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1766523500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5297954000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5297954000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4551500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4551500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 76834306093 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 76834306093 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 93187445593 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 93187445593 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3073252500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3073252500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2816431000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2816431000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5889683500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5889683500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036246 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036246 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018586 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018586 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.786804 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.786804 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.753775 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.753775 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.057697 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.057697 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100741 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100741 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027997 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027997 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032097 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032097 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15185.398987 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15185.398987 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23892.534445 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23892.534445 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24934.419818 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24934.419818 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 35689.369680 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 35689.369680 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15219.860081 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15219.860081 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26720.366765 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26720.366765 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18037.041461 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18037.041461 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18864.103659 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18864.103659 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 111417.848591 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 111417.848591 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 126831.093868 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 126831.093868 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 119020.162419 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 119020.162419 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17885.384480 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17885.384480 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18819.005959 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18819.005959 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165799.120630 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165799.120630 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 170300.580481 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170300.580481 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 167921.637110 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 167921.637110 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5253385 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.776230 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 182951519 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5253897 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 34.822060 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8525973531000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.776230 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980032 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.980032 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 5433139 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.652394 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 192499091 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5433651 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 35.427209 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8522355919000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.652394 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979790 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.979790 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 104 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 382279380 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 382279380 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 182951519 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 182951519 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 182951519 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 182951519 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 182951519 # number of overall hits -system.cpu1.icache.overall_hits::total 182951519 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5561220 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5561220 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5561220 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5561220 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5561220 # number of overall misses -system.cpu1.icache.overall_misses::total 5561220 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 62243274721 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 62243274721 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 62243274721 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 62243274721 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 62243274721 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 62243274721 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 188512739 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 188512739 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 188512739 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 188512739 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 188512739 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 188512739 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029500 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.029500 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029500 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.029500 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029500 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.029500 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11192.377701 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 11192.377701 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11192.377701 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 11192.377701 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11192.377701 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 11192.377701 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 9679381 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 762 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 668024 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.489571 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 127 # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 401935440 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 401935440 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 192499091 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 192499091 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 192499091 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 192499091 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 192499091 # number of overall hits +system.cpu1.icache.overall_hits::total 192499091 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5751797 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5751797 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5751797 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5751797 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5751797 # number of overall misses +system.cpu1.icache.overall_misses::total 5751797 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 64772051533 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 64772051533 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 64772051533 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 64772051533 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 64772051533 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 64772051533 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 198250888 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 198250888 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 198250888 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 198250888 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 198250888 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 198250888 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029013 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.029013 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029013 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.029013 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029013 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.029013 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11261.185249 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 11261.185249 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11261.185249 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 11261.185249 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11261.185249 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 11261.185249 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 9932539 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 584 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 679779 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.611424 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 83.428571 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 5253385 # number of writebacks -system.cpu1.icache.writebacks::total 5253385 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 307318 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 307318 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 307318 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 307318 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 307318 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 307318 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5253902 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5253902 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5253902 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5253902 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5253902 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5253902 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 5433139 # number of writebacks +system.cpu1.icache.writebacks::total 5433139 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 318133 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 318133 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 318133 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 318133 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 318133 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 318133 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5433664 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5433664 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5433664 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5433664 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5433664 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5433664 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 56076616223 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 56076616223 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 56076616223 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 56076616223 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 56076616223 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 56076616223 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9266998 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9266998 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9266998 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 9266998 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027870 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027870 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027870 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.027870 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027870 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.027870 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10673.327409 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10673.327409 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10673.327409 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10673.327409 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10673.327409 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10673.327409 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 138313.402985 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 138313.402985 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 138313.402985 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 138313.402985 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 58335043744 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 58335043744 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 58335043744 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 58335043744 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58335043744 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 58335043744 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9645998 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9645998 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9645998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 9645998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027408 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027408 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027408 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.027408 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027408 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.027408 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10735.857746 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10735.857746 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10735.857746 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10735.857746 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10735.857746 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10735.857746 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 143970.119403 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 143970.119403 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 143970.119403 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 143970.119403 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6897065 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6901426 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 4002 # 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mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025585 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for WritebackDirty accesses system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000002 # mshr miss rate for WritebackDirty accesses +system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses +system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997593 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997593 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997423 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997423 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.235701 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.235701 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.097211 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097211 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.261133 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.261133 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.562593 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.562593 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020902 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.043972 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.097211 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.255366 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.161372 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020902 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.043972 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.097211 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.255366 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.220198 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.220198 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.100533 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.100533 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.259697 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.259697 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.564482 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.564482 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020118 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.041734 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.100533 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.250625 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.161131 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020118 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.041734 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.100533 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.250625 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.228955 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 38188.145684 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38104.963680 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38153.236460 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 56526.199996 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 56526.199996 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 30720.803520 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30720.803520 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19094.913466 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19094.913466 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 541954.363636 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 541954.363636 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46776.544018 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46776.544018 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32126.941549 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32126.941549 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33480.096542 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33480.096542 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 56378.079768 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 56378.079768 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 38188.145684 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38104.963680 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32126.941549 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36262.720911 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35052.548527 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 38188.145684 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38104.963680 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32126.941549 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36262.720911 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 56526.199996 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 41391.104169 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 130798.507463 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 103397.034445 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 103731.077147 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 119313.304315 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 119313.304315 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 130798.507463 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 111247.456361 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 111368.970315 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.227681 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41427.194120 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 42816.625616 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 42000.330201 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 61725.447981 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 61725.447981 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31534.767177 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31534.767177 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19207.062102 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19207.062102 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 829199.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 829199.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46834.031226 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46834.031226 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31709.187167 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31709.187167 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 34078.669100 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34078.669100 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 47809.112331 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 47809.112331 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41427.194120 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 42816.625616 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31709.187167 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36652.754938 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35194.853490 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41427.194120 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 42816.625616 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31709.187167 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36652.754938 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 61725.447981 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42949.626773 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 136455.223881 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 157792.808589 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 157715.959791 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162796.257105 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162796.257105 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 136455.223881 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 160152.021440 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 160106.841012 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 21246355 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10958434 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1131 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1866438 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1866138 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 300 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 825754 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9752282 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 5284 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5284 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4201386 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 7090370 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2466487 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 905169 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 447608 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337242 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 479463 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 119 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 201 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1130462 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1058321 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5253902 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4579290 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 402900 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 396573 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15761317 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16025111 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 394044 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1160504 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 33340976 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 672467056 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 619232766 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1502776 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4371544 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1297574142 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 6151657 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 17448758 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.126682 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.332668 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 22091106 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11384004 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1413 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1936993 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1936645 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 348 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 874786 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10136227 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 16538 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 16538 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4413805 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 7327056 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2612396 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 936034 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 441152 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 362021 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 491027 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 69 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 118 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1142611 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1118724 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5433664 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4777910 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 490221 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 429103 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16300596 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16818339 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 407716 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1217877 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 34744528 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 695476144 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 648316997 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1556520 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4598760 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1349948421 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 6442205 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 18213720 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.125270 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.331082 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 15238612 87.33% 87.33% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2209846 12.66% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 300 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 15932436 87.47% 87.47% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2280936 12.52% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 348 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 17448758 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 21067285470 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 18213720 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 21942621967 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 170823638 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 185589939 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7886135987 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8156255052 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7380840948 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7729530656 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 206620146 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 213583628 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 614769571 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 643750548 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40283 # Transaction distribution -system.iobus.trans_dist::ReadResp 40283 # Transaction distribution -system.iobus.trans_dist::WriteReq 136631 # Transaction distribution -system.iobus.trans_dist::WriteResp 136631 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47650 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40360 # Transaction distribution +system.iobus.trans_dist::ReadResp 40360 # Transaction distribution +system.iobus.trans_dist::WriteReq 136653 # Transaction distribution +system.iobus.trans_dist::WriteResp 136653 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47814 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2997,15 +3019,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122584 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122696 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231250 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231250 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353828 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47670 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47834 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -3016,103 +3038,103 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155691 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338672 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338672 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155826 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339016 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339016 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496449 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36944000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496928 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 37078503 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 334500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 13500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 24787502 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 24630000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36442000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36390000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 567400129 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 567310169 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92684000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92774000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147860000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147946000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115578 # number of replacements -system.iocache.tags.tagsinuse 11.298905 # Cycle average of tags in use +system.iocache.tags.replacements 115606 # number of replacements +system.iocache.tags.tagsinuse 11.303294 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115594 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115622 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9125697698000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.418105 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.880800 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463632 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.242550 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706182 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9121340835000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.838171 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.465123 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239886 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466570 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706456 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040595 # Number of tag accesses -system.iocache.tags.data_accesses 1040595 # Number of data accesses +system.iocache.tags.tag_accesses 1040982 # Number of tag accesses +system.iocache.tags.data_accesses 1040982 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8854 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8891 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8897 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8934 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8854 # number of demand (read+write) misses -system.iocache.demand_misses::total 8894 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8897 # number of demand (read+write) misses +system.iocache.demand_misses::total 8937 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8854 # number of overall misses -system.iocache.overall_misses::total 8894 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5230500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1713293012 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1718523512 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8897 # number of overall misses +system.iocache.overall_misses::total 8937 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5248000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1663076066 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1668324066 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13529785617 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13529785617 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5599500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1713293012 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1718892512 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5599500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1713293012 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1718892512 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13545989103 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13545989103 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5617000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1663076066 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1668693066 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5617000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1663076066 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1668693066 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8854 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8891 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8897 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8934 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8854 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8894 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8897 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8937 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8854 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8894 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8897 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8937 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3126,55 +3148,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141364.864865 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 193504.970861 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 193287.989203 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141837.837838 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 186925.487917 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 186738.758227 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126768.848072 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126768.848072 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139987.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 193504.970861 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 193264.280639 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139987.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 193504.970861 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 193264.280639 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34686 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126920.668456 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126920.668456 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 140425 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 186925.487917 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 186717.362202 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 140425 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 186925.487917 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 186717.362202 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33278 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3488 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3432 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.944381 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.696387 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8854 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8891 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8897 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8934 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8854 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8894 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8897 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8937 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8854 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8894 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3380500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1270593012 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1273973512 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8897 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8937 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3398000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1218226066 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1221624066 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8187257903 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8187257903 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3599500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1270593012 # 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number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1218226066 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1221843066 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3188,624 +3210,651 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91364.864865 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 143504.970861 # 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average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 143264.280639 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89987.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 143504.970861 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 143264.280639 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76860.809563 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76860.809563 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90425 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 136925.487917 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 136717.362202 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90425 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 136925.487917 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 136717.362202 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1550465 # number of replacements -system.l2c.tags.tagsinuse 63029.233494 # Cycle average of tags in use -system.l2c.tags.total_refs 6222316 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1609843 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.865169 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 21079.795710 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 246.485529 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 359.766358 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4048.838393 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9854.606144 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 15763.557433 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 96.147248 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 123.490081 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3067.505167 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 4557.367994 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3831.673436 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.321652 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003761 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.005490 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.061780 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.150369 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.240533 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001467 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.001884 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.046806 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.069540 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.058467 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.961750 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10787 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 260 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 48331 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1394 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 453 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 8932 # Occupied blocks per task id +system.l2c.tags.replacements 1667118 # number of replacements +system.l2c.tags.tagsinuse 63361.638008 # Cycle average of tags in use +system.l2c.tags.total_refs 6455366 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1727204 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.737466 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 4891044000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 22165.641734 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 239.050229 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 385.051566 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4239.404809 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 8813.325361 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14013.639467 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 94.428510 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 121.397759 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2981.044706 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 5621.582558 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4687.071308 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.338221 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003648 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.005875 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.064688 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.134481 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.213831 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001441 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.001852 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.045487 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.085779 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.071519 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.966822 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 9996 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 251 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49839 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 1469 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 415 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 8111 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 256 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2970 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5917 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 39033 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.164597 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.737473 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 79030194 # Number of tag accesses -system.l2c.tags.data_accesses 79030194 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 2899125 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2899125 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 179542 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 131751 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 311293 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 44871 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 37587 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 82458 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 177447 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 158953 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 336400 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6841 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4759 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 555678 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 657090 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 315358 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6220 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4455 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 465798 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 550752 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 288275 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2855226 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6841 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4759 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 555678 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 834537 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 315358 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6220 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4455 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 465798 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 709705 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 288275 # number of demand (read+write) hits -system.l2c.demand_hits::total 3191626 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6841 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4759 # number of overall hits -system.l2c.overall_hits::cpu0.inst 555678 # number of overall hits -system.l2c.overall_hits::cpu0.data 834537 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 315358 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6220 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4455 # number of overall hits -system.l2c.overall_hits::cpu1.inst 465798 # number of overall hits -system.l2c.overall_hits::cpu1.data 709705 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 288275 # number of overall hits -system.l2c.overall_hits::total 3191626 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 65170 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 60899 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 126069 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 13497 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 10880 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 24377 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 548373 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 111880 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 660253 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3162 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3066 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 64369 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 165419 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 348485 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1778 # 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mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.459585 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.102284 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.209765 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.566771 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.235417 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.259333 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.083711 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.160901 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.417816 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.255793 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.804259 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.438944 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.707217 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.351978 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.459585 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102284 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.273646 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.566771 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.235417 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.259333 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.083711 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.202746 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.417816 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.275132 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.351978 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.459585 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102284 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.273646 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.566771 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.235417 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.259333 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.083711 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.202746 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.417816 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.275132 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70448.531555 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70759.533394 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70604.730311 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73634.273785 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73691.039349 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73660.634044 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 133387.815570 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 127291.827027 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 131293.474083 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130444.744844 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 132053.640348 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127934.727208 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 137013.813278 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177768.128110 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 136025.584071 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 135853.198726 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127776.483314 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 136612.753688 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174711.416846 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 159370.250555 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70113.311234 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 70257.085725 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 70137.015467 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130444.744844 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 132053.640348 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127934.727208 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135746.754803 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177768.128110 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 136025.584071 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 135853.198726 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127776.483314 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 133739.131074 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174711.416846 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 155806.340709 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130444.744844 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 132053.640348 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127934.727208 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135746.754803 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177768.128110 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 136025.584071 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 135853.198726 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127776.483314 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 133739.131074 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174711.416846 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 155806.340709 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165399.143105 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112791.044776 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 85408.885941 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 139208.448018 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164446.132935 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 102249.341030 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155848.412897 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168235.634593 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 118447.761194 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 139802.229848 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 139452.164338 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164282.633343 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145775.972367 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156258.745989 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164922.181923 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112791.044776 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 93716.697040 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 145706.176668 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 166168.682074 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 118447.761194 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 142619.113794 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 146010.226499 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 59665 # Transaction distribution -system.membus.trans_dist::ReadResp 1004280 # Transaction distribution -system.membus.trans_dist::WriteReq 38225 # Transaction distribution -system.membus.trans_dist::WriteResp 38225 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1333923 # Transaction distribution -system.membus.trans_dist::CleanEvict 260984 # Transaction distribution -system.membus.trans_dist::UpgradeReq 453995 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 297100 # Transaction distribution +system.membus.trans_dist::ReadReq 59609 # Transaction distribution +system.membus.trans_dist::ReadResp 1087641 # Transaction distribution +system.membus.trans_dist::WriteReq 38144 # Transaction distribution +system.membus.trans_dist::WriteResp 38144 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1427135 # Transaction distribution +system.membus.trans_dist::CleanEvict 277667 # Transaction distribution +system.membus.trans_dist::UpgradeReq 445891 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 321137 # Transaction distribution system.membus.trans_dist::UpgradeResp 23 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 671706 # Transaction distribution -system.membus.trans_dist::ReadExResp 651282 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 944615 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 156981 # Transaction distribution +system.membus.trans_dist::ReadExResp 142959 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1028032 # Transaction distribution +system.membus.trans_dist::InvalidateReq 712467 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122696 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25256 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5471994 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5619910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238072 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238072 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5857982 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155691 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24870 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5347246 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5494888 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237811 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237811 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5732699 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155826 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50512 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 180426240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 180632999 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7268224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7268224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 187901223 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 614880 # Total snoops (count) -system.membus.snoop_fanout::samples 4166995 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49740 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159196224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 159402346 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7246976 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7246976 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 166649322 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 621233 # Total snoops (count) +system.membus.snoop_fanout::samples 4467120 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4166995 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4467120 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4166995 # Request fanout histogram -system.membus.reqLayer0.occupancy 98592998 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4467120 # Request fanout histogram +system.membus.reqLayer0.occupancy 98530997 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 53000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21315973 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20867984 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9342770498 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9912231208 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8446463151 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6259994034 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45344986 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45597361 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3859,57 +3908,58 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 12162467 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6606326 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1941011 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 162574 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 148386 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 14188 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 59667 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4643440 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38225 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38225 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 4233094 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2736996 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 756317 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 379558 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1135875 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 201 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 201 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1140134 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1140134 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4591007 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10341744 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7350795 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17692539 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 299067465 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 193620382 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 492687847 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3308925 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8737988 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.345814 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.479035 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 12663754 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6874752 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2026071 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 169438 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 153466 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 15972 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 59611 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4844529 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38144 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38144 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 4439938 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2880952 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 762470 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 404798 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1167268 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 118 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 118 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 311901 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 311901 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4792157 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 968815 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 862087 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10699681 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7828066 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 18527747 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 272166853 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 192849765 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 465016618 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3356905 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9121086 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.343228 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.478461 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5730454 65.58% 65.58% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2993346 34.26% 99.84% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 14188 0.16% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 6006442 65.85% 65.85% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3098672 33.97% 99.82% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 15972 0.18% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8737988 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9497901955 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 9121086 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9875342461 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2589298 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2628126 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 5324917465 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4863215068 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3923923162 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3891669395 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 12950 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 5261 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5465 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 13576 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index 5a29e8890..a4f8f5e6d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,141 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.331525 # Number of seconds simulated -sim_ticks 51331524771000 # Number of ticks simulated -final_tick 51331524771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.327140 # Number of seconds simulated +sim_ticks 51327140089000 # Number of ticks simulated +final_tick 51327140089000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185259 # Simulator instruction rate (inst/s) -host_op_rate 217677 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11233724737 # Simulator tick rate (ticks/s) -host_mem_usage 689476 # Number of bytes of host memory used -host_seconds 4569.41 # Real time elapsed on the host -sim_insts 846524467 # Number of instructions simulated -sim_ops 994654061 # Number of ops (including micro ops) simulated +host_inst_rate 210997 # Simulator instruction rate (inst/s) +host_op_rate 247928 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12768702843 # Simulator tick rate (ticks/s) +host_mem_usage 688028 # Number of bytes of host memory used +host_seconds 4019.76 # Real time elapsed on the host +sim_insts 848158120 # Number of instructions simulated +sim_ops 996609834 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 205568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 197440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5696288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 72187912 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 428288 # Number of bytes read from this memory -system.physmem.bytes_read::total 78715496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5696288 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5696288 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67280640 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 211968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 207872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5637664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 41611720 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 447104 # Number of bytes read from this memory +system.physmem.bytes_read::total 48116328 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5637664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5637664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 68318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 67301220 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3212 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3085 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 104957 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1127949 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6692 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1245895 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1051260 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 68338916 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3312 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3248 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 104041 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 650196 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6986 # Number of read requests responded to by this memory +system.physmem.num_reads::total 767783 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1067474 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1053833 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 4005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 3846 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 110971 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1406308 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1533473 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 110971 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 110971 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1310708 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1070047 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 4130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 4050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 109838 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 810716 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 937444 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 109838 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 109838 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1331037 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1311109 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1310708 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 3846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 110971 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1406708 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2844582 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1245895 # Number of read requests accepted -system.physmem.writeReqs 1053833 # Number of write requests accepted -system.physmem.readBursts 1245895 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1053833 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 79684928 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 52352 # Total number of bytes read from write queue -system.physmem.bytesWritten 67299776 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 78715496 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 67301220 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 818 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1331438 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1331037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4130 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 4050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 109838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 811117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2268882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 767783 # Number of read requests accepted +system.physmem.writeReqs 1070047 # Number of write requests accepted +system.physmem.readBursts 767783 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1070047 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 49097152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 40960 # Total number of bytes read from write queue +system.physmem.bytesWritten 68336896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 48116328 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 68338916 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 640 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2264 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 74822 # Per bank write bursts -system.physmem.perBankRdBursts::1 82180 # Per bank write bursts -system.physmem.perBankRdBursts::2 80987 # Per bank write bursts -system.physmem.perBankRdBursts::3 75462 # Per bank write bursts -system.physmem.perBankRdBursts::4 75477 # Per bank write bursts -system.physmem.perBankRdBursts::5 80130 # Per bank write bursts -system.physmem.perBankRdBursts::6 74577 # Per bank write bursts -system.physmem.perBankRdBursts::7 72890 # Per bank write bursts -system.physmem.perBankRdBursts::8 72311 # Per bank write bursts -system.physmem.perBankRdBursts::9 102827 # Per bank write bursts -system.physmem.perBankRdBursts::10 78128 # Per bank write bursts -system.physmem.perBankRdBursts::11 79408 # Per bank write bursts -system.physmem.perBankRdBursts::12 72963 # Per bank write bursts -system.physmem.perBankRdBursts::13 76387 # Per bank write bursts -system.physmem.perBankRdBursts::14 73944 # Per bank write bursts -system.physmem.perBankRdBursts::15 72584 # Per bank write bursts -system.physmem.perBankWrBursts::0 62047 # Per bank write bursts -system.physmem.perBankWrBursts::1 68427 # Per bank write bursts -system.physmem.perBankWrBursts::2 68519 # Per bank write bursts -system.physmem.perBankWrBursts::3 66050 # Per bank write bursts -system.physmem.perBankWrBursts::4 65357 # Per bank write bursts -system.physmem.perBankWrBursts::5 67435 # Per bank write bursts -system.physmem.perBankWrBursts::6 63960 # Per bank write bursts -system.physmem.perBankWrBursts::7 63937 # Per bank write bursts -system.physmem.perBankWrBursts::8 63039 # Per bank write bursts -system.physmem.perBankWrBursts::9 70105 # Per bank write bursts -system.physmem.perBankWrBursts::10 66227 # Per bank write bursts -system.physmem.perBankWrBursts::11 68082 # Per bank write bursts -system.physmem.perBankWrBursts::12 64306 # Per bank write bursts -system.physmem.perBankWrBursts::13 66291 # Per bank write bursts -system.physmem.perBankWrBursts::14 64522 # Per bank write bursts -system.physmem.perBankWrBursts::15 63255 # Per bank write bursts +system.physmem.perBankRdBursts::0 44980 # Per bank write bursts +system.physmem.perBankRdBursts::1 51602 # Per bank write bursts +system.physmem.perBankRdBursts::2 47368 # Per bank write bursts +system.physmem.perBankRdBursts::3 43602 # Per bank write bursts +system.physmem.perBankRdBursts::4 45132 # Per bank write bursts +system.physmem.perBankRdBursts::5 50541 # Per bank write bursts +system.physmem.perBankRdBursts::6 45264 # Per bank write bursts +system.physmem.perBankRdBursts::7 48215 # Per bank write bursts +system.physmem.perBankRdBursts::8 45181 # Per bank write bursts +system.physmem.perBankRdBursts::9 71916 # Per bank write bursts +system.physmem.perBankRdBursts::10 43746 # Per bank write bursts +system.physmem.perBankRdBursts::11 51986 # Per bank write bursts +system.physmem.perBankRdBursts::12 43936 # Per bank write bursts +system.physmem.perBankRdBursts::13 46943 # Per bank write bursts +system.physmem.perBankRdBursts::14 42923 # Per bank write bursts +system.physmem.perBankRdBursts::15 43808 # Per bank write bursts +system.physmem.perBankWrBursts::0 64378 # Per bank write bursts +system.physmem.perBankWrBursts::1 68822 # Per bank write bursts +system.physmem.perBankWrBursts::2 67360 # Per bank write bursts +system.physmem.perBankWrBursts::3 65401 # Per bank write bursts +system.physmem.perBankWrBursts::4 67058 # Per bank write bursts +system.physmem.perBankWrBursts::5 69359 # Per bank write bursts +system.physmem.perBankWrBursts::6 64813 # Per bank write bursts +system.physmem.perBankWrBursts::7 68136 # Per bank write bursts +system.physmem.perBankWrBursts::8 65855 # Per bank write bursts +system.physmem.perBankWrBursts::9 70723 # Per bank write bursts +system.physmem.perBankWrBursts::10 64194 # Per bank write bursts +system.physmem.perBankWrBursts::11 71056 # Per bank write bursts +system.physmem.perBankWrBursts::12 64787 # Per bank write bursts +system.physmem.perBankWrBursts::13 67120 # Per bank write bursts +system.physmem.perBankWrBursts::14 64460 # Per bank write bursts +system.physmem.perBankWrBursts::15 64242 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 38 # Number of times write queue was full causing retry -system.physmem.totGap 51331523357500 # Total gap between requests +system.physmem.numWrRetry 33 # Number of times write queue was full causing retry +system.physmem.totGap 51327138675500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1224610 # Read request sizes (log2) +system.physmem.readPktSize::6 746498 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1051260 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 635913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 326498 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 150136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 126962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 653 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 332 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 170 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 71 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1067474 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 514277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 203743 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 584 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 567 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1290 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 814 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 357 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 141 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 138 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -159,168 +159,168 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 11720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 15352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 33279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 54389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 62052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 63406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 64510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 63581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 65005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 68339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 65443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 80751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 86913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 66052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 69586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 62814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 93 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 477001 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 308.142583 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 177.284446 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 336.100691 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 186993 39.20% 39.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 111432 23.36% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 45372 9.51% 72.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23464 4.92% 76.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18197 3.81% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11652 2.44% 83.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10522 2.21% 85.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8218 1.72% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 61151 12.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 477001 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59594 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.891952 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 270.280066 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 59591 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59594 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59594 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.645384 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.994879 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.954134 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 56960 95.58% 95.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 905 1.52% 97.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 37 0.06% 97.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 115 0.19% 97.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 18 0.03% 97.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 110 0.18% 97.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 195 0.33% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 24 0.04% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 355 0.60% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 71 0.12% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 24 0.04% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 56 0.09% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 280 0.47% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 26 0.04% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 33 0.06% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 125 0.21% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 203 0.34% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 8 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 11 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::15 26644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 32364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 54414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 60551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 69991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 63900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 76806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 64795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 68451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 60364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 58974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 57166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 80 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 471185 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 249.230345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 149.487407 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 290.645433 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 207601 44.06% 44.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 122052 25.90% 69.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 43152 9.16% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 22522 4.78% 83.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14798 3.14% 87.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9568 2.03% 89.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7612 1.62% 90.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6084 1.29% 91.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 37796 8.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 471185 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 54136 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.170570 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 76.787361 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 54130 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 54136 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 54136 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.723733 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.769647 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.988954 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 40635 75.06% 75.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 4496 8.31% 83.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 5195 9.60% 92.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1325 2.45% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 409 0.76% 96.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 232 0.43% 96.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 326 0.60% 97.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 142 0.26% 97.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 398 0.74% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 127 0.23% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 56 0.10% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 67 0.12% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 319 0.59% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 37 0.07% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 24 0.04% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 111 0.21% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 168 0.31% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 5 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 17 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59594 # Writes before turning the bus around for reads -system.physmem.totQLat 31834686171 # Total ticks spent queuing -system.physmem.totMemAccLat 55179879921 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6225385000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25568.45 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 54136 # Writes before turning the bus around for reads +system.physmem.totQLat 15242803686 # Total ticks spent queuing +system.physmem.totMemAccLat 29626734936 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3835715000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19869.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44318.45 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.55 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.31 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.53 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.31 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38619.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.96 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.33 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.33 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.63 # Average write queue length when enqueuing -system.physmem.readRowHits 1023243 # Number of row buffer hits during reads -system.physmem.writeRowHits 796390 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.73 # Row buffer hit rate for writes -system.physmem.avgGap 22320693.30 # Average gap between requests -system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1817907840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 991914000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4808848200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3406743360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3352725536160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1236862065645 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29713947077250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34314560092455 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.489031 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49431665045810 # Time in different power states -system.physmem_0.memoryStateTime::REF 1714072360000 # Time in different power states +system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.33 # Average write queue length when enqueuing +system.physmem.readRowHits 579803 # Number of row buffer hits during reads +system.physmem.writeRowHits 783916 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.42 # Row buffer hit rate for writes +system.physmem.avgGap 27928121.03 # Average gap between requests +system.physmem.pageHitRate 74.32 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1791077400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 977274375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2938244400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3468841200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1235175473835 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29712796340250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34309586468340 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.449224 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49429866192554 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713925980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 185786732190 # Time in different power states +system.physmem_0.memoryStateTime::ACT 183347171196 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1788219720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 975715125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4902705600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3407358960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3352725536160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1238749464465 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29712291456000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34314840456030 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.494493 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49428877758086 # Time in different power states -system.physmem_1.memoryStateTime::REF 1714072360000 # Time in different power states +system.physmem_1.actEnergy 1771020720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 966330750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3045424200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3450165840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1235608843410 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29712416191500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34309697193300 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.451381 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49429214230967 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713925980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 188572884414 # Time in different power states +system.physmem_1.memoryStateTime::ACT 183999255033 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -344,15 +344,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 223870317 # Number of BP lookups -system.cpu.branchPred.condPredicted 149571742 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12183866 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157933845 # Number of BTB lookups -system.cpu.branchPred.BTBHits 103250874 # Number of BTB hits +system.cpu.branchPred.lookups 224297572 # Number of BP lookups +system.cpu.branchPred.condPredicted 149902957 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12193787 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 158452721 # Number of BTB lookups +system.cpu.branchPred.BTBHits 103491021 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.376028 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 30780710 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 342883 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.313502 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 30817326 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 343319 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -383,85 +383,85 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 937088 # Table walker walks requested -system.cpu.dtb.walker.walksLong 937088 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15029 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 154587 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 427394 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 509694 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2223.932399 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 14616.246492 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 506310 99.34% 99.34% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 1920 0.38% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 988 0.19% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 199 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 148 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 28 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 46 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 49 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 509694 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 474748 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 23018.407660 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 18045.301329 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 20477.097679 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 463839 97.70% 97.70% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 7714 1.62% 99.33% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 2286 0.48% 99.81% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 175 0.04% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 504 0.11% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 86 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 94 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 30 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 8 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 474748 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 784053971876 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.725342 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.519550 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 781854829876 99.72% 99.72% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 1175747000 0.15% 99.87% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 476309500 0.06% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 200437500 0.03% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 146602500 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 120332500 0.02% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 25999000 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 51086000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2628000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 784053971876 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 154588 91.14% 91.14% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 15029 8.86% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 169617 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 937088 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 949838 # Table walker walks requested +system.cpu.dtb.walker.walksLong 949838 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15818 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155419 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 436827 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 513011 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2225.817770 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 14567.134273 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 509618 99.34% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 1930 0.38% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 987 0.19% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 197 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 149 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 32 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 53 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 41 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 513011 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 485512 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 23036.801356 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 18084.539614 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 20755.830536 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 474265 97.68% 97.68% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 7843 1.62% 99.30% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 2427 0.50% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 166 0.03% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 551 0.11% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 105 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 109 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 26 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 485512 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 779669132376 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.722626 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.523315 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 777439658376 99.71% 99.71% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 1176099000 0.15% 99.86% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 488850000 0.06% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 205535000 0.03% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 152105500 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 121751500 0.02% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 29187500 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 53249500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2696000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 779669132376 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 155420 90.76% 90.76% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 15818 9.24% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 171238 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 949838 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 937088 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 169617 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 949838 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171238 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 169617 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1106705 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171238 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1121076 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 169133397 # DTB read hits -system.cpu.dtb.read_misses 670096 # DTB read misses -system.cpu.dtb.write_hits 147221017 # DTB write hits -system.cpu.dtb.write_misses 266992 # DTB write misses +system.cpu.dtb.read_hits 169331819 # DTB read hits +system.cpu.dtb.read_misses 674131 # DTB read misses +system.cpu.dtb.write_hits 147501461 # DTB write hits +system.cpu.dtb.write_misses 275707 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 39151 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1017 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 71818 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 99 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9972 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 72020 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 117 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 10130 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 69741 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 169803493 # DTB read accesses -system.cpu.dtb.write_accesses 147488009 # DTB write accesses +system.cpu.dtb.perms_faults 69829 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 170005950 # DTB read accesses +system.cpu.dtb.write_accesses 147777168 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 316354414 # DTB hits -system.cpu.dtb.misses 937088 # DTB misses -system.cpu.dtb.accesses 317291502 # DTB accesses +system.cpu.dtb.hits 316833280 # DTB hits +system.cpu.dtb.misses 949838 # DTB misses +system.cpu.dtb.accesses 317783118 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -491,328 +491,325 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 160983 # Table walker walks requested -system.cpu.itb.walker.walksLong 160983 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1438 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 121478 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17520 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 143463 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1273.722144 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 9463.659088 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 142472 99.31% 99.31% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 574 0.40% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 44 0.03% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 82 0.06% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 231 0.16% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 26 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 161333 # Table walker walks requested +system.cpu.itb.walker.walksLong 161333 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1433 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 121604 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 17607 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 143726 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1329.870726 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 9693.373994 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 142645 99.25% 99.25% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 592 0.41% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 67 0.05% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 93 0.06% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 270 0.19% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 24 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::262144-294911 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::294912-327679 5 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::393216-425983 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 143463 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 140436 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 29061.341109 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24320.215707 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 22395.663440 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 137485 97.90% 97.90% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 845 0.60% 98.50% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 1830 1.30% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 92 0.07% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 113 0.08% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 31 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 34 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkWaitTime::294912-327679 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::360448-393215 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 143726 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 140644 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 29101.756918 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24236.740283 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 22905.442201 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 137486 97.75% 97.75% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 886 0.63% 98.38% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 1961 1.39% 99.78% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 124 0.09% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 124 0.09% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 33 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 20 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 140436 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 672381692680 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.944059 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.230149 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 37665306856 5.60% 5.60% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 634665708824 94.39% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 49644500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 1013500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 19000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 672381692680 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 121478 98.83% 98.83% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1438 1.17% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 122916 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 140644 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 672291747976 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.944017 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.230261 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 37693655356 5.61% 5.61% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 634541752620 94.38% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 55651000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 688000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 1000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 672291747976 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 121604 98.84% 98.84% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1433 1.16% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 123037 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 160983 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 160983 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161333 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 161333 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 122916 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 122916 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 283899 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 355891670 # ITB inst hits -system.cpu.itb.inst_misses 160983 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123037 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 123037 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 284370 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 356599136 # ITB inst hits +system.cpu.itb.inst_misses 161333 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 39151 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1017 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 52900 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53042 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 368990 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 369633 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 356052653 # ITB inst accesses -system.cpu.itb.hits 355891670 # DTB hits -system.cpu.itb.misses 160983 # DTB misses -system.cpu.itb.accesses 356052653 # DTB accesses -system.cpu.numCycles 1641618102 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 356760469 # ITB inst accesses +system.cpu.itb.hits 356599136 # DTB hits +system.cpu.itb.misses 161333 # DTB misses +system.cpu.itb.accesses 356760469 # DTB accesses +system.cpu.numCycles 1628081885 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 643295277 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 998912988 # Number of instructions fetch has processed -system.cpu.fetch.Branches 223870317 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 134031584 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 911548920 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26021190 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3814569 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 28072 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9294541 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1045994 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 928 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 355505947 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6091455 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 48555 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1582038896 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.739816 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.145969 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 644023121 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1000825975 # Number of instructions fetch has processed +system.cpu.fetch.Branches 224297572 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 134308347 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 897356081 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26042356 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3815311 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 27434 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9297529 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1037208 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 977 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 356212596 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6096332 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 48851 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1568578839 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.747604 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.149571 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1026150412 64.86% 64.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 213368743 13.49% 78.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70509493 4.46% 82.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 272010248 17.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1011708684 64.50% 64.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 213717515 13.62% 78.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 70499052 4.49% 82.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 272653588 17.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1582038896 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.136372 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.608493 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 523526038 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 567332242 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 432225078 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 49743606 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9211932 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33585206 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3858658 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1082487330 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 28953315 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9211932 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 568013928 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 68659821 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 370106883 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 437449183 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 128597149 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1062778939 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6765759 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 5100330 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 330196 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 669001 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 77613497 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 20248 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1010589647 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1636490834 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1256895335 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1474103 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 945145868 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 65443776 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 26770566 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23114475 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 102068123 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 173157157 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 150776419 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9868164 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9014634 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1027918827 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27065451 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1043272281 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3272960 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60330213 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33600804 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 313388 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1582038896 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.659448 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.917899 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1568578839 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.137768 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.614727 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 523834599 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 552751170 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 433009950 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 49764409 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9218711 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33629126 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3862659 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1084582874 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 28977480 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9218711 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 568372766 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 66217937 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 371830406 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 438295981 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 114643038 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1064838864 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6775021 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 5115924 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 336846 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 638712 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 63601510 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 20546 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1012729668 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1640391275 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1259385666 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1476745 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 947192806 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 65536859 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 26910765 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23247835 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 101832167 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 173436334 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 151069277 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9864131 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8951241 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1029826470 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27204925 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1045231227 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3279121 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60421557 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33664917 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 313528 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1568578839 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.666356 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.920348 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 936232713 59.18% 59.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 333194737 21.06% 80.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234236353 14.81% 95.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 71914703 4.55% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6441221 0.41% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19169 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 921654762 58.76% 58.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 333747896 21.28% 80.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234544221 14.95% 94.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72152324 4.60% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6460263 0.41% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19373 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1582038896 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1568578839 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57633129 35.05% 35.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 100179 0.06% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26746 0.02% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 783 0.00% 35.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44218992 26.89% 62.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 62461837 37.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 57742950 35.03% 35.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 99825 0.06% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26740 0.02% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 625 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44231739 26.83% 61.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 62727458 38.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 21 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 718385578 68.86% 68.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2533352 0.24% 69.10% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 122770 0.01% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 382 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 121248 0.01% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 173007895 16.58% 85.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 149100989 14.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 719843938 68.87% 68.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2535420 0.24% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 122954 0.01% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 380 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 121377 0.01% 69.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 173211987 16.57% 85.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 149395124 14.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1043272281 # Type of FU issued -system.cpu.iq.rate 0.635515 # Inst issue rate -system.cpu.iq.fu_busy_cnt 164441666 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157621 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3833820592 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1114508942 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1025374913 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2477491 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 947894 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 909947 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1206157308 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1556618 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4301219 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1045231227 # Type of FU issued +system.cpu.iq.rate 0.642002 # Inst issue rate +system.cpu.iq.fu_busy_cnt 164829337 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157697 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3824665950 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1116644145 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1027372601 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2483800 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 950168 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 912054 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1208499896 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1560667 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4304106 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13765356 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14482 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 143653 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6293913 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13785862 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14456 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 142604 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6312817 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2526650 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1543650 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2532139 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1442341 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9211932 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6884950 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9078435 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1055205514 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9218711 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 7060342 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6923682 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1057253447 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 173157157 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 150776419 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22691259 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 56491 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8949926 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 143653 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3653003 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5096400 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8749403 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1032130630 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 169121119 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10215406 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 173436334 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 151069277 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22822922 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 57401 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6792645 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 142604 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3655399 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5100784 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8756183 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1034064574 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 169319677 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10227871 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221236 # number of nop insts executed -system.cpu.iew.exec_refs 316337352 # number of memory reference insts executed -system.cpu.iew.exec_branches 195829859 # Number of branches executed -system.cpu.iew.exec_stores 147216233 # Number of stores executed -system.cpu.iew.exec_rate 0.628728 # Inst execution rate -system.cpu.iew.wb_sent 1027090277 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1026284860 # cumulative count of insts written-back -system.cpu.iew.wb_producers 436833707 # num instructions producing a value -system.cpu.iew.wb_consumers 706462159 # num instructions consuming a value -system.cpu.iew.wb_rate 0.625167 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.618340 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 51246502 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 26752063 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8385203 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1570087734 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.633502 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.269814 # Number of insts commited each cycle +system.cpu.iew.exec_nop 222052 # number of nop insts executed +system.cpu.iew.exec_refs 316816486 # number of memory reference insts executed +system.cpu.iew.exec_branches 196206176 # Number of branches executed +system.cpu.iew.exec_stores 147496809 # Number of stores executed +system.cpu.iew.exec_rate 0.635143 # Inst execution rate +system.cpu.iew.wb_sent 1029092840 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1028284655 # cumulative count of insts written-back +system.cpu.iew.wb_producers 437786008 # num instructions producing a value +system.cpu.iew.wb_consumers 708231099 # num instructions consuming a value +system.cpu.iew.wb_rate 0.631593 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.618140 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 51332329 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 26891397 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8391320 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1556613982 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.640242 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.274821 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1059518127 67.48% 67.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 287046411 18.28% 85.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 120236472 7.66% 93.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36451838 2.32% 95.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28385212 1.81% 97.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13987217 0.89% 98.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8615612 0.55% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4166173 0.27% 99.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11680672 0.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1044975044 67.13% 67.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 287768132 18.49% 85.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 120346121 7.73% 93.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36551788 2.35% 95.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28453995 1.83% 97.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14010396 0.90% 98.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8635881 0.55% 98.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4170150 0.27% 99.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11702475 0.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1570087734 # Number of insts commited each cycle -system.cpu.commit.committedInsts 846524467 # Number of instructions committed -system.cpu.commit.committedOps 994654061 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1556613982 # Number of insts commited each cycle +system.cpu.commit.committedInsts 848158120 # Number of instructions committed +system.cpu.commit.committedOps 996609834 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 303874306 # Number of memory references committed -system.cpu.commit.loads 159391800 # Number of loads committed -system.cpu.commit.membars 6909679 # Number of memory barriers committed -system.cpu.commit.branches 188935778 # Number of branches committed -system.cpu.commit.fp_insts 896706 # Number of committed floating point instructions. -system.cpu.commit.int_insts 913907111 # Number of committed integer instructions. -system.cpu.commit.function_calls 25250179 # Number of function calls committed. +system.cpu.commit.refs 304406931 # Number of memory references committed +system.cpu.commit.loads 159650471 # Number of loads committed +system.cpu.commit.membars 6926449 # Number of memory barriers committed +system.cpu.commit.branches 189300112 # Number of branches committed +system.cpu.commit.fp_insts 898776 # Number of committed floating point instructions. +system.cpu.commit.int_insts 915651780 # Number of committed integer instructions. +system.cpu.commit.function_calls 25280403 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 688421836 69.21% 69.21% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2147861 0.22% 69.43% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98019 0.01% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 689842559 69.22% 69.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2150231 0.22% 69.43% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98139 0.01% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction @@ -835,540 +832,541 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.44% # system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 111997 0.01% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 159391800 16.02% 85.47% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 144482506 14.53% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 111932 0.01% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 159650471 16.02% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 144756460 14.52% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 994654061 # Class of committed instruction -system.cpu.commit.bw_lim_events 11680672 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2596784081 # The number of ROB reads -system.cpu.rob.rob_writes 2103659595 # The number of ROB writes -system.cpu.timesIdled 8144337 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59579206 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101021431570 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 846524467 # Number of Instructions Simulated -system.cpu.committedOps 994654061 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.939245 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.939245 # CPI: Total CPI of All Threads -system.cpu.ipc 0.515665 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.515665 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1221742987 # number of integer regfile reads -system.cpu.int_regfile_writes 729786392 # number of integer regfile writes -system.cpu.fp_regfile_reads 1462559 # number of floating regfile reads -system.cpu.fp_regfile_writes 782552 # number of floating regfile writes -system.cpu.cc_regfile_reads 224594796 # number of cc regfile reads -system.cpu.cc_regfile_writes 225242859 # number of cc regfile writes -system.cpu.misc_regfile_reads 2567204891 # number of misc regfile reads -system.cpu.misc_regfile_writes 26785378 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9653571 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.972798 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 282643774 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9654083 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.277123 # Average number of references to valid blocks. +system.cpu.commit.op_class_0::total 996609834 # Class of committed instruction +system.cpu.commit.bw_lim_events 11702475 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2585312705 # The number of ROB reads +system.cpu.rob.rob_writes 2107755396 # The number of ROB writes +system.cpu.timesIdled 8146940 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59503046 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101026198411 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 848158120 # Number of Instructions Simulated +system.cpu.committedOps 996609834 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.919550 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.919550 # CPI: Total CPI of All Threads +system.cpu.ipc 0.520955 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.520955 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1224113620 # number of integer regfile reads +system.cpu.int_regfile_writes 731133953 # number of integer regfile writes +system.cpu.fp_regfile_reads 1465257 # number of floating regfile reads +system.cpu.fp_regfile_writes 785096 # number of floating regfile writes +system.cpu.cc_regfile_reads 225210240 # number of cc regfile reads +system.cpu.cc_regfile_writes 225863400 # number of cc regfile writes +system.cpu.misc_regfile_reads 2555640420 # number of misc regfile reads +system.cpu.misc_regfile_writes 26930775 # number of misc regfile writes +system.cpu.dcache.tags.replacements 9682749 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 283083620 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9683261 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.234327 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.972798 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.972800 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 381 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1234280358 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1234280358 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 146896386 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146896386 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128038519 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128038519 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 377527 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 377527 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 324244 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 324244 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3284324 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3284324 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3679077 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3679077 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 274934905 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 274934905 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 275312432 # number of overall hits -system.cpu.dcache.overall_hits::total 275312432 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9519580 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9519580 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11197407 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11197407 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1162034 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1162034 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1231431 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1231431 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 446029 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 446029 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 20716987 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20716987 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21879021 # number of overall misses -system.cpu.dcache.overall_misses::total 21879021 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 166239076000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 166239076000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 434694643757 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 434694643757 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 89167821376 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 89167821376 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6826466500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 6826466500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 272500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 272500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 600933719757 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 600933719757 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 600933719757 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 600933719757 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 156415966 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 156415966 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 139235926 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 139235926 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1539561 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1539561 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1555675 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1555675 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3730353 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3730353 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3679082 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3679082 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 295651892 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 295651892 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 297191453 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 297191453 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060861 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.060861 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080420 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080420 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.754783 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.754783 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791573 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.791573 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119568 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119568 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.070072 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.070072 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.073619 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.073619 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17462.858235 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17462.858235 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38821.009521 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38821.009521 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 72409.920959 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 72409.920959 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15304.983532 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15304.983532 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 54500 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 54500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29006.810679 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29006.810679 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27466.207001 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27466.207001 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 49612844 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 1236470793 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1236470793 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 147113779 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 147113779 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128236098 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128236098 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 377977 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 377977 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 323653 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 323653 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3296961 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3296961 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3691090 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3691090 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 275349877 # 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number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 6 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 20807261 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20807261 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21977375 # number of overall misses +system.cpu.dcache.overall_misses::total 21977375 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 168019956500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 168019956500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 444932022751 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 444932022751 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 52262346938 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 52262346938 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6889431000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 6889431000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 285500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 285500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 612951979251 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 612951979251 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 612951979251 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 612951979251 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 156661001 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 156661001 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 139496137 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 139496137 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1548091 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1548091 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1557456 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1557456 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3743099 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3743099 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3691096 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3691096 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 296157138 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 296157138 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 297705229 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 297705229 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060942 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.060942 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080719 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080719 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.755843 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.755843 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.792191 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.792191 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119189 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119189 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.070258 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.070258 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.073823 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.073823 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17598.832048 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17598.832048 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39514.252371 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39514.252371 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42358.745228 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42358.745228 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15442.376574 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15442.376574 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 47583.333333 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 47583.333333 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29458.561569 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29458.561569 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27890.136072 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27890.136072 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32144751 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1593346 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1600072 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.137521 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.089565 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7472245 # number of writebacks -system.cpu.dcache.writebacks::total 7472245 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4426093 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4426093 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9200570 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9200570 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7004 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 7004 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 218758 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 218758 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 13626663 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 13626663 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 13626663 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 13626663 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5093487 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5093487 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1996837 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1996837 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1155229 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1155229 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1224427 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1224427 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 227271 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 227271 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 7090324 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 7090324 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 8245553 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 8245553 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 7504258 # number of writebacks +system.cpu.dcache.writebacks::total 7504258 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4442516 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4442516 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9255736 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9255736 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7058 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 7058 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 218425 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 218425 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 13698252 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 13698252 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 13698252 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 13698252 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5104706 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5104706 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2004303 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2004303 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1163297 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1163297 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226745 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1226745 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 227713 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 227713 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 6 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 7109009 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 7109009 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 8272306 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 8272306 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84024978000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 84024978000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76144562086 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 76144562086 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 22952152500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 22952152500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 87564866876 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 87564866876 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3184481000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3184481000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 267500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 267500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160169540086 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 160169540086 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 183121692586 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 183121692586 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6191871000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6191871000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6228308464 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228308464 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12420179464 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 12420179464 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032564 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032564 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014341 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014341 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.750363 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.750363 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787071 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787071 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060925 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060925 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023982 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.023982 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027745 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027745 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16496.552951 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16496.552951 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38132.587730 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38132.587730 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19868.054299 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19868.054299 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 71514.975475 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 71514.975475 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14011.822890 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14011.822890 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 53500 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 53500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22589.876018 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22589.876018 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 84710979000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77672671390 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77672671390 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23648689000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23648689000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 50594844438 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 50594844438 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3209583500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3209583500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 279500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 279500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162383650390 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 162383650390 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186032339390 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 186032339390 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6191842000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6191842000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6228406964 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228406964 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12420248964 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 12420248964 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032584 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032584 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014368 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014368 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751440 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751440 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787659 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787659 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060835 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060835 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024004 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024004 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027787 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027787 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16594.683220 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16594.683220 # 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average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 46583.333333 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22841.953132 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22841.953132 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22488.570828 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22488.570828 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183854.207495 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183854.207495 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184841.137346 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184841.137346 # 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Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 370501257 # Number of tag accesses -system.cpu.icache.tags.data_accesses 370501257 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 339700335 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 339700335 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 339700335 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 339700335 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 339700335 # 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number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 340404778 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 340404778 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 340404778 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 340404778 # number of overall hits +system.cpu.icache.overall_hits::total 340404778 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15786521 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15786521 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15786521 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15786521 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15786521 # number of overall misses +system.cpu.icache.overall_misses::total 15786521 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 213423777380 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 213423777380 # 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average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 24648 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1429 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1434 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 16.440168 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 17.188285 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 15015869 # number of writebacks -system.cpu.icache.writebacks::total 15015869 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 767710 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 767710 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 767710 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 767710 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 767710 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 767710 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15016606 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15016606 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15016606 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15016606 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15016606 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15016606 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 19490.411179 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.567542 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004448 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006439 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.120398 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.297400 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996227 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 288 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 61244 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 288 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 554 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2686 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5116 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52825 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.934509 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 408147650 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 408147650 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 779679 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 299256 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1078935 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 7472245 # 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number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5836278000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5836278000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5770678500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8189441500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5836379500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5836379500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2418763000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607013500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 14025776500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004103 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010204 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.005802 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607058000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 14025821000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004222 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010790 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.006044 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.784102 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.784102 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.197685 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.197685 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005574 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005574 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.038376 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.038376 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.403563 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.403563 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004103 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010204 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005574 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.075357 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.029564 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004103 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010204 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005574 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.075357 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.029564 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127646.793587 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128088.816856 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127863.347785 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68011.600757 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68011.600757 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783097 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783097 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.201314 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.201314 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005512 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005512 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039436 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039436 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.405812 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.405812 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004222 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010790 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005512 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.077035 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.030160 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004222 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010790 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005512 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.077035 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.030160 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126647.937192 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127169.056402 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68010.437463 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68010.437463 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69666.666667 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69666.666667 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128655.026050 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128655.026050 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124605.160034 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124605.160034 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 128886.233897 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 128886.233897 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145023.125375 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145023.125375 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127646.793587 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128088.816856 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124605.160034 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 128745.436731 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128259.937845 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127646.793587 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128088.816856 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124605.160034 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 128745.436731 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128259.937845 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129465.449687 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129465.449687 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124519.613263 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124519.613263 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129612.133934 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129612.133934 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69897.425416 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69897.425416 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126647.937192 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124519.613263 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129523.100498 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128943.104737 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126647.937192 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124519.613263 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129523.100498 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128943.104737 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171350.302868 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148975.814960 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173203.881766 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173203.881766 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171348.610369 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148974.778069 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173206.893993 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173206.893993 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172277.339923 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.070555 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172278.000416 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.572427 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 50072876 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 25402191 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3486 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2165 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2165 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 50149666 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 25446406 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2163 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2163 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 1616472 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23106705 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 1624231 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23137410 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8523542 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 15015869 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2370764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43153 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43158 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1956829 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1956829 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15016606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6481683 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1331091 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1224427 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45091458 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29183621 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 729593 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1917139 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 76921811 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1922405600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1017963166 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2418728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6263128 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2949050622 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1833494 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 27720270 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.025088 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.156393 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 8571764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 15019267 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2370936 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 43503 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1964146 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1964146 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15020006 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6501231 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1333409 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1226745 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45101659 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29271837 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 729068 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1925616 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 77028180 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1922840864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1021731230 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2408256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6275144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2953255494 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1860303 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 27780180 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.025443 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.157467 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 27024822 97.49% 97.49% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 695448 2.51% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 27073367 97.46% 97.46% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 706813 2.54% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 27720270 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 48021701496 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 27780180 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 48093772959 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1471889 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1496382 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22555136481 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22560257433 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13331758520 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13373462829 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 427610263 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 428394234 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1134604242 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1141603196 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40281 # Transaction distribution -system.iobus.trans_dist::ReadResp 40281 # Transaction distribution +system.iobus.trans_dist::ReadReq 40297 # Transaction distribution +system.iobus.trans_dist::ReadResp 40297 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1588,11 +1590,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230920 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230920 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353736 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1607,16 +1609,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334112 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334112 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492032 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 41869500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41874500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 342000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 342500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1630,77 +1632,77 @@ system.iobus.reqLayer14.occupancy 9500 # La system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25153000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25162500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36496500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36499500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 567170357 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 567349755 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147680000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147712000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115446 # number of replacements -system.iocache.tags.tagsinuse 10.422236 # Cycle average of tags in use +system.iocache.tags.replacements 115457 # number of replacements +system.iocache.tags.tagsinuse 10.423127 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115462 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13103145496000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 5.903254 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 4.518982 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.368953 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.282436 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651390 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13098803375000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544202 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.878925 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221513 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429933 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651445 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039497 # Number of tag accesses -system.iocache.tags.data_accesses 1039497 # Number of data accesses +system.iocache.tags.tag_accesses 1039641 # Number of tag accesses +system.iocache.tags.data_accesses 1039641 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8796 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8833 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8796 # number of demand (read+write) misses -system.iocache.demand_misses::total 8836 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8812 # number of demand (read+write) misses +system.iocache.demand_misses::total 8852 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8796 # number of overall misses -system.iocache.overall_misses::total 8836 # number of overall misses +system.iocache.overall_misses::realview.ide 8812 # number of overall misses +system.iocache.overall_misses::total 8852 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5069500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1678447047 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1683516547 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1683110232 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1688179732 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13410212810 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13410212810 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13415109023 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13415109023 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5420500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1678447047 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1683867547 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1683110232 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1688530732 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5420500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1678447047 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1683867547 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1683110232 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1688530732 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8796 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8833 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8796 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8836 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8812 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8852 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8796 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8836 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8812 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8852 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1715,54 +1717,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 190819.355048 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 190593.971131 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 191002.068997 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 190776.328625 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125723.888191 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125723.888191 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125769.791335 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125769.791335 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 190819.355048 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 190568.984495 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 191002.068997 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 190751.325350 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 190819.355048 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 190568.984495 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34452 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 191002.068997 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 190751.325350 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34444 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3448 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3506 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.991879 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.824301 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8796 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8833 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8812 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8849 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8796 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8836 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8812 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8852 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8796 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8836 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8812 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8852 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1238647047 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1241866547 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1242510232 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1245729732 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8071956842 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8071956842 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8076836456 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8076836456 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3420500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1238647047 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1242067547 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1242510232 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1245930732 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3420500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1238647047 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1242067547 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1242510232 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1245930732 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1777,71 +1779,71 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140819.355048 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 140593.971131 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141002.068997 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 140776.328625 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75676.487306 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75676.487306 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75722.234831 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75722.234831 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 140819.355048 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 140568.984495 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 141002.068997 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 140751.325350 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 140819.355048 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 140568.984495 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 141002.068997 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 140751.325350 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 54972 # Transaction distribution -system.membus.trans_dist::ReadResp 402203 # Transaction distribution +system.membus.trans_dist::ReadResp 409202 # Transaction distribution system.membus.trans_dist::WriteReq 33696 # Transaction distribution system.membus.trans_dist::WriteResp 33696 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1051260 # Transaction distribution -system.membus.trans_dist::CleanEvict 188377 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34626 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1067474 # Transaction distribution +system.membus.trans_dist::CleanEvict 191385 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34855 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 880179 # Transaction distribution -system.membus.trans_dist::ReadExResp 880179 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 347231 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution +system.membus.trans_dist::ReadExReq 394790 # Transaction distribution +system.membus.trans_dist::ReadExResp 394790 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 354230 # Transaction distribution +system.membus.trans_dist::InvalidateReq 604321 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3643028 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3772648 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237638 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237638 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4010286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3203313 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3332933 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237959 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237959 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3570892 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 138764108 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 138934078 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7252608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7252608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 146186686 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2808 # Total snoops (count) -system.membus.snoop_fanout::samples 2697046 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 109183820 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 109353790 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7271424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7271424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 116625214 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2530 # Total snoops (count) +system.membus.snoop_fanout::samples 2735759 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2697046 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2735759 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2697046 # Request fanout histogram -system.membus.reqLayer0.occupancy 103954500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2735759 # Request fanout histogram +system.membus.reqLayer0.occupancy 103971500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 32000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5466500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5468000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7139670905 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7155774176 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6571001988 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4068025704 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44720417 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44802062 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -1896,6 +1898,6 @@ system.realview.mcc.osc_mcc.clock 20000 # Cl system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16102 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 16114 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt index ea1074d2e..a24da51f0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111167 # Nu sim_ticks 51111167216500 # Number of ticks simulated final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1100410 # Simulator instruction rate (inst/s) -host_op_rate 1293220 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57262321562 # Simulator tick rate (ticks/s) -host_mem_usage 678496 # Number of bytes of host memory used -host_seconds 892.58 # Real time elapsed on the host +host_inst_rate 1780456 # Simulator instruction rate (inst/s) +host_op_rate 2092420 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 92650032032 # Simulator tick rate (ticks/s) +host_mem_usage 679092 # Number of bytes of host memory used +host_seconds 551.66 # Real time elapsed on the host sim_insts 982203438 # Number of instructions simulated sim_ops 1154301153 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -16,9 +16,9 @@ system.clk_domain.clock 1000 # Cl system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 5483956 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 110253960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 74912136 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory -system.physmem.bytes_read::total 116962748 # Number of bytes read from this memory +system.physmem.bytes_read::total 81620924 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 5483956 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 5483956 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 103277504 # Number of bytes written to this memory @@ -27,18 +27,18 @@ system.physmem.bytes_written::total 103298084 # Nu system.physmem.num_reads::cpu.dtb.walker 6476 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5837 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 126094 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1722731 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1170515 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1867963 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1315747 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1613711 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::total 1616284 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 8109 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 7309 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 107295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2157140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1465671 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2288399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1596929 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 107295 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 107295 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 2020645 # Write bandwidth from this memory (bytes/s) @@ -48,9 +48,9 @@ system.physmem.bw_total::writebacks 2020645 # To system.physmem.bw_total::cpu.dtb.walker 8109 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 7309 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 107295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2157543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1466073 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4309446 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3617977 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -721,11 +721,11 @@ system.membus.trans_dist::CleanEvict 226320 # Tr system.membus.trans_dist::UpgradeReq 40491 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 40492 # Transaction distribution -system.membus.trans_dist::ReadExReq 1379258 # Transaction distribution -system.membus.trans_dist::ReadExResp 1379258 # Transaction distribution +system.membus.trans_dist::ReadExReq 827042 # Transaction distribution +system.membus.trans_dist::ReadExResp 827042 # Transaction distribution system.membus.trans_dist::ReadSharedReq 448267 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution +system.membus.trans_dist::InvalidateReq 658880 # Transaction distribution +system.membus.trans_dist::InvalidateResp 658880 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) @@ -737,11 +737,11 @@ system.membus.pkt_count::total 6009963 # Pa system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 213041440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 213210490 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177699616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177868666 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 220601274 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 185259450 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 3924997 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 54c2c1887..d41a2f111 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -4,74 +4,74 @@ sim_seconds 47.256536 # Nu sim_ticks 47256535705500 # Number of ticks simulated final_tick 47256535705500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1053178 # Simulator instruction rate (inst/s) -host_op_rate 1239009 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51012949173 # Simulator tick rate (ticks/s) -host_mem_usage 689744 # Number of bytes of host memory used -host_seconds 926.36 # Real time elapsed on the host +host_inst_rate 1671940 # Simulator instruction rate (inst/s) +host_op_rate 1966949 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 80984002716 # Simulator tick rate (ticks/s) +host_mem_usage 693668 # Number of bytes of host memory used +host_seconds 583.53 # Real time elapsed on the host sim_insts 975625723 # Number of instructions simulated sim_ops 1147772483 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 155968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 156864 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 131392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3922036 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 63542792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 217344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 214144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2638472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 46092656 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 429440 # Number of bytes read from this memory -system.physmem.bytes_read::total 117344244 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3922036 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2638472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6560508 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 101301760 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 3883124 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 35607176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 217792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 214080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2613000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 38038064 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 430464 # Number of bytes read from this memory +system.physmem.bytes_read::total 81291956 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3883124 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2613000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6496124 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 101151552 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 101322344 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2437 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 101172136 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2451 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2053 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 101689 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 992869 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3396 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 3346 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 41333 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 720214 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6710 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1874047 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1582840 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 101081 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 556375 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3403 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3345 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 40935 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 594361 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6726 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1310730 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1580493 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1585414 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3300 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1583067 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3319 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 2780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 82995 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1344635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 4532 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 55833 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 975371 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2483133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 82995 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 55833 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 138828 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2143656 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 82171 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 753487 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 4530 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 55294 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 804927 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1720227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 82171 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 55294 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 137465 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2140478 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2144092 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2143656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2140913 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2140478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3319 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 2780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 82995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1345070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 4532 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 55833 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 975371 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4627224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 82171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 753922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 4530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 55294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 804927 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3861140 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -321,36 +321,36 @@ system.cpu0.dcache.tags.tag_accesses 360582168 # Nu system.cpu0.dcache.tags.data_accesses 360582168 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 85561344 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 85561344 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 80310172 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 80310172 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 80310144 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 80310144 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214412 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 214412 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259684 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 259684 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259689 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 259689 # number of WriteLineReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2079285 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 2079285 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2039916 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 2039916 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 165871516 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 165871516 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 166085928 # number of overall hits -system.cpu0.dcache.overall_hits::total 166085928 # number of overall hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2039805 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2039805 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 165871488 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 165871488 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 166085900 # number of overall hits +system.cpu0.dcache.overall_hits::total 166085900 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 3292661 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 3292661 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1484829 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1484829 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1484857 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1484857 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 774558 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 774558 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 823198 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 823198 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 823193 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 823193 # number of WriteLineReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 118361 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 118361 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 156543 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 156543 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4777490 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4777490 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5552048 # number of overall misses -system.cpu0.dcache.overall_misses::total 5552048 # number of overall misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 156654 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 156654 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4777518 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4777518 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5552076 # number of overall misses +system.cpu0.dcache.overall_misses::total 5552076 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 88854005 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 88854005 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 81795001 # number of WriteReq accesses(hits+misses) @@ -373,16 +373,16 @@ system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018153 system.cpu0.dcache.WriteReq_miss_rate::total 0.018153 # miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.783197 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::total 0.783197 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760192 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760192 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760187 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760187 # miss rate for WriteLineReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053858 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053858 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.071271 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.071271 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.071321 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.071321 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027996 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.027996 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032347 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.032347 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032348 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.032348 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -451,96 +451,96 @@ system.cpu0.l2cache.prefetcher.pfBufferHit 0 # system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2651661 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16083.621220 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 15456673 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2667641 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.794135 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 2651590 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16092.484650 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 15457113 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2667587 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.794418 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15982.700506 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 46.812729 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 54.107985 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.975507 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002857 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003302 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.981666 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15898 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 67 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1468 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4776 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4826 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4604 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005005 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.970337 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 394866118 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 394866118 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 294519 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 156806 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 451325 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 4431483 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 4431483 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 7294760 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 7294760 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 771 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 771 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 630855 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 630855 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4984424 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 4984424 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2948651 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 2948651 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 218371 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 218371 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 294519 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 156806 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4984424 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3579506 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 9015255 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 294519 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 156806 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4984424 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3579506 # number of overall hits -system.cpu0.l2cache.overall_hits::total 9015255 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11443 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8713 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 20156 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 140594 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 140594 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 156543 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 156543 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 712979 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 712979 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 495543 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 495543 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1236929 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 1236929 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 604457 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 604457 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11443 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8713 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 495543 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1949908 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2465607 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11443 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8713 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 495543 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1949908 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2465607 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 305962 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 165519 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 471481 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4431483 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 4431483 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 7294760 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 7294760 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 141365 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 141365 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 156543 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 156543 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.tags.occ_blocks::writebacks 15991.608429 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 49.291374 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 51.584847 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.976050 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003009 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003148 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.982207 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 77 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15920 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 56 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 226 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1478 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4821 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4797 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4598 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.971680 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 394865177 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 394865177 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 294372 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 156640 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 451012 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 4430802 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 4430802 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 7295441 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 7295441 # number of WritebackClean hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 774 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 774 # number of UpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 631554 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 631554 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4983798 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 4983798 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2949332 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 2949332 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 218231 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 218231 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 294372 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 156640 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 4983798 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3580886 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 9015696 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 294372 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 156640 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 4983798 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3580886 # number of overall hits +system.cpu0.l2cache.overall_hits::total 9015696 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11531 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8761 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 20292 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 140614 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 140614 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 156654 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 156654 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 712280 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 712280 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 496169 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 496169 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1236248 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 1236248 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 604597 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 604597 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11531 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8761 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 496169 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1948528 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2464989 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11531 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8761 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 496169 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1948528 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2464989 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 305903 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 165401 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 471304 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4430802 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 4430802 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 7295441 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 7295441 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 141388 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 141388 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 156654 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 156654 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1343834 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 1343834 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5479967 # number of ReadCleanReq accesses(hits+misses) @@ -549,41 +549,41 @@ system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4185580 system.cpu0.l2cache.ReadSharedReq_accesses::total 4185580 # number of ReadSharedReq accesses(hits+misses) system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 822828 # number of InvalidateReq accesses(hits+misses) system.cpu0.l2cache.InvalidateReq_accesses::total 822828 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 305962 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 165519 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 305903 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 165401 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.inst 5479967 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.data 5529414 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 11480862 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 305962 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 165519 # number of overall (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 11480685 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 305903 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 165401 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.inst 5479967 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.data 5529414 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 11480862 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037400 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052640 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.042750 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994546 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994546 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.overall_accesses::total 11480685 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037695 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052968 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.043055 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994526 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994526 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.530556 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.530556 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090428 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090428 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.295522 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.295522 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.734609 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.734609 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037400 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052640 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090428 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.352643 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.214758 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037400 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052640 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090428 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.352643 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.214758 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.530036 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.530036 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090542 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090542 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.295359 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.295359 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.734779 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.734779 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037695 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052968 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090542 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.352393 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.214707 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037695 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052968 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090542 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.352393 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.214707 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -592,24 +592,24 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1559370 # number of writebacks -system.cpu0.l2cache.writebacks::total 1559370 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 1558575 # number of writebacks +system.cpu0.l2cache.writebacks::total 1558575 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 24116923 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12284721 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_requests 24117057 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12284855 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1399 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 1786138 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1785867 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 271 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 1785822 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1785488 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 334 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.trans_dist::ReadReq 618755 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 10284302 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 33226 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 33226 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 4431483 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 7296159 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 141365 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 156543 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 297908 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 4430802 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 7296840 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 141388 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 156654 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 298042 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 1343834 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 1343834 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5479967 # Transaction distribution @@ -617,27 +617,27 @@ system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4185580 system.cpu0.toL2Bus.trans_dist::InvalidateReq 822828 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateResp 822828 # Transaction distribution system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16525634 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19681122 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19681390 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 362662 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 722420 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 37291838 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 37292106 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 701575188 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 753965416 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1450648 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2889680 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size::total 1459880932 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6128014 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 30453385 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.067263 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.250512 # Request fanout histogram +system.cpu0.toL2Bus.snoops 6124419 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 30450834 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.067260 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.250516 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 28405278 93.27% 93.27% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2047836 6.72% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 271 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 28403043 93.28% 93.28% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2047457 6.72% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 334 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 30453385 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 30450834 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -853,36 +853,36 @@ system.cpu1.dcache.tags.tag_accesses 351517490 # Nu system.cpu1.dcache.tags.data_accesses 351517490 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 84375671 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 84375671 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 77626077 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 77626077 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 77626026 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 77626026 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188285 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 188285 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 64906 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 64906 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 64910 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 64910 # number of WriteLineReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062470 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 2062470 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2047972 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 2047972 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 162001748 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 162001748 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 162190033 # number of overall hits -system.cpu1.dcache.overall_hits::total 162190033 # number of overall hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2047982 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 2047982 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 162001697 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 162001697 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 162189982 # number of overall hits +system.cpu1.dcache.overall_hits::total 162189982 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 3369907 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 3369907 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1463826 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1463826 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1463877 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1463877 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 790298 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 790298 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 435847 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 435847 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 435843 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 435843 # number of WriteLineReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 145888 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 145888 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 159002 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 159002 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4833733 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4833733 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5624031 # number of overall misses -system.cpu1.dcache.overall_misses::total 5624031 # number of overall misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158992 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 158992 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4833784 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4833784 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5624082 # number of overall misses +system.cpu1.dcache.overall_misses::total 5624082 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 87745578 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 87745578 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 79089903 # number of WriteReq accesses(hits+misses) @@ -901,20 +901,20 @@ system.cpu1.dcache.overall_accesses::cpu1.data 167814064 system.cpu1.dcache.overall_accesses::total 167814064 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038405 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.038405 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018508 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018508 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018509 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018509 # miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.807594 # miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::total 0.807594 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870383 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870383 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870375 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870375 # miss rate for WriteLineReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066062 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066062 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.072045 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.072045 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.072041 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.072041 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028973 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.028973 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033513 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.033513 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033514 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.033514 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -983,98 +983,97 @@ system.cpu1.l2cache.prefetcher.pfBufferHit 0 # system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2273518 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13372.591247 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 14355328 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2289651 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 6.269658 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9713557312500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 13267.841352 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 47.789421 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 56.960475 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.809805 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002917 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003477 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.816198 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 75 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 16058 # Occupied blocks per task id +system.cpu1.l2cache.tags.replacements 2274505 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13370.273853 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 14355408 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2290637 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 6.266994 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9713557342500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 13266.664229 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 44.449121 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 59.160502 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.809733 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002713 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003611 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.816057 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 66 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 16066 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 317 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1558 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5907 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4452 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3824 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004578 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.980103 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 364667597 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 364667597 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 349833 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155576 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 505409 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 4030572 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 4030572 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 6737405 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 6737405 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1033 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1033 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 606896 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 606896 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4338388 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 4338388 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3076039 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 3076039 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 163041 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 163041 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 349833 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155576 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4338388 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3682935 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8526732 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 349833 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155576 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4338388 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3682935 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8526732 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12358 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9778 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 22136 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 147541 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 147541 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 159002 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 159002 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 708595 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 708595 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 467005 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 467005 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1230054 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 1230054 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 272567 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 272567 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12358 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9778 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 467005 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1938649 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 2427790 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12358 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9778 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 467005 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1938649 # number of overall misses -system.cpu1.l2cache.overall_misses::total 2427790 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 362191 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165354 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 527545 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4030572 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 4030572 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 6737405 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 6737405 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 148574 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 148574 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 159002 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 159002 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 37 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 307 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1542 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5867 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4427 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3923 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004028 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.980591 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 364664430 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 364664430 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 349739 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155441 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 505180 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 4030758 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 4030758 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 6737219 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 6737219 # number of WritebackClean hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1036 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1036 # number of UpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 606945 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 606945 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4338204 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 4338204 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3075973 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 3075973 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 162958 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 162958 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 349739 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155441 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 4338204 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3682918 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 8526302 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 349739 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155441 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 4338204 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3682918 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8526302 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12351 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9805 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 22156 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 147585 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 147585 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158992 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 158992 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 708546 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 708546 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 467189 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 467189 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1230120 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 1230120 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 272650 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 272650 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12351 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9805 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 467189 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1938666 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 2428011 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12351 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9805 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 467189 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1938666 # number of overall misses +system.cpu1.l2cache.overall_misses::total 2428011 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 362090 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165246 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 527336 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4030758 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 4030758 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 6737219 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 6737219 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 148621 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 148621 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158992 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 158992 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315491 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 1315491 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4805393 # number of ReadCleanReq accesses(hits+misses) @@ -1083,41 +1082,41 @@ system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4306093 system.cpu1.l2cache.ReadSharedReq_accesses::total 4306093 # number of ReadSharedReq accesses(hits+misses) system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 435608 # number of InvalidateReq accesses(hits+misses) system.cpu1.l2cache.InvalidateReq_accesses::total 435608 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 362191 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165354 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 362090 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165246 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.inst 4805393 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.data 5621584 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10954522 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 362191 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165354 # number of overall (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 10954313 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 362090 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165246 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.inst 4805393 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 5621584 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10954522 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034120 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.059134 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.041960 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.993047 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.993047 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.overall_accesses::total 10954313 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034110 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.059336 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.042015 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.993029 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.993029 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.538654 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.538654 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097184 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097184 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.285654 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.285654 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.625716 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.625716 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034120 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.059134 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097184 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.344858 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.221624 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034120 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.059134 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097184 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.344858 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.221624 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.538617 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.538617 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097222 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097222 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.285670 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.285670 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.625907 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.625907 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034110 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.059336 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097222 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.344861 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.221649 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034110 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.059336 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097222 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.344861 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.221649 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1126,24 +1125,24 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 1197492 # number of writebacks -system.cpu1.l2cache.writebacks::total 1197492 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 1199052 # number of writebacks +system.cpu1.l2cache.writebacks::total 1199052 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 22219563 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11356978 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_requests 22219600 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11357015 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1770232 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1770046 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 186 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1768706 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1768522 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 184 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.trans_dist::ReadReq 610577 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 9722063 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 5621 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 5621 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4030572 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6737791 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 148574 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 159002 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 307576 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4030758 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6737605 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 148621 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158992 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 307613 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 1315491 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 1315491 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4805393 # Transaction distribution @@ -1151,27 +1150,27 @@ system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4306093 system.cpu1.toL2Bus.trans_dist::InvalidateReq 435608 # Transaction distribution system.cpu1.toL2Bus.trans_dist::InvalidateResp 435608 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14415927 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18715946 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18716020 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368094 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 841114 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 34341081 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 34341155 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 615058056 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 741477723 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1472376 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3364456 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size::total 1361372611 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5728933 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 28119998 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.072981 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.260131 # Request fanout histogram +system.cpu1.toL2Bus.snoops 5725702 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 28118123 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.072932 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.260049 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 26067955 92.70% 92.70% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2051857 7.30% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 186 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 26067606 92.71% 92.71% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2050333 7.29% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 184 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 28119998 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 28118123 # Request fanout histogram system.iobus.trans_dist::ReadReq 40311 # Transaction distribution system.iobus.trans_dist::ReadResp 40311 # Transaction distribution system.iobus.trans_dist::WriteReq 136636 # Transaction distribution @@ -1280,193 +1279,204 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1772759 # number of replacements -system.l2c.tags.tagsinuse 62623.636789 # Cycle average of tags in use -system.l2c.tags.total_refs 4610700 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1831680 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.517197 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 34513.616341 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 69.391588 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 102.836315 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3358.057391 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 7927.916069 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 241.822259 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 388.027254 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2900.077291 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 13121.892282 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.526636 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001059 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.001569 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.051240 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.120970 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003690 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.005921 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.044252 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.200224 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.955561 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 194 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 58727 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 191 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 457 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3184 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5196 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 49841 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.002960 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.896103 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 73222946 # Number of tag accesses -system.l2c.tags.data_accesses 73222946 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 2756862 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2756862 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 19292 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 16576 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 35868 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2708 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 2412 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 5120 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 311775 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 276099 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 587874 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6229 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4594 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 436955 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 721918 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5484 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3754 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 425773 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 684534 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2289241 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6229 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4594 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 436955 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 1033693 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5484 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3754 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 425773 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 960633 # number of demand (read+write) hits -system.l2c.demand_hits::total 2877115 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6229 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4594 # number of overall hits -system.l2c.overall_hits::cpu0.inst 436955 # number of overall hits -system.l2c.overall_hits::cpu0.data 1033693 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5484 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3754 # number of overall hits -system.l2c.overall_hits::cpu1.inst 425773 # number of overall hits -system.l2c.overall_hits::cpu1.data 960633 # number of overall hits -system.l2c.overall_hits::total 2877115 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 65194 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 61685 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 126879 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 6603 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 6332 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 12935 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 822855 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 542831 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 1365686 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2437 # number of ReadSharedReq misses +system.l2c.tags.replacements 1766126 # number of replacements +system.l2c.tags.tagsinuse 63106.596515 # Cycle average of tags in use +system.l2c.tags.total_refs 4618110 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1825499 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.529780 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 514828500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 34858.975183 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 68.002297 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 102.298868 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3405.442592 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 8003.318713 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 244.723732 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 389.512702 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2881.151775 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 13153.170652 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.531906 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001038 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.001561 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.051963 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.122121 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003734 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.005943 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.043963 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.200701 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.962930 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 203 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 59170 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 200 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 472 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3156 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5264 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 50220 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.003098 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.902863 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 73355182 # Number of tag accesses +system.l2c.tags.data_accesses 73355182 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 2757627 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2757627 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 19019 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 16164 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 35183 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2641 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 2463 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 5104 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 198159 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 177179 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 375338 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6315 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4649 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 438189 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 723007 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5487 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3779 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 426355 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 685222 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 2293003 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 118931 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 103897 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 222828 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6315 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4649 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 438189 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 921166 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5487 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3779 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 426355 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 862401 # number of demand (read+write) hits +system.l2c.demand_hits::total 2668341 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6315 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4649 # number of overall hits +system.l2c.overall_hits::cpu0.inst 438189 # number of overall hits +system.l2c.overall_hits::cpu0.data 921166 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5487 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3779 # number of overall hits +system.l2c.overall_hits::cpu1.inst 426355 # number of overall hits +system.l2c.overall_hits::cpu1.data 862401 # number of overall hits +system.l2c.overall_hits::total 2668341 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 65379 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 61938 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 127317 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 6666 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 6353 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 13019 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 385718 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 415753 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 801471 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2451 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2053 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 58588 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 182243 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3396 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3346 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 41232 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 187565 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 480860 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2437 # number of demand (read+write) misses +system.l2c.ReadSharedReq_misses::cpu0.inst 57980 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 180523 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3403 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3345 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 40834 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 186956 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 477545 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 477269 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 162394 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 639663 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2451 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2053 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 58588 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1005098 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3396 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 3346 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 41232 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 730396 # number of demand (read+write) misses -system.l2c.demand_misses::total 1846546 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2437 # number of overall misses +system.l2c.demand_misses::cpu0.inst 57980 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 566241 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3403 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 3345 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 40834 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 602709 # number of demand (read+write) misses +system.l2c.demand_misses::total 1279016 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2451 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2053 # number of overall misses -system.l2c.overall_misses::cpu0.inst 58588 # number of overall misses -system.l2c.overall_misses::cpu0.data 1005098 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3396 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 3346 # number of overall misses -system.l2c.overall_misses::cpu1.inst 41232 # number of overall misses -system.l2c.overall_misses::cpu1.data 730396 # number of overall misses -system.l2c.overall_misses::total 1846546 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 2756862 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 2756862 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 84486 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 78261 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 162747 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 9311 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 8744 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 18055 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 1134630 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 818930 # 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number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8666 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6647 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 495543 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 2038791 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 8880 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7100 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 467005 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 1691029 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 4723661 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8666 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6647 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 495543 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 2038791 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 8880 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7100 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 467005 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 1691029 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4723661 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.771654 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.788196 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.779609 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.709161 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.724154 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.716422 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.725219 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.662854 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.699076 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.281214 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.308861 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.118230 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.201560 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.382432 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.471268 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.088290 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.215073 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.173589 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.281214 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.308861 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.118230 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.492987 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.382432 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.471268 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.088290 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.431924 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.390914 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.281214 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.308861 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.118230 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.492987 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.382432 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.471268 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.088290 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.431924 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.390914 # miss rate for overall accesses +system.l2c.overall_misses::cpu0.inst 57980 # number of overall misses +system.l2c.overall_misses::cpu0.data 566241 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3403 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 3345 # number of overall misses +system.l2c.overall_misses::cpu1.inst 40834 # number of overall misses +system.l2c.overall_misses::cpu1.data 602709 # number of overall misses +system.l2c.overall_misses::total 1279016 # number of overall misses +system.l2c.WritebackDirty_accesses::writebacks 2757627 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 2757627 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 84398 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 78102 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 162500 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 9307 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 8816 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 18123 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 583877 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 592932 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 1176809 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8766 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6702 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 496169 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 903530 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8890 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7124 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 467189 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 872178 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 2770548 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 596200 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 266291 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 862491 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8766 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6702 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 496169 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1487407 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 8890 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7124 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 467189 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 1465110 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3947357 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8766 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6702 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 496169 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1487407 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 8890 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7124 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 467189 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 1465110 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3947357 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.774651 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.793040 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.783489 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.716235 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.720622 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.718369 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.660615 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.701182 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.681054 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.279603 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.306326 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.116855 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.199797 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.382790 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.469540 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.087404 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.214355 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.172365 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.800518 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.609837 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.741646 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.279603 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.306326 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.116855 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.380690 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.382790 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.469540 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.087404 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.411375 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.324018 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.279603 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.306326 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.116855 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.380690 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.382790 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.469540 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.087404 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.411375 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.324018 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1475,51 +1485,51 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1476146 # number of writebacks -system.l2c.writebacks::total 1476146 # number of writebacks +system.l2c.writebacks::writebacks 1473799 # number of writebacks +system.l2c.writebacks::total 1473799 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 82185 # Transaction distribution -system.membus.trans_dist::ReadResp 571969 # Transaction distribution +system.membus.trans_dist::ReadResp 568654 # Transaction distribution system.membus.trans_dist::WriteReq 38847 # Transaction distribution system.membus.trans_dist::WriteResp 38847 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1582840 # Transaction distribution -system.membus.trans_dist::CleanEvict 248395 # Transaction distribution -system.membus.trans_dist::UpgradeReq 346027 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 310425 # Transaction distribution -system.membus.trans_dist::UpgradeResp 161621 # Transaction distribution -system.membus.trans_dist::ReadExReq 1349349 # Transaction distribution -system.membus.trans_dist::ReadExResp 1343882 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 489784 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1580493 # Transaction distribution +system.membus.trans_dist::CleanEvict 246676 # Transaction distribution +system.membus.trans_dist::UpgradeReq 346899 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 310542 # Transaction distribution +system.membus.trans_dist::UpgradeResp 162598 # Transaction distribution +system.membus.trans_dist::ReadExReq 787734 # Transaction distribution +system.membus.trans_dist::ReadExResp 783864 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 486469 # Transaction distribution +system.membus.trans_dist::InvalidateReq 741739 # Transaction distribution +system.membus.trans_dist::InvalidateResp 741739 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27742 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6280303 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6430721 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6419962 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6570380 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346906 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 346906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6777627 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6917286 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155691 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55484 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 211450588 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 211661967 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 175247068 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 175458447 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399552 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7399552 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 219061519 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 182857999 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4554580 # Request fanout histogram +system.membus.snoop_fanout::samples 4621584 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4554580 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4621584 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4554580 # Request fanout histogram +system.membus.snoop_fanout::total 4621584 # Request fanout histogram system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks @@ -1572,41 +1582,43 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 11149388 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5745365 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1662887 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 135292 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 121804 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 13488 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 11149977 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5745476 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1663139 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 131712 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 118684 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 13028 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 82187 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3554010 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3554361 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 38847 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 38847 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 2756862 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2018423 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 360088 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 315545 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 675633 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2226645 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2226645 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3471823 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9531217 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8234338 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17765555 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 294166716 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 247379555 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 541546271 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2005695 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 13274431 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.283856 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.453116 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 2757627 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2018256 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 359820 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 315646 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 675466 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1363961 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1363961 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3472174 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 862491 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 862491 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9530168 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8235967 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17766135 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255951612 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 230454307 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 486405919 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1999071 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 13268387 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.283691 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.452962 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 9519891 71.72% 71.72% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3741052 28.18% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 13488 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 9517290 71.73% 71.73% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3738069 28.17% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 13028 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 13274431 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 13268387 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index f426a8e38..734b4a589 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111167 # Nu sim_ticks 51111167216500 # Number of ticks simulated final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1152055 # Simulator instruction rate (inst/s) -host_op_rate 1353914 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59949794817 # Simulator tick rate (ticks/s) -host_mem_usage 676672 # Number of bytes of host memory used -host_seconds 852.57 # Real time elapsed on the host +host_inst_rate 1770185 # Simulator instruction rate (inst/s) +host_op_rate 2080350 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 92115569363 # Simulator tick rate (ticks/s) +host_mem_usage 676500 # Number of bytes of host memory used +host_seconds 554.86 # Real time elapsed on the host sim_insts 982203438 # Number of instructions simulated sim_ops 1154301153 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -16,9 +16,9 @@ system.clk_domain.clock 1000 # Cl system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 5483956 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 110253960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 74912136 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory -system.physmem.bytes_read::total 116962748 # Number of bytes read from this memory +system.physmem.bytes_read::total 81620924 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 5483956 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 5483956 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 103277504 # Number of bytes written to this memory @@ -27,18 +27,18 @@ system.physmem.bytes_written::total 103298084 # Nu system.physmem.num_reads::cpu.dtb.walker 6476 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5837 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 126094 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1722731 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1170515 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1867963 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1315747 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1613711 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::total 1616284 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 8109 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 7309 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 107295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2157140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1465671 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2288399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1596929 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 107295 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 107295 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 2020645 # Write bandwidth from this memory (bytes/s) @@ -48,9 +48,9 @@ system.physmem.bw_total::writebacks 2020645 # To system.physmem.bw_total::cpu.dtb.walker 8109 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 7309 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 107295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2157543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1466073 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4309446 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3617977 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -721,11 +721,11 @@ system.membus.trans_dist::CleanEvict 226320 # Tr system.membus.trans_dist::UpgradeReq 40491 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 40492 # Transaction distribution -system.membus.trans_dist::ReadExReq 1379258 # Transaction distribution -system.membus.trans_dist::ReadExResp 1379258 # Transaction distribution +system.membus.trans_dist::ReadExReq 827042 # Transaction distribution +system.membus.trans_dist::ReadExResp 827042 # Transaction distribution system.membus.trans_dist::ReadSharedReq 448267 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution +system.membus.trans_dist::InvalidateReq 658880 # Transaction distribution +system.membus.trans_dist::InvalidateResp 658880 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) @@ -737,11 +737,11 @@ system.membus.pkt_count::total 6009963 # Pa system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 213041440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 213210490 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177699616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177868666 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 220601274 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 185259450 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 3924997 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 1114600cf..f3542cbe8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,167 +1,167 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.602418 # Number of seconds simulated -sim_ticks 47602418253500 # Number of ticks simulated -final_tick 47602418253500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.579919 # Number of seconds simulated +sim_ticks 47579919171500 # Number of ticks simulated +final_tick 47579919171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 704375 # Simulator instruction rate (inst/s) -host_op_rate 828740 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38464814262 # Simulator tick rate (ticks/s) -host_mem_usage 746580 # Number of bytes of host memory used -host_seconds 1237.56 # Real time elapsed on the host -sim_insts 871704321 # Number of instructions simulated -sim_ops 1025613965 # Number of ops (including micro ops) simulated +host_inst_rate 994477 # Simulator instruction rate (inst/s) +host_op_rate 1169790 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52043300787 # Simulator tick rate (ticks/s) +host_mem_usage 760992 # Number of bytes of host memory used +host_seconds 914.24 # Real time elapsed on the host +sim_insts 909188095 # Number of instructions simulated +sim_ops 1069465904 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 106624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 114944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3306740 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 39207752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 13461760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 71360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 71552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2461816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 13970768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 8718016 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 430784 # Number of bytes read from this memory -system.physmem.bytes_read::total 81922116 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3306740 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2461816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5768556 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 69209472 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 95808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 82560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3301172 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 14310344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 18775424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 218368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 230464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3000056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 12646096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 13033600 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 427520 # Number of bytes read from this memory +system.physmem.bytes_read::total 66121412 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3301172 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3000056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6301228 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 84303296 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 69230056 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1666 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1796 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 92075 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 612634 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 210340 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1115 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1118 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 38554 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 218306 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 136219 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6731 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1320554 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1081398 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 84323880 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1497 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1290 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 91988 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 223612 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 293366 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3412 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3601 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 46964 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 197608 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 203650 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6680 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1073668 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1317239 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1083972 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2240 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 69466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 823650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 282796 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 51716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 293489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 183142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1720965 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69466 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 51716 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 121182 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1453907 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 432 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1319813 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2014 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 300764 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 394608 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4589 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 4844 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 63053 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 265786 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 273931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1389692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69382 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 63053 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 132435 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1771825 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1454339 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1453907 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2415 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 824083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 282796 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 51716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 293489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 183142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3175304 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1320554 # Number of read requests accepted -system.physmem.writeReqs 1083972 # Number of write requests accepted -system.physmem.readBursts 1320554 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1083972 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 84482048 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 33408 # Total number of bytes read from write queue -system.physmem.bytesWritten 69229248 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 81922116 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 69230056 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 522 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1772258 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1771825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69382 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 301197 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 394608 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 4844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 63053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 265786 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 273931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3161949 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1073668 # Number of read requests accepted +system.physmem.writeReqs 1319813 # Number of write requests accepted +system.physmem.readBursts 1073668 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1319813 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 68691008 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 23744 # Total number of bytes read from write queue +system.physmem.bytesWritten 84321664 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 66121412 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 84323880 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 371 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2261 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 79060 # Per bank write bursts -system.physmem.perBankRdBursts::1 84693 # Per bank write bursts -system.physmem.perBankRdBursts::2 79264 # Per bank write bursts -system.physmem.perBankRdBursts::3 82906 # Per bank write bursts -system.physmem.perBankRdBursts::4 76161 # Per bank write bursts -system.physmem.perBankRdBursts::5 86285 # Per bank write bursts -system.physmem.perBankRdBursts::6 80943 # Per bank write bursts -system.physmem.perBankRdBursts::7 81570 # Per bank write bursts -system.physmem.perBankRdBursts::8 74520 # Per bank write bursts -system.physmem.perBankRdBursts::9 121634 # Per bank write bursts -system.physmem.perBankRdBursts::10 72298 # Per bank write bursts -system.physmem.perBankRdBursts::11 79752 # Per bank write bursts -system.physmem.perBankRdBursts::12 77563 # Per bank write bursts -system.physmem.perBankRdBursts::13 85585 # Per bank write bursts -system.physmem.perBankRdBursts::14 78768 # Per bank write bursts -system.physmem.perBankRdBursts::15 79030 # Per bank write bursts -system.physmem.perBankWrBursts::0 65472 # Per bank write bursts -system.physmem.perBankWrBursts::1 70626 # Per bank write bursts -system.physmem.perBankWrBursts::2 66791 # Per bank write bursts -system.physmem.perBankWrBursts::3 69615 # Per bank write bursts -system.physmem.perBankWrBursts::4 63756 # Per bank write bursts -system.physmem.perBankWrBursts::5 71331 # Per bank write bursts -system.physmem.perBankWrBursts::6 67500 # Per bank write bursts -system.physmem.perBankWrBursts::7 68943 # Per bank write bursts -system.physmem.perBankWrBursts::8 63410 # Per bank write bursts -system.physmem.perBankWrBursts::9 68673 # Per bank write bursts -system.physmem.perBankWrBursts::10 63007 # Per bank write bursts -system.physmem.perBankWrBursts::11 67951 # Per bank write bursts -system.physmem.perBankWrBursts::12 66506 # Per bank write bursts -system.physmem.perBankWrBursts::13 73077 # Per bank write bursts -system.physmem.perBankWrBursts::14 66769 # Per bank write bursts -system.physmem.perBankWrBursts::15 68280 # Per bank write bursts +system.physmem.perBankRdBursts::0 64017 # Per bank write bursts +system.physmem.perBankRdBursts::1 68044 # Per bank write bursts +system.physmem.perBankRdBursts::2 61517 # Per bank write bursts +system.physmem.perBankRdBursts::3 65955 # Per bank write bursts +system.physmem.perBankRdBursts::4 65874 # Per bank write bursts +system.physmem.perBankRdBursts::5 75726 # Per bank write bursts +system.physmem.perBankRdBursts::6 64933 # Per bank write bursts +system.physmem.perBankRdBursts::7 65424 # Per bank write bursts +system.physmem.perBankRdBursts::8 62003 # Per bank write bursts +system.physmem.perBankRdBursts::9 113372 # Per bank write bursts +system.physmem.perBankRdBursts::10 63434 # Per bank write bursts +system.physmem.perBankRdBursts::11 64718 # Per bank write bursts +system.physmem.perBankRdBursts::12 56904 # Per bank write bursts +system.physmem.perBankRdBursts::13 64084 # Per bank write bursts +system.physmem.perBankRdBursts::14 56898 # Per bank write bursts +system.physmem.perBankRdBursts::15 60394 # Per bank write bursts +system.physmem.perBankWrBursts::0 80527 # Per bank write bursts +system.physmem.perBankWrBursts::1 85904 # Per bank write bursts +system.physmem.perBankWrBursts::2 80420 # Per bank write bursts +system.physmem.perBankWrBursts::3 86054 # Per bank write bursts +system.physmem.perBankWrBursts::4 85401 # Per bank write bursts +system.physmem.perBankWrBursts::5 88715 # Per bank write bursts +system.physmem.perBankWrBursts::6 80808 # Per bank write bursts +system.physmem.perBankWrBursts::7 81222 # Per bank write bursts +system.physmem.perBankWrBursts::8 80522 # Per bank write bursts +system.physmem.perBankWrBursts::9 87926 # Per bank write bursts +system.physmem.perBankWrBursts::10 79616 # Per bank write bursts +system.physmem.perBankWrBursts::11 81105 # Per bank write bursts +system.physmem.perBankWrBursts::12 77689 # Per bank write bursts +system.physmem.perBankWrBursts::13 84231 # Per bank write bursts +system.physmem.perBankWrBursts::14 77252 # Per bank write bursts +system.physmem.perBankWrBursts::15 80134 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 42 # Number of times write queue was full causing retry -system.physmem.totGap 47602414888000 # Total gap between requests +system.physmem.numWrRetry 116 # Number of times write queue was full causing retry +system.physmem.totGap 47579915806000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1277329 # Read request sizes (log2) +system.physmem.readPktSize::6 1030443 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1081398 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1104957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 68933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 25891 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 22057 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 19390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 16894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 14853 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 11934 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 867 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 305 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1317239 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 761963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 94096 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 44762 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 38689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 33193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 29336 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 25572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 22083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 17610 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1054 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 470 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 138 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 78 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -188,167 +188,168 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 18639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 22143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 48134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 53739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 58424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 62461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 64493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 65899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 66079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 68869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 71761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 68201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 69441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 73837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 67956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 64592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 63507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 42279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 54831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 58608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 65543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 69713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 74423 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 78144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 80302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 80268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 82803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 85991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 82780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 84137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 91440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 82956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 77042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 74792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 244 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 129 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 850234 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 180.786598 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 111.487051 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 240.213026 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 527654 62.06% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 158419 18.63% 80.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52205 6.14% 86.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 27644 3.25% 90.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18445 2.17% 92.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11596 1.36% 93.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9081 1.07% 94.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9121 1.07% 95.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 36069 4.24% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 850234 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60429 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.843949 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 329.896328 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 60426 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60429 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60429 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.900462 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.285869 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.671229 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 56824 94.03% 94.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1552 2.57% 96.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 279 0.46% 97.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 180 0.30% 97.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 145 0.24% 97.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 117 0.19% 97.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 182 0.30% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 82 0.14% 98.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 275 0.46% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 67 0.11% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 37 0.06% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 44 0.07% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 253 0.42% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 30 0.05% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 37 0.06% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 108 0.18% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 152 0.25% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 5 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::52 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 302 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1107709 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 138.133954 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 95.206974 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 184.490982 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 762645 68.85% 68.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 210995 19.05% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 48832 4.41% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 22284 2.01% 94.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 16979 1.53% 95.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10320 0.93% 96.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6180 0.56% 97.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5743 0.52% 97.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23731 2.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1107709 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 70958 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.125666 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 121.252784 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 70954 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 70958 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 70958 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.567688 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.991036 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.306981 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 58539 82.50% 82.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 9965 14.04% 96.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 642 0.90% 97.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 182 0.26% 97.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 135 0.19% 97.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 121 0.17% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 191 0.27% 98.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 83 0.12% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 286 0.40% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 59 0.08% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 34 0.05% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 42 0.06% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 259 0.37% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 42 0.06% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 31 0.04% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 116 0.16% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 167 0.24% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 16 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60429 # Writes before turning the bus around for reads -system.physmem.totQLat 28489428593 # Total ticks spent queuing -system.physmem.totMemAccLat 53240028593 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6600160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 21582.38 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::100-103 4 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 4 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 8 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 8 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 70958 # Writes before turning the bus around for reads +system.physmem.totQLat 35332291342 # Total ticks spent queuing +system.physmem.totMemAccLat 55456610092 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5366485000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32919.40 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40332.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.45 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.72 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.45 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 51669.40 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.77 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.39 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.77 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.12 # Average write queue length when enqueuing -system.physmem.readRowHits 1056858 # Number of row buffer hits during reads -system.physmem.writeRowHits 494645 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.06 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 45.73 # Row buffer hit rate for writes -system.physmem.avgGap 19797005.68 # Average gap between requests -system.physmem.pageHitRate 64.60 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3250149840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1773395250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5076832800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3525340320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3109158352560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1224482966955 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27487341349500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31834608387225 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.760359 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45727050942416 # Time in different power states -system.physmem_0.memoryStateTime::REF 1589549260000 # Time in different power states +system.physmem.avgRdQLen 1.40 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.48 # Average write queue length when enqueuing +system.physmem.readRowHits 793862 # Number of row buffer hits during reads +system.physmem.writeRowHits 489250 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.96 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 37.13 # Row buffer hit rate for writes +system.physmem.avgGap 19878961.15 # Average gap between requests +system.physmem.pageHitRate 53.67 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4296030480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2344064250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4145606400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4335450480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3107688614160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1225363115070 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27473067932250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31821240813090 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.795690 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45703113685218 # Time in different power states +system.physmem_0.memoryStateTime::REF 1588797860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 285815210084 # Time in different power states +system.physmem_0.memoryStateTime::ACT 288003145282 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3177619200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1733820000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5219370000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3484121040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3109158352560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1221031665405 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27490368798750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31834173746955 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.751229 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45732072121963 # Time in different power states -system.physmem_1.memoryStateTime::REF 1589549260000 # Time in different power states +system.physmem_1.actEnergy 4078249560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2225235375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4226055600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4202118000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3107688614160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1219254807825 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27478426088250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31820101168770 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.771738 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45712034121275 # Time in different power states +system.physmem_1.memoryStateTime::REF 1588797860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 280793976787 # Time in different power states +system.physmem_1.memoryStateTime::ACT 279086495725 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -379,9 +380,9 @@ system.realview.nvmem.bw_total::total 4 # To system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1674 # Number of DMA write transactions. +system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -412,70 +413,70 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 112758 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 112758 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10038 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 87373 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 24 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 112734 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.230631 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 77.436531 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 112733 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 116306 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 116306 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10885 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88573 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 116284 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.223591 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 76.245351 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 116283 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 112734 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 97435 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 23281.346539 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21381.718359 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 19258.937396 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 96246 98.78% 98.78% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 178 0.18% 98.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 868 0.89% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 20 0.02% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 55 0.06% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 17 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 37 0.04% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkWaitTime::total 116284 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 99480 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22519.581825 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21136.105654 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 15840.339731 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 98726 99.24% 99.24% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 154 0.15% 99.40% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 495 0.50% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 15 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 37 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 19 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 26 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 97435 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 8883013024 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.766632 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.422974 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 2073007704 23.34% 23.34% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 6810005320 76.66% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 8883013024 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 87373 89.70% 89.70% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10038 10.30% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 97411 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 112758 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 99480 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 8374009004 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.680543 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.466266 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 2675132860 31.95% 31.95% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 5698876144 68.05% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 8374009004 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 88573 89.06% 89.06% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10885 10.94% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 99458 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 116306 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 112758 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 97411 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 116306 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 99458 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 97411 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 210169 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 99458 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 215764 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 88968055 # DTB read hits -system.cpu0.dtb.read_misses 85634 # DTB read misses -system.cpu0.dtb.write_hits 80360369 # DTB write hits -system.cpu0.dtb.write_misses 27124 # DTB write misses +system.cpu0.dtb.read_hits 86290817 # DTB read hits +system.cpu0.dtb.read_misses 86990 # DTB read misses +system.cpu0.dtb.write_hits 77965379 # DTB write hits +system.cpu0.dtb.write_misses 29316 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 39919 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 39097 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 36691 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 3879 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4448 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10141 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 89053689 # DTB read accesses -system.cpu0.dtb.write_accesses 80387493 # DTB write accesses +system.cpu0.dtb.perms_faults 9789 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 86377807 # DTB read accesses +system.cpu0.dtb.write_accesses 77994695 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 169328424 # DTB hits -system.cpu0.dtb.misses 112758 # DTB misses -system.cpu0.dtb.accesses 169441182 # DTB accesses +system.cpu0.dtb.hits 164256196 # DTB hits +system.cpu0.dtb.misses 116306 # DTB misses +system.cpu0.dtb.accesses 164372502 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -505,236 +506,239 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 62308 # Table walker walks requested -system.cpu0.itb.walker.walksLong 62308 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 814 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 55869 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 62308 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 62308 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 62308 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 56683 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 26679.454157 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23625.111342 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 26536.909948 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 55487 97.89% 97.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 42 0.07% 97.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 988 1.74% 99.71% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 26 0.05% 99.75% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 65 0.11% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.02% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 49 0.09% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 56683 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 53337 # Table walker walks requested +system.cpu0.itb.walker.walksLong 53337 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 559 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 47077 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 53337 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 53337 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 53337 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 47636 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25421.330506 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23137.989766 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 22597.528238 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 46963 98.59% 98.59% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 37 0.08% 98.66% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 536 1.13% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 19 0.04% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 27 0.06% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.03% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 23 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 11 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 47636 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 1979242204 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 1979242204 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 1979242204 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 55869 98.56% 98.56% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 814 1.44% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 56683 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 47077 98.83% 98.83% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 559 1.17% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 47636 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 62308 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 62308 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53337 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53337 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56683 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56683 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 118991 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 472241024 # ITB inst hits -system.cpu0.itb.inst_misses 62308 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 47636 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 47636 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 100973 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 461259285 # ITB inst hits +system.cpu0.itb.inst_misses 53337 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 39919 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 28001 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 25459 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 472303332 # ITB inst accesses -system.cpu0.itb.hits 472241024 # DTB hits -system.cpu0.itb.misses 62308 # DTB misses -system.cpu0.itb.accesses 472303332 # DTB accesses -system.cpu0.numCycles 95204836507 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 461312622 # ITB inst accesses +system.cpu0.itb.hits 461259285 # DTB hits +system.cpu0.itb.misses 53337 # DTB misses +system.cpu0.itb.accesses 461312622 # DTB accesses +system.cpu0.numCycles 95159838338 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5131 # number of quiesce instructions executed -system.cpu0.committedInsts 471986732 # Number of instructions committed -system.cpu0.committedOps 554132163 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 509304939 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 463756 # Number of float alu accesses -system.cpu0.num_func_calls 28209702 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 71348449 # number of instructions that are conditional controls -system.cpu0.num_int_insts 509304939 # number of integer instructions -system.cpu0.num_fp_insts 463756 # number of float instructions -system.cpu0.num_int_register_reads 736700300 # number of times the integer registers were read -system.cpu0.num_int_register_writes 403898232 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 771652 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 344244 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 122509563 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 122079243 # number of times the CC registers were written -system.cpu0.num_mem_refs 169317654 # number of memory refs -system.cpu0.num_load_insts 88962856 # Number of load instructions -system.cpu0.num_store_insts 80354798 # Number of store instructions -system.cpu0.num_idle_cycles 93934250531.242035 # Number of idle cycles -system.cpu0.num_busy_cycles 1270585975.757973 # Number of busy cycles -system.cpu0.not_idle_fraction 0.013346 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.986654 # Percentage of idle cycles -system.cpu0.Branches 105166310 # Number of branches fetched +system.cpu0.kern.inst.quiesce 13594 # number of quiesce instructions executed +system.cpu0.committedInsts 460977499 # Number of instructions committed +system.cpu0.committedOps 540688150 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 495872658 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 377758 # Number of float alu accesses +system.cpu0.num_func_calls 27096084 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 70442961 # number of instructions that are conditional controls +system.cpu0.num_int_insts 495872658 # number of integer instructions +system.cpu0.num_fp_insts 377758 # number of float instructions +system.cpu0.num_int_register_reads 724744849 # number of times the integer registers were read +system.cpu0.num_int_register_writes 393986605 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 623895 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 289632 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 122670714 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 122315787 # number of times the CC registers were written +system.cpu0.num_mem_refs 164249297 # number of memory refs +system.cpu0.num_load_insts 86287437 # Number of load instructions +system.cpu0.num_store_insts 77961860 # Number of store instructions +system.cpu0.num_idle_cycles 93938070746.252213 # Number of idle cycles +system.cpu0.num_busy_cycles 1221767591.747779 # Number of busy cycles +system.cpu0.not_idle_fraction 0.012839 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.987161 # Percentage of idle cycles +system.cpu0.Branches 102925889 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 383762588 69.22% 69.22% # Class of executed instruction -system.cpu0.op_class::IntMult 1237276 0.22% 69.44% # Class of executed instruction -system.cpu0.op_class::IntDiv 66509 0.01% 69.45% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 45552 0.01% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::MemRead 88962856 16.05% 85.51% # Class of executed instruction -system.cpu0.op_class::MemWrite 80354798 14.49% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 375485543 69.40% 69.40% # Class of executed instruction +system.cpu0.op_class::IntMult 1178634 0.22% 69.62% # Class of executed instruction +system.cpu0.op_class::IntDiv 59866 0.01% 69.63% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.63% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 39720 0.01% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::MemRead 86287437 15.95% 85.59% # Class of executed instruction +system.cpu0.op_class::MemWrite 77961860 14.41% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 554429579 # Class of executed instruction -system.cpu0.dcache.tags.replacements 5824476 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.611071 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 163267162 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5824987 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.028760 # Average number of references to valid blocks. +system.cpu0.op_class::total 541013060 # Class of executed instruction +system.cpu0.dcache.tags.replacements 5729731 # number of replacements +system.cpu0.dcache.tags.tagsinuse 475.426094 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 158277130 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5730241 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.621374 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 6293818000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.611071 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.989475 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.989475 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 344508686 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 344508686 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 82887500 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 82887500 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 75943802 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 75943802 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 196404 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 196404 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 140054 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 140054 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1847526 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1847526 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1825483 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1825483 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 158831302 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 158831302 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 159027706 # number of overall hits -system.cpu0.dcache.overall_hits::total 159027706 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3189198 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3189198 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1439126 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1439126 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 657536 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 657536 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 792800 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 792800 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 174919 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 174919 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195568 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 195568 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4628324 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4628324 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5285860 # number of overall misses -system.cpu0.dcache.overall_misses::total 5285860 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52614413500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 52614413500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36171191500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 36171191500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 66218479500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 66218479500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2808474500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2808474500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5670137000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5670137000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 6661000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 6661000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 88785605000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 88785605000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 88785605000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 88785605000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 86076698 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 86076698 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 77382928 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 77382928 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 853940 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 853940 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 932854 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 932854 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2022445 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2022445 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2021051 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2021051 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 163459626 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 163459626 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 164313566 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 164313566 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037051 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037051 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018597 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018597 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770003 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770003 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.849865 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.849865 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086489 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086489 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.096765 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.096765 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028315 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.028315 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032169 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.032169 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16497.694248 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 16497.694248 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25134.138012 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 25134.138012 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 83524.822780 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 83524.822780 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16055.857283 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16055.857283 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28993.173730 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28993.173730 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.426094 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.928567 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.928567 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 399 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 334208607 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 334208607 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 80244173 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 80244173 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73488227 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73488227 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200421 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 200421 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 184838 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 184838 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1883304 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1883304 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1842196 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1842196 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 153732400 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 153732400 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 153932821 # number of overall hits +system.cpu0.dcache.overall_hits::total 153932821 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3080001 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3080001 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1447988 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1447988 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 695954 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 695954 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 768699 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 768699 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 158470 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 158470 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 198134 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 198134 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4527989 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4527989 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5223943 # number of overall misses +system.cpu0.dcache.overall_misses::total 5223943 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52478340000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 52478340000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 38322628500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 38322628500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 49559521500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 49559521500 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2516267500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2516267500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5589291500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 5589291500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2738500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2738500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 90800968500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 90800968500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 90800968500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 90800968500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 83324174 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 83324174 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74936215 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 74936215 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 896375 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 896375 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 953537 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 953537 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2041774 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2041774 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2040330 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2040330 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 158260389 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 158260389 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 159156764 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 159156764 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036964 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036964 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019323 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.019323 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.776409 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.776409 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.806155 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.806155 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077614 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.077614 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097109 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097109 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028611 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.028611 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032823 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.032823 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17038.416546 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 17038.416546 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 26466.122993 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 26466.122993 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 64471.947407 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 64471.947407 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15878.510128 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15878.510128 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28209.653568 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28209.653568 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19183.100621 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19183.100621 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16796.813574 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 16796.813574 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20053.266141 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20053.266141 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17381.692048 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17381.692048 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -743,158 +747,158 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 5824476 # number of writebacks -system.cpu0.dcache.writebacks::total 5824476 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 27468 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 27468 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21247 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21247 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43989 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43989 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 48715 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 48715 # 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number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 130930 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195568 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 195568 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4579609 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4579609 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5235861 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5235861 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14992 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14992 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15725 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 15725 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 30717 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 30717 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 47545298500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 47545298500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 34168378500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 34168378500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16138287000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16138287000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 65425679500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 65425679500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1807284000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1807284000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5474645000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5474645000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 6585000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 6585000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 81713677000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 81713677000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 97851964000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 97851964000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2585195500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2585195500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2654242000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2654242000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5239437500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5239437500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036732 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036732 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018323 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018323 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.768499 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.768499 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.849865 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.849865 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064738 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064738 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.096765 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.096765 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028017 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028017 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031865 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031865 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15037.747847 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15037.747847 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24098.232994 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24098.232994 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24591.600483 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24591.600483 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 82524.822780 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 82524.822780 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13803.436951 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13803.436951 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27993.562341 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27993.562341 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5729731 # number of writebacks +system.cpu0.dcache.writebacks::total 5729731 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28073 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 28073 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21239 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21239 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41058 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41058 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 49312 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 49312 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 49312 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 49312 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3051928 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3051928 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1426749 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1426749 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 694810 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 694810 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 768699 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 768699 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 117412 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 117412 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 198134 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 198134 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4478677 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4478677 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5173487 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5173487 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 28514 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 28514 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 27871 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27871 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 56385 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 56385 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 47315434500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 47315434500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 36384996000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 36384996000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17003029000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17003029000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 48790822500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 48790822500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1643233500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1643233500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5391195500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5391195500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2700500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2700500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 83700430500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 83700430500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 100703459500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 100703459500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5280351500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5280351500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5086850000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5086850000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10367201500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10367201500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036627 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036627 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019040 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019040 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.775133 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.775133 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.806155 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.806155 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057505 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057505 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097109 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097109 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028299 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028299 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032506 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032506 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15503.456995 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15503.456995 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25502.030140 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25502.030140 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24471.479973 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24471.479973 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 63471.947407 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 63471.947407 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13995.447654 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13995.447654 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27209.845357 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27209.845357 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17842.937465 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17842.937465 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18688.800944 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18688.800944 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172438.333778 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172438.333778 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 168791.224165 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168791.224165 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 170571.263470 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 170571.263470 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18688.650800 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18688.650800 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19465.296714 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19465.296714 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185184.523392 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185184.523392 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182514.082738 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 182514.082738 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 183864.529573 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 183864.529573 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 5187208 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.827248 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 467053304 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5187720 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 90.030554 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 59167640000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.827248 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999663 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999663 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 4741257 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.854043 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 456517510 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 4741769 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 96.275780 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 46470060000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.854043 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999715 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999715 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 349 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 113 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 949669768 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 949669768 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 467053304 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 467053304 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 467053304 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 467053304 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 467053304 # number of overall hits -system.cpu0.icache.overall_hits::total 467053304 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5187720 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5187720 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5187720 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5187720 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5187720 # number of overall misses -system.cpu0.icache.overall_misses::total 5187720 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 57877602000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 57877602000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 57877602000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 57877602000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 57877602000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 57877602000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 472241024 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 472241024 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 472241024 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 472241024 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 472241024 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 472241024 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010985 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.010985 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010985 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.010985 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010985 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.010985 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11156.654947 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 11156.654947 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11156.654947 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 11156.654947 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11156.654947 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 11156.654947 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 927260344 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 927260344 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 456517510 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 456517510 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 456517510 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 456517510 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 456517510 # number of overall hits +system.cpu0.icache.overall_hits::total 456517510 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 4741775 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 4741775 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 4741775 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 4741775 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 4741775 # number of overall misses +system.cpu0.icache.overall_misses::total 4741775 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 53890518500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 53890518500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 53890518500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 53890518500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 53890518500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 53890518500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 461259285 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 461259285 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 461259285 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 461259285 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 461259285 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 461259285 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010280 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.010280 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010280 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.010280 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010280 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.010280 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11365.051800 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 11365.051800 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11365.051800 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 11365.051800 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11365.051800 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 11365.051800 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -903,252 +907,251 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # 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number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4741775 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 4741775 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 4741775 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 4741775 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 4741775 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 4741775 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 55283742000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 55283742000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 55283742000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 55283742000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 55283742000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 55283742000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 51519631500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 51519631500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 51519631500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 51519631500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 51519631500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 51519631500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5954209000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 5954209000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010985 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010985 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010985 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010985 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010985 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010985 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10656.654947 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10656.654947 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10656.654947 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10656.654947 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10656.654947 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10656.654947 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010280 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010280 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010280 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010280 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010280 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010280 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10865.051906 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10865.051906 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10865.051906 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10865.051906 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10865.051906 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10865.051906 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7982984 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7983049 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 57 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8039497 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8039521 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # 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Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 811.917616 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.928313 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003521 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005140 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.049556 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.986529 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1345 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 71 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14277 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 134 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 148 # 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mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 37405.362009 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43402.883601 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 40125.883979 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53710.651253 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53710.651253 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 31385.864378 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31385.864378 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20490.595895 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20490.595895 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 400966.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 400966.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56072.696294 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56072.696294 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33233.793022 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33233.793022 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35933.623236 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35933.623236 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 103366.722006 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 103366.722006 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 37405.362009 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43402.883601 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33233.793022 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 40169.962119 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38184.153016 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 37405.362009 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43402.883601 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33233.793022 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40169.962119 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53710.651253 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42808.499208 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.246709 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36703.309338 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 38935.907750 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 37656.958763 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69416.351262 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 69416.351262 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30104.940787 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30104.940787 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19703.980740 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19703.980740 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 482899.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 482899.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62918.364243 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62918.364243 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34098.951036 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34098.951036 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 36088.202106 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 36088.202106 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 71877.062952 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 71877.062952 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36703.309338 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 38935.907750 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34098.951036 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 41586.766119 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39511.624446 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36703.309338 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 38935.907750 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34098.951036 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 41586.766119 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69416.351262 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49031.784454 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164416.155283 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139300.006883 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161266.772655 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161266.772655 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177171.722663 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149117.743129 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175001.040508 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 175001.040508 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 162803.887098 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 143977.932613 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176098.758535 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 156367.199276 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 22819923 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11703604 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 745 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 1879398 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1879148 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 250 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 571604 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9815849 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 15726 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 15725 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5399709 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 7169213 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2378526 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 893354 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 436778 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 349583 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 518285 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 80 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 141 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1259427 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1201684 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5187720 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4806547 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 796318 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 790789 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15648898 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18825417 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 354875 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 604975 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 35434165 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 664167892 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 709387519 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1351368 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2219552 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1377126331 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6368237 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 18252902 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.116630 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.321021 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 21737448 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11172038 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1012 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 1879362 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1879064 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 298 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 568365 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9266330 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 27872 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 27871 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5482404 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 6640558 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2386717 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 980471 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 448075 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 360841 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 517122 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1223880 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1201425 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4741775 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4748017 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 819035 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 766846 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14311056 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18559366 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 302345 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 623475 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 33796242 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 607086484 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 696970881 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1144232 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2288536 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1307490133 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6577979 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 17957076 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.118626 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.323399 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 16124321 88.34% 88.34% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2128331 11.66% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 250 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 15827205 88.14% 88.14% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2129573 11.86% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 298 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 18252902 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 22598952997 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 17957076 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 21527019496 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 218107077 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 184192978 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7824705000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7155786000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8347252415 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8237151691 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 185954998 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 159316000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 327531000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 337408998 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1400,69 +1403,71 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 91986 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 91986 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 7535 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 69987 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 5 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 91981 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.271795 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 82.431072 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-2047 91980 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 91981 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 77527 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23020.089775 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21173.462910 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 18225.313395 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 76677 98.90% 98.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 165 0.21% 99.12% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 586 0.76% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 21 0.03% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 33 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 9 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 21 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 77527 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -5562525576 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.783829 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.411632 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1202455220 21.62% 21.62% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -4360070356 78.38% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -5562525576 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 69988 90.28% 90.28% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 7535 9.72% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 77523 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 91986 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 108188 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 108188 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9416 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 83328 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 4 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 108184 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.073948 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 24.322514 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-511 108183 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 108184 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 92748 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 25260.781904 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21819.891311 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 28424.827210 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 90515 97.59% 97.59% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 165 0.18% 97.77% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1735 1.87% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 64 0.07% 99.71% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 109 0.12% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 46 0.05% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 73 0.08% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 21 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 8 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 92748 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -800290088 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean -1.452962 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1963081332 245.30% 245.30% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 1162791244 -145.30% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -800290088 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 83329 89.85% 89.85% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 9416 10.15% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 92745 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 108188 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 91986 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 77523 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 108188 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92745 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 77523 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 169509 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92745 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 200933 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 75524944 # DTB read hits -system.cpu1.dtb.read_misses 67300 # DTB read misses -system.cpu1.dtb.write_hits 69031204 # DTB write hits -system.cpu1.dtb.write_misses 24686 # DTB write misses +system.cpu1.dtb.read_hits 84911532 # DTB read hits +system.cpu1.dtb.read_misses 79075 # DTB read misses +system.cpu1.dtb.write_hits 77663318 # DTB write hits +system.cpu1.dtb.write_misses 29113 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 39919 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 34037 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 39584 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4586 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 5277 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9261 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 75592244 # DTB read accesses -system.cpu1.dtb.write_accesses 69055890 # DTB write accesses +system.cpu1.dtb.perms_faults 10813 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 84990607 # DTB read accesses +system.cpu1.dtb.write_accesses 77692431 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 144556148 # DTB hits -system.cpu1.dtb.misses 91986 # DTB misses -system.cpu1.dtb.accesses 144648134 # DTB accesses +system.cpu1.dtb.hits 162574850 # DTB hits +system.cpu1.dtb.misses 108188 # DTB misses +system.cpu1.dtb.accesses 162683038 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1492,237 +1497,239 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 54155 # Table walker walks requested -system.cpu1.itb.walker.walksLong 54155 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 390 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 48650 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 54155 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 54155 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 54155 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 49040 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 26306.504894 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23642.829205 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 24027.787857 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 48185 98.26% 98.26% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 51 0.10% 98.36% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 689 1.40% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 22 0.04% 99.81% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 39 0.08% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 16 0.03% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 29 0.06% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 63937 # Table walker walks requested +system.cpu1.itb.walker.walksLong 63937 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 631 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57861 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 63937 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 63937 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 63937 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 58492 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 30403.747521 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24852.510144 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 37514.660324 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 55985 95.71% 95.71% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 47 0.08% 95.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 2099 3.59% 99.38% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 87 0.15% 99.53% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 102 0.17% 99.71% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 51 0.09% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 79 0.14% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 15 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 17 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 49040 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -2103778220 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -2103778220 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -2103778220 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 48650 99.20% 99.20% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 390 0.80% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 49040 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 58492 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1988115332 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1988115332 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1988115332 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 57861 98.92% 98.92% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 631 1.08% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 58492 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 54155 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 54155 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 63937 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 63937 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49040 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49040 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 103195 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 400011912 # ITB inst hits -system.cpu1.itb.inst_misses 54155 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58492 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58492 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 122429 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 448499634 # ITB inst hits +system.cpu1.itb.inst_misses 63937 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 39919 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 23432 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 27923 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 400066067 # ITB inst accesses -system.cpu1.itb.hits 400011912 # DTB hits -system.cpu1.itb.misses 54155 # DTB misses -system.cpu1.itb.accesses 400066067 # DTB accesses -system.cpu1.numCycles 95204836507 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 448563571 # ITB inst accesses +system.cpu1.itb.hits 448499634 # DTB hits +system.cpu1.itb.misses 63937 # DTB misses +system.cpu1.itb.accesses 448563571 # DTB accesses +system.cpu1.numCycles 95159838343 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 14080 # number of quiesce instructions executed -system.cpu1.committedInsts 399717589 # Number of instructions committed -system.cpu1.committedOps 471481802 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 433690793 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 447669 # Number of float alu accesses -system.cpu1.num_func_calls 24290810 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 60559296 # number of instructions that are conditional controls -system.cpu1.num_int_insts 433690793 # number of integer instructions -system.cpu1.num_fp_insts 447669 # number of float instructions -system.cpu1.num_int_register_reads 628918503 # number of times the integer registers were read -system.cpu1.num_int_register_writes 343906147 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 709471 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 405960 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 102969972 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 102767338 # number of times the CC registers were written -system.cpu1.num_mem_refs 144547138 # number of memory refs -system.cpu1.num_load_insts 75521772 # Number of load instructions -system.cpu1.num_store_insts 69025366 # Number of store instructions -system.cpu1.num_idle_cycles 94207572529.552017 # Number of idle cycles -system.cpu1.num_busy_cycles 997263977.447979 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010475 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989525 # Percentage of idle cycles -system.cpu1.Branches 89155171 # Number of branches fetched +system.cpu1.kern.inst.quiesce 5923 # number of quiesce instructions executed +system.cpu1.committedInsts 448210596 # Number of instructions committed +system.cpu1.committedOps 528777754 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 486415785 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 519922 # Number of float alu accesses +system.cpu1.num_func_calls 27136019 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 67942031 # number of instructions that are conditional controls +system.cpu1.num_int_insts 486415785 # number of integer instructions +system.cpu1.num_fp_insts 519922 # number of float instructions +system.cpu1.num_int_register_reads 706615491 # number of times the integer registers were read +system.cpu1.num_int_register_writes 385601488 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 832776 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 452540 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 115428294 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 115157338 # number of times the CC registers were written +system.cpu1.num_mem_refs 162566757 # number of memory refs +system.cpu1.num_load_insts 84909557 # Number of load instructions +system.cpu1.num_store_insts 77657200 # Number of store instructions +system.cpu1.num_idle_cycles 94045434394.442017 # Number of idle cycles +system.cpu1.num_busy_cycles 1114403948.557976 # Number of busy cycles +system.cpu1.not_idle_fraction 0.011711 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.988289 # Percentage of idle cycles +system.cpu1.Branches 99989008 # Number of branches fetched system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 326125112 69.13% 69.13% # Class of executed instruction -system.cpu1.op_class::IntMult 978063 0.21% 69.33% # Class of executed instruction -system.cpu1.op_class::IntDiv 57214 0.01% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 68664 0.01% 69.36% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.36% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.36% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.36% # Class of executed instruction -system.cpu1.op_class::MemRead 75521772 16.01% 85.37% # Class of executed instruction -system.cpu1.op_class::MemWrite 69025366 14.63% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 365279701 69.04% 69.04% # Class of executed instruction +system.cpu1.op_class::IntMult 1087060 0.21% 69.25% # Class of executed instruction +system.cpu1.op_class::IntDiv 61840 0.01% 69.26% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.26% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 71500 0.01% 69.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.27% # Class of executed instruction +system.cpu1.op_class::MemRead 84909557 16.05% 85.32% # Class of executed instruction +system.cpu1.op_class::MemWrite 77657200 14.68% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 471776234 # Class of executed instruction -system.cpu1.dcache.tags.replacements 4623789 # number of replacements -system.cpu1.dcache.tags.tagsinuse 430.899907 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 139725575 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4624300 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 30.215508 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8408408114000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.899907 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.841601 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.841601 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 420 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 293714645 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 293714645 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 70428619 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 70428619 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 65452147 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 65452147 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 175356 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 175356 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 181976 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 181976 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1569435 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1569435 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1531483 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1531483 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 135880766 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 135880766 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 136056122 # number of overall hits -system.cpu1.dcache.overall_hits::total 136056122 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2625513 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2625513 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1190956 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1190956 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 551150 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 551150 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 454381 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 454381 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 150766 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 150766 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187526 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 187526 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 3816469 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 3816469 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 4367619 # number of overall misses -system.cpu1.dcache.overall_misses::total 4367619 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 39306904500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 39306904500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 28030249500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 28030249500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20535959500 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 20535959500 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2343079000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2343079000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5222807000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5222807000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5948500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5948500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 67337154000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 67337154000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 67337154000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 67337154000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 73054132 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 73054132 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 66643103 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 66643103 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 726506 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 726506 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 636357 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 636357 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1720201 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1720201 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1719009 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1719009 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 139697235 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 139697235 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 140423741 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 140423741 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035939 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035939 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017871 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.017871 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.758631 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.758631 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.714035 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.714035 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.087644 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.087644 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.109090 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.109090 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027320 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.027320 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031103 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.031103 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14971.133070 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14971.133070 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23535.923661 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 23535.923661 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45195.462618 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45195.462618 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15541.163127 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15541.163127 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27851.108646 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27851.108646 # average StoreCondReq miss latency +system.cpu1.op_class::total 529066901 # Class of executed instruction +system.cpu1.dcache.tags.replacements 5332630 # number of replacements +system.cpu1.dcache.tags.tagsinuse 455.913081 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 157043226 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5333142 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.446661 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8395596843000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.913081 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890455 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.890455 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 330516943 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 330516943 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 79081838 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 79081838 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 73714078 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 73714078 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 184325 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 184325 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 141992 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 141992 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1768915 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1768915 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1742986 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1742986 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 152795916 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 152795916 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 152980241 # number of overall hits +system.cpu1.dcache.overall_hits::total 152980241 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3051137 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3051137 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1365469 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1365469 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 638330 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 638330 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 475836 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 475836 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 176856 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 176856 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 201345 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 201345 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4416606 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4416606 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5054936 # number of overall misses +system.cpu1.dcache.overall_misses::total 5054936 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 51930161500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 51930161500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 32223402000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 32223402000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 17094390000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 17094390000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3024227500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3024227500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5760420500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5760420500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4429500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4429500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 84153563500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 84153563500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 84153563500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 84153563500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 82132975 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 82132975 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 75079547 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 75079547 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 822655 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 822655 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 617828 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 617828 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1945771 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1945771 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1944331 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1944331 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 157212522 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 157212522 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 158035177 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 158035177 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037149 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.037149 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018187 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018187 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.775939 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.775939 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.770176 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.770176 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.090893 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.090893 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103555 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103555 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028093 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.028093 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031986 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.031986 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17019.937649 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 17019.937649 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23598.779613 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 23598.779613 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 35924.961541 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 35924.961541 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17099.942891 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17099.942891 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28609.702252 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28609.702252 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17643.836227 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17643.836227 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15417.359893 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15417.359893 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19053.898740 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19053.898740 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16647.799992 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16647.799992 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1731,157 +1738,157 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 4623789 # number of writebacks -system.cpu1.dcache.writebacks::total 4623789 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 13826 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 13826 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 458 # 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number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 551150 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 454381 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 454381 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 107288 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 107288 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187526 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 187526 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 3802185 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 3802185 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4353335 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4353335 # 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number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5883500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62384329000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 62384329000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 74895480000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 74895480000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4378993500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4378993500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 4297960500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 4297960500 # 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mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062369 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.062369 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.109090 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.109090 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027217 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027217 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031001 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031001 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13622.829037 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13622.829037 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22516.428839 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22516.428839 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22700.083462 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22700.083462 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44195.462618 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44195.462618 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13915.610320 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13915.610320 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26851.455265 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26851.455265 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5332630 # number of writebacks +system.cpu1.dcache.writebacks::total 5332630 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 22206 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 22206 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 454 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 454 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 46550 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46550 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 22660 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 22660 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 22660 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 22660 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3028931 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3028931 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1365015 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1365015 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 638330 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 638330 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 475836 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 475836 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 130306 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 130306 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 201345 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 201345 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4393946 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4393946 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5032276 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5032276 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 10149 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 10149 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 10618 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 10618 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 20767 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 20767 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 46920862500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 46920862500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 30832329000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 30832329000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15929044000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15929044000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 16618554000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 16618554000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1916877000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1916877000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5559123500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5559123500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4381500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4381500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 77753191500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 77753191500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 93682235500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 93682235500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1652437500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1652437500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1820826500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1820826500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3473264000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3473264000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036878 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036878 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018181 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018181 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.775939 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.775939 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.770176 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.770176 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066969 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066969 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103555 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103555 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027949 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027949 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031843 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031843 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15490.898439 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15490.898439 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22587.538598 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22587.538598 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24954.246236 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24954.246236 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 34924.961541 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 34924.961541 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14710.581247 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14710.581247 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27609.940649 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27609.940649 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16407.494375 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16407.494375 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17204.161867 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17204.161867 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181527.732869 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 181527.732869 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 184556.874785 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184556.874785 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 183015.629284 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 183015.629284 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17695.527323 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17695.527323 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18616.275320 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18616.275320 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162817.765297 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162817.765297 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171484.884159 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171484.884159 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 167249.193432 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 167249.193432 # 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Cycle average of tags in use +system.cpu1.icache.tags.total_refs 443130586 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5369047 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 82.534309 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8395565369000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.099630 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968945 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.968945 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 291 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 112 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 804847209 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 804847209 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 395188527 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 395188527 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 395188527 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 395188527 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 395188527 # number of overall hits -system.cpu1.icache.overall_hits::total 395188527 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4823385 # 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number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 400011912 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 400011912 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 400011912 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 400011912 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 400011912 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.012058 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.012058 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.012058 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.012058 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.012058 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.012058 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10828.261999 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10828.261999 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10828.261999 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10828.261999 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10828.261999 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10828.261999 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 902368316 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 902368316 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 443130586 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 443130586 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 443130586 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 443130586 # 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number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 58701560000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 58701560000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 448499634 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 448499634 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 448499634 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 448499634 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 448499634 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 448499634 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011971 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.011971 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011971 # 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average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10328.261999 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10328.261999 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10328.261999 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133231.818182 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133231.818182 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133231.818182 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133231.818182 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 56017036000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 56017036000 # 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mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011971 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.011971 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011971 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.011971 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10433.327473 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10433.327473 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10433.327473 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10433.327473 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10433.327473 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10433.327473 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134213.636364 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134213.636364 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6259356 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6259387 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 27 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7379094 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7379143 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 42 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 793397 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 1777622 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13086.026545 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 13889107 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 1793675 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 7.743380 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10216605092500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 11949.147964 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 18.692431 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 11.350132 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1106.836018 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.729318 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001141 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000693 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.067556 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.798708 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1073 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 90 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14890 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 279 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 606 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 184 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 80 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 993 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4499 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8129 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1192 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.065491 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005493 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.908813 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 320280578 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 320280578 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 210783 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 138334 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 349117 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 2929003 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 2929003 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 6516555 # 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number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 138334 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4404363 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3201933 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 7955413 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 210783 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 138334 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4404363 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3201933 # number of overall hits -system.cpu1.l2cache.overall_hits::total 7955413 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9658 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8230 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 17888 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 199042 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 199042 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 187508 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 187508 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 18 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 18 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 241510 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 241510 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 419022 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 419022 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 820381 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 820381 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 261023 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 261023 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9658 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8230 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 419022 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1061891 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1498801 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9658 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8230 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 419022 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1061891 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1498801 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 365970000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 332045500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 698015500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3049287500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 3049287500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1869580500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1869580500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 5786000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 5786000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12702911999 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 12702911999 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 16109032000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 16109032000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 28713782500 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 28713782500 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 18098463500 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 18098463500 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 365970000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 332045500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16109032000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 41416694499 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 58223741999 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 365970000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 332045500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16109032000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 41416694499 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 58223741999 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 220441 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 146564 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 367005 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 2929003 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 2929003 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 6516555 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 6516555 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 199251 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 199251 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 187508 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 187508 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 18 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 18 # 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miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998951 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998951 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.prefetcher.pfSpanPage 880313 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2062305 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13347.402456 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 15756881 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2078287 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 7.581667 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 10111476094500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 12484.773775 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 51.991468 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 59.953770 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 750.683443 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.762010 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003173 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003659 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.045818 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.814661 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1312 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 49 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14621 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 23 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 231 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 561 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 497 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 20 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 989 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4575 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5108 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3891 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080078 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002991 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.892395 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 362674413 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 362674413 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 250614 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 164455 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 415069 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 3362211 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 3362211 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 7338042 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 7338042 # 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mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.577314 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.577314 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.043812 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.056153 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.086873 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.248029 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.158074 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.043812 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.056153 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.086873 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.248029 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.222290 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.222290 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.087248 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.243922 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.243922 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.545288 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.545288 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.044490 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.058050 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.238862 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.155561 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.044490 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.058050 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.238862 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.221168 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31892.938497 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34345.747266 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33021.438953 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45228.472646 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45228.472646 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31448.558621 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31448.558621 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19347.062525 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19347.062525 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 299777.777778 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 299777.777778 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45478.321421 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45478.321421 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32444.358530 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32444.358530 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28974.177244 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28974.177244 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 63336.932661 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 63336.932661 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31892.938497 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34345.747266 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32444.358530 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32683.006303 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32620.144319 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31892.938497 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34345.747266 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32444.358530 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32683.006303 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45228.472646 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36217.034917 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125731.818182 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173505.119595 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 173288.263938 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177032.033665 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 177032.033665 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125731.818182 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 175237.518719 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 175122.924602 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.224069 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 55403.890650 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 63174.543661 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 59015.868648 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53443.738662 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 53443.738662 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32420.177903 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32420.177903 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20104.409004 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20104.409004 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 574428.428571 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 574428.428571 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 49441.389291 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 49441.389291 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33509.163433 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33509.163433 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 37517.049925 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 37517.049925 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 49915.483741 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 49915.483741 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 55403.890650 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 63174.543661 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33509.163433 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 40112.725623 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 38511.337017 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55403.890650 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 63174.543661 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33509.163433 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 40112.725623 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53443.738662 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 43076.877448 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154769.189083 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 154468.369237 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163932.755698 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163932.755698 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 159454.446959 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 159281.937060 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 19593534 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10054336 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1096 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1611494 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1611307 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_requests 22159802 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11360195 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 912 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1833001 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1832814 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 187 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 454071 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 8632529 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 23288 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 23288 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 3935373 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6517651 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2069350 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 732453 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 387389 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 344195 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 449127 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 94 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 141 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1061448 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1001075 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4823385 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4143057 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 462376 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 452130 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14469858 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15078885 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 308515 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 488328 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 30345586 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 617360632 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 574871104 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1172512 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1763528 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1195167776 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5321649 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 15507476 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.118236 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.322925 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 515851 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9779420 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 10618 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 10618 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4509550 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 7338954 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2389159 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 893791 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 389403 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 363316 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 479303 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1190307 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1167875 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5369048 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4688099 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 521676 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 473618 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16106851 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17229570 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 365629 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 576836 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 34278886 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 687205752 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 665341501 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1396720 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2098264 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1356042237 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5987251 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 17478652 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.119213 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.324072 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 13674115 88.18% 88.18% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 1833174 11.82% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 15395152 88.08% 88.08% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2083313 11.92% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 187 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 15507476 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 19383363503 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 17478652 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 21924818496 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 170060906 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 193282156 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7235187500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8053682000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 6851260042 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7892863413 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 161951000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 191039000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 267887000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 314553499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40445 # Transaction distribution -system.iobus.trans_dist::ReadResp 40445 # Transaction distribution -system.iobus.trans_dist::WriteReq 136989 # Transaction distribution -system.iobus.trans_dist::WriteResp 136989 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47854 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40370 # Transaction distribution +system.iobus.trans_dist::ReadResp 40370 # Transaction distribution +system.iobus.trans_dist::WriteReq 136628 # Transaction distribution +system.iobus.trans_dist::WriteResp 136628 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2375,15 +2381,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122996 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231792 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231792 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122664 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231252 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231252 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354868 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47874 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353996 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2394,19 +2400,19 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156011 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355520 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7355520 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155794 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339024 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339024 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7513617 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 37057000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496904 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 37005501 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 320500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 324001 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -2414,7 +2420,7 @@ system.iobus.reqLayer4.occupancy 8000 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) @@ -2422,75 +2428,75 @@ system.iobus.reqLayer15.occupancy 8500 # La system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 26714502 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 26468500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 37418500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 37415000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 568759261 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 567277400 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92994000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92767000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148232000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147948000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115885 # number of replacements -system.iocache.tags.tagsinuse 11.295009 # Cycle average of tags in use +system.iocache.tags.replacements 115622 # number of replacements +system.iocache.tags.tagsinuse 11.298154 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115901 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115638 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9206049239000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.821414 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.473594 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.238838 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.467100 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705938 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9192209246000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.385038 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.913116 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.461565 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.244570 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706135 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1043421 # Number of tag accesses -system.iocache.tags.data_accesses 1043421 # Number of data accesses +system.iocache.tags.tag_accesses 1040991 # Number of tag accesses +system.iocache.tags.data_accesses 1040991 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8912 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8949 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8898 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8935 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8912 # number of demand (read+write) misses -system.iocache.demand_misses::total 8952 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8898 # number of demand (read+write) misses +system.iocache.demand_misses::total 8938 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8912 # number of overall misses -system.iocache.overall_misses::total 8952 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5263500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1680350485 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1685613985 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8898 # number of overall misses +system.iocache.overall_misses::total 8938 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1672896003 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1678095503 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13574924276 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13574924276 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5632500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1680350485 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1685982985 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5632500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1680350485 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1685982985 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13552714897 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13552714897 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1672896003 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1678464503 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1672896003 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1678464503 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8912 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8949 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8898 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8935 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8912 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8952 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8898 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8938 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8912 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8952 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8898 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8938 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2504,55 +2510,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142256.756757 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 188549.201638 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 188357.803665 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 188008.092043 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 187811.472076 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126887.424998 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126887.424998 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 140812.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 188549.201638 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 188335.900916 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 140812.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 188549.201638 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 188335.900916 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33982 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126983.686540 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126983.686540 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 188008.092043 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 187789.718393 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 188008.092043 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 187789.718393 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33965 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3504 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3500 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.698059 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.704286 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106958 # number of writebacks -system.iocache.writebacks::total 106958 # number of writebacks +system.iocache.writebacks::writebacks 106694 # number of writebacks +system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8912 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8949 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8898 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8935 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8912 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8952 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8898 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8938 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8912 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8952 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3413500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1234750485 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1238163985 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8898 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8938 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1227996003 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1231345503 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8219197460 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8219197460 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3632500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1234750485 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1238382985 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3632500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1234750485 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1238382985 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8209903918 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8209903918 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1227996003 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1231564503 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1227996003 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1231564503 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2566,614 +2572,645 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92256.756757 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138549.201638 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 138357.803665 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138008.092043 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 137811.472076 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76826.417595 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76826.417595 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90812.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 138549.201638 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 138335.900916 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90812.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 138549.201638 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 138335.900916 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76923.618151 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76923.618151 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 138008.092043 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 137789.718393 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 138008.092043 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 137789.718393 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1212335 # number of replacements -system.l2c.tags.tagsinuse 62688.740428 # Cycle average of tags in use -system.l2c.tags.total_refs 5318857 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1271612 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.182767 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 22897.710256 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 262.803618 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 467.362186 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4684.066084 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 11639.690690 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16421.765271 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.113156 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 2.385766 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2988.095077 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1979.468778 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1337.279546 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.349391 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004010 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.007131 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.071473 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.177608 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.250576 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000124 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000036 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.045595 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.030204 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.020405 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.956554 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10727 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 233 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 48317 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 79 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 232 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 1534 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 8882 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 227 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1867 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 10232 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 35894 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.163681 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003555 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.737259 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 68046834 # Number of tag accesses -system.l2c.tags.data_accesses 68046834 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 2553793 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2553793 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 170923 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 116715 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 287638 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 41425 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 35212 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 76637 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 168896 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 169545 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 338441 # 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number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 442976 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 748777 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 303485 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5587 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4895 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 380461 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 650830 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 259287 # number of demand (read+write) hits -system.l2c.demand_hits::total 2806073 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5417 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4358 # number of overall hits -system.l2c.overall_hits::cpu0.inst 442976 # number of overall hits -system.l2c.overall_hits::cpu0.data 748777 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3006.389178 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5620.523219 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9896.072880 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 161.524171 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 257.856403 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3567.908148 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 7366.209685 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9779.597138 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.355538 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001836 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003030 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.045874 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.085762 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.151002 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002465 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003935 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.054442 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.112399 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.149225 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.965507 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10707 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 245 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 48305 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 130 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 740 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 9837 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 245 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1549 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5150 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 41466 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.163376 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003738 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.737076 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 74056413 # Number of tag accesses +system.l2c.tags.data_accesses 74056413 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 2788899 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2788899 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 164206 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 131282 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 295488 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 38310 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 41053 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 79363 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 46553 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 57229 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 103782 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5034 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.516511 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.379744 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.439790 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.100056 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.251550 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.410394 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.279701 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70645.608157 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70822.845472 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70734.817393 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73734.473584 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73731.803576 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73733.082159 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 127628.243439 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124096.831143 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 126163.836968 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 132190.734135 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131878.695349 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 125750.999182 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129476.889559 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162820.374673 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130763.060082 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130968.771730 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125690.280371 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131038.589718 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157398.925958 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 146856.147423 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 68924.750887 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69320.540881 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69003.914396 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132190.734135 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131878.695349 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125750.999182 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 128777.448103 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162820.374673 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130763.060082 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130968.771730 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125690.280371 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 128945.611264 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157398.925958 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 143922.799278 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132190.734135 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131878.695349 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125750.999182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 128777.448103 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162820.374673 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130763.060082 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130968.771730 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125690.280371 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 128945.611264 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157398.925958 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 143922.799278 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 146409.886006 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107722.727273 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 155515.816633 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131303.061689 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144246.646804 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 160019.263397 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153661.782662 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159169.005787 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136788.857298 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131789.337281 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157986.725916 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146905.077510 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154929.620177 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 145302.455709 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107722.727273 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 157727.976102 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 138490.550103 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 158584.607059 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 141961.697472 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 139187.653919 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 82348 # Transaction distribution -system.membus.trans_dist::ReadResp 741199 # Transaction distribution -system.membus.trans_dist::WriteReq 39013 # Transaction distribution -system.membus.trans_dist::WriteResp 39013 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1081398 # Transaction distribution -system.membus.trans_dist::CleanEvict 196468 # Transaction distribution -system.membus.trans_dist::UpgradeReq 401198 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 306316 # Transaction distribution -system.membus.trans_dist::UpgradeResp 16 # Transaction distribution -system.membus.trans_dist::ReadExReq 643986 # Transaction distribution -system.membus.trans_dist::ReadExResp 621414 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 658851 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106984 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122996 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 81896 # Transaction distribution +system.membus.trans_dist::ReadResp 974121 # Transaction distribution +system.membus.trans_dist::WriteReq 38489 # Transaction distribution +system.membus.trans_dist::WriteResp 38489 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1317239 # Transaction distribution +system.membus.trans_dist::CleanEvict 246913 # Transaction distribution +system.membus.trans_dist::UpgradeReq 405326 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 320030 # Transaction distribution +system.membus.trans_dist::UpgradeResp 23 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 159351 # Transaction distribution +system.membus.trans_dist::ReadExResp 141190 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 892225 # Transaction distribution +system.membus.trans_dist::InvalidateReq 691970 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122664 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 28036 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4525576 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4676700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238552 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238552 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4915252 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156011 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26416 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4917130 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5066302 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237968 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237968 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5304270 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155794 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 56072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143876076 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 144088363 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7276096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7276096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 151364459 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 576558 # Total snoops (count) -system.membus.snoop_fanout::samples 3516604 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143189356 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 143398186 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7255936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7255936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 150654122 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 585601 # Total snoops (count) +system.membus.snoop_fanout::samples 4153558 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3516604 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4153558 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3516604 # Request fanout histogram -system.membus.reqLayer0.occupancy 101595998 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4153558 # Request fanout histogram +system.membus.reqLayer0.occupancy 101297998 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 23093498 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21722999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7460114319 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9168141817 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6921315949 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5620018463 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45614101 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45534588 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3227,52 +3264,53 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 10579543 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5766836 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1724769 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 116961 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 105875 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 11086 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 82350 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3947474 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 39013 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 39013 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3635231 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2252852 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 680846 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 382953 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1063799 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 141 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 141 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1092357 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1092357 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3872368 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 106984 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8825237 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6597118 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15422355 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 252378371 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 173059496 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 425437867 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2867232 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 7585274 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.353752 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.481180 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 11339751 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6165572 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1768705 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 157796 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 143620 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 14176 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 81898 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4275837 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38489 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38489 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 4106250 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2453030 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 692369 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 399393 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1091762 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 86 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 305771 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 305771 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4201160 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 934668 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 827940 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9127029 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7489964 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 16616993 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 227401989 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 187094309 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 414496298 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3137723 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8291271 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.336829 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.476230 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4913057 64.77% 64.77% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2661131 35.08% 99.85% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 11086 0.15% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5512705 66.49% 66.49% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2764390 33.34% 99.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 14176 0.17% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7585274 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8312830316 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8291271 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8991327701 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2630923 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2644911 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4557123754 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4134292430 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3526163360 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3690529810 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index f5f82f47e..3c1e4fda0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.811400 # Number of seconds simulated -sim_ticks 51811399994500 # Number of ticks simulated -final_tick 51811399994500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.759374 # Number of seconds simulated +sim_ticks 51759374264500 # Number of ticks simulated +final_tick 51759374264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 805770 # Simulator instruction rate (inst/s) -host_op_rate 946938 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50389185573 # Simulator tick rate (ticks/s) -host_mem_usage 678984 # Number of bytes of host memory used -host_seconds 1028.22 # Real time elapsed on the host -sim_insts 828512987 # Number of instructions simulated -sim_ops 973664549 # Number of ops (including micro ops) simulated +host_inst_rate 1125548 # Simulator instruction rate (inst/s) +host_op_rate 1322684 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69608471837 # Simulator tick rate (ticks/s) +host_mem_usage 675480 # Number of bytes of host memory used +host_seconds 743.58 # Real time elapsed on the host +sim_insts 836933434 # Number of instructions simulated +sim_ops 983519389 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 133568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 141952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 4623732 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 65034376 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 398080 # Number of bytes read from this memory -system.physmem.bytes_read::total 70331708 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 4623732 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4623732 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 61230400 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 155264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 159360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 4743732 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 36334600 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 399488 # Number of bytes read from this memory +system.physmem.bytes_read::total 41792444 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 4743732 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 4743732 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 63133056 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 61250980 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 2087 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2218 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 112653 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1016175 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6220 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1139353 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 956725 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 63153636 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 2426 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2490 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 114528 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 567741 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6242 # Number of read requests responded to by this memory +system.physmem.num_reads::total 693427 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 986454 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 959298 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2578 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 2740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 89242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1255214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7683 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1357456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 89242 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89242 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1181794 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1182191 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1181794 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 2740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 89242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1255611 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7683 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2539647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1139353 # Number of read requests accepted -system.physmem.writeReqs 959298 # Number of write requests accepted -system.physmem.readBursts 1139353 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 959298 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 72868032 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 50560 # Total number of bytes read from write queue -system.physmem.bytesWritten 61249856 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 70331708 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 61250980 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 790 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.num_writes::total 989027 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 3000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 3079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 91650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 701991 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 807437 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 91650 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 91650 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1219741 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1220139 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1219741 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 3000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 3079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 91650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 702388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2027576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 693427 # Number of read requests accepted +system.physmem.writeReqs 989027 # Number of write requests accepted +system.physmem.readBursts 693427 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 989027 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 44328448 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 50880 # Total number of bytes read from write queue +system.physmem.bytesWritten 63152448 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 41792444 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 63153636 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 795 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 69574 # Per bank write bursts -system.physmem.perBankRdBursts::1 73483 # Per bank write bursts -system.physmem.perBankRdBursts::2 70905 # Per bank write bursts -system.physmem.perBankRdBursts::3 67568 # Per bank write bursts -system.physmem.perBankRdBursts::4 64326 # Per bank write bursts -system.physmem.perBankRdBursts::5 70688 # Per bank write bursts -system.physmem.perBankRdBursts::6 65575 # Per bank write bursts -system.physmem.perBankRdBursts::7 64409 # Per bank write bursts -system.physmem.perBankRdBursts::8 65562 # Per bank write bursts -system.physmem.perBankRdBursts::9 110058 # Per bank write bursts -system.physmem.perBankRdBursts::10 69387 # Per bank write bursts -system.physmem.perBankRdBursts::11 70852 # Per bank write bursts -system.physmem.perBankRdBursts::12 67727 # Per bank write bursts -system.physmem.perBankRdBursts::13 71395 # Per bank write bursts -system.physmem.perBankRdBursts::14 70177 # Per bank write bursts -system.physmem.perBankRdBursts::15 66877 # Per bank write bursts -system.physmem.perBankWrBursts::0 57914 # Per bank write bursts -system.physmem.perBankWrBursts::1 61200 # Per bank write bursts -system.physmem.perBankWrBursts::2 60974 # Per bank write bursts -system.physmem.perBankWrBursts::3 59703 # Per bank write bursts -system.physmem.perBankWrBursts::4 56782 # Per bank write bursts -system.physmem.perBankWrBursts::5 61096 # Per bank write bursts -system.physmem.perBankWrBursts::6 57709 # Per bank write bursts -system.physmem.perBankWrBursts::7 57516 # Per bank write bursts -system.physmem.perBankWrBursts::8 58389 # Per bank write bursts -system.physmem.perBankWrBursts::9 61168 # Per bank write bursts -system.physmem.perBankWrBursts::10 60736 # Per bank write bursts -system.physmem.perBankWrBursts::11 62143 # Per bank write bursts -system.physmem.perBankWrBursts::12 59319 # Per bank write bursts -system.physmem.perBankWrBursts::13 62705 # Per bank write bursts -system.physmem.perBankWrBursts::14 61087 # Per bank write bursts -system.physmem.perBankWrBursts::15 58588 # Per bank write bursts +system.physmem.perBankRdBursts::0 40853 # Per bank write bursts +system.physmem.perBankRdBursts::1 42497 # Per bank write bursts +system.physmem.perBankRdBursts::2 39380 # Per bank write bursts +system.physmem.perBankRdBursts::3 40815 # Per bank write bursts +system.physmem.perBankRdBursts::4 36874 # Per bank write bursts +system.physmem.perBankRdBursts::5 45606 # Per bank write bursts +system.physmem.perBankRdBursts::6 38207 # Per bank write bursts +system.physmem.perBankRdBursts::7 36804 # Per bank write bursts +system.physmem.perBankRdBursts::8 38817 # Per bank write bursts +system.physmem.perBankRdBursts::9 83381 # Per bank write bursts +system.physmem.perBankRdBursts::10 47849 # Per bank write bursts +system.physmem.perBankRdBursts::11 45678 # Per bank write bursts +system.physmem.perBankRdBursts::12 39735 # Per bank write bursts +system.physmem.perBankRdBursts::13 40223 # Per bank write bursts +system.physmem.perBankRdBursts::14 37028 # Per bank write bursts +system.physmem.perBankRdBursts::15 38885 # Per bank write bursts +system.physmem.perBankWrBursts::0 61132 # Per bank write bursts +system.physmem.perBankWrBursts::1 62574 # Per bank write bursts +system.physmem.perBankWrBursts::2 60681 # Per bank write bursts +system.physmem.perBankWrBursts::3 62576 # Per bank write bursts +system.physmem.perBankWrBursts::4 57559 # Per bank write bursts +system.physmem.perBankWrBursts::5 64093 # Per bank write bursts +system.physmem.perBankWrBursts::6 59756 # Per bank write bursts +system.physmem.perBankWrBursts::7 59796 # Per bank write bursts +system.physmem.perBankWrBursts::8 61252 # Per bank write bursts +system.physmem.perBankWrBursts::9 63246 # Per bank write bursts +system.physmem.perBankWrBursts::10 66784 # Per bank write bursts +system.physmem.perBankWrBursts::11 64593 # Per bank write bursts +system.physmem.perBankWrBursts::12 60371 # Per bank write bursts +system.physmem.perBankWrBursts::13 61779 # Per bank write bursts +system.physmem.perBankWrBursts::14 59591 # Per bank write bursts +system.physmem.perBankWrBursts::15 60974 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 61 # Number of times write queue was full causing retry -system.physmem.totGap 51811397057500 # Total gap between requests +system.physmem.numWrRetry 25 # Number of times write queue was full causing retry +system.physmem.totGap 51759371327500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1096237 # Read request sizes (log2) +system.physmem.readPktSize::6 650311 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 956725 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1111594 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 330 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 485 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 535 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 665 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 290 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 111 # What read queue length does an incoming req see +system.physmem.writePktSize::6 986454 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 663933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 23086 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 539 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 655 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 269 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 163 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 108 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 66 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -159,166 +159,165 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 13396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 55236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 57047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 55563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 55847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 56596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 57293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 56619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 58037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 60289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 57688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 57977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 60291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 57181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 56145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 56000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 160 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 450226 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 297.889433 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 171.979745 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.177331 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 179632 39.90% 39.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 110318 24.50% 64.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 39188 8.70% 73.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22734 5.05% 78.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15887 3.53% 81.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11846 2.63% 84.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9963 2.21% 86.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8722 1.94% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 51936 11.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 450226 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 53627 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.230425 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 337.691151 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 53625 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 53627 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 53627 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.846029 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.135395 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.325860 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 51578 96.18% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 290 0.54% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 64 0.12% 96.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 105 0.20% 97.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 36 0.07% 97.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 101 0.19% 97.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 231 0.43% 97.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 25 0.05% 97.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 324 0.60% 98.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 70 0.13% 98.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 27 0.05% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 55 0.10% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 281 0.52% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 24 0.04% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 27 0.05% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 150 0.28% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 183 0.34% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::15 32057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 37802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 54666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 57679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 55454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 58825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 55973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 56654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 56029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 57159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 59457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 57206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 57286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 59007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 55988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 54822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 54598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 61 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 441826 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 243.264489 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.730249 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 285.608942 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 196692 44.52% 44.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 117501 26.59% 71.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 39119 8.85% 79.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20402 4.62% 84.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13280 3.01% 87.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8813 1.99% 89.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7349 1.66% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5826 1.32% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 32844 7.43% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 441826 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 52334 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 13.234628 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 140.708770 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 52332 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 52334 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 52334 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.854989 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.140951 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.267205 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 48626 92.91% 92.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1874 3.58% 96.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 113 0.22% 96.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 103 0.20% 96.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 52 0.10% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 95 0.18% 97.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 242 0.46% 97.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 26 0.05% 97.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 308 0.59% 98.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 80 0.15% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 37 0.07% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 50 0.10% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 303 0.58% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 32 0.06% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 32 0.06% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 137 0.26% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 171 0.33% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 16 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 17 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 10 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 53627 # Writes before turning the bus around for reads -system.physmem.totQLat 14356871098 # Total ticks spent queuing -system.physmem.totMemAccLat 35704927348 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5692815000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12609.64 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 52334 # Writes before turning the bus around for reads +system.physmem.totQLat 9243736951 # Total ticks spent queuing +system.physmem.totMemAccLat 22230586951 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3463160000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13345.81 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31359.64 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.18 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.36 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.18 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 32095.81 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.86 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.22 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.81 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.22 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.12 # Average write queue length when enqueuing -system.physmem.readRowHits 917761 # Number of row buffer hits during reads -system.physmem.writeRowHits 727604 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.03 # Row buffer hit rate for writes -system.physmem.avgGap 24687952.91 # Average gap between requests -system.physmem.pageHitRate 78.51 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1698338880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 926673000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4262879400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3064353120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3384068597520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1294076187855 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29951683866750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34639780896525 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.574535 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49826749097915 # Time in different power states -system.physmem_0.memoryStateTime::REF 1730096420000 # Time in different power states +system.physmem.avgWrQLen 26.31 # Average write queue length when enqueuing +system.physmem.readRowHits 510166 # Number of row buffer hits during reads +system.physmem.writeRowHits 727396 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.71 # Row buffer hit rate for writes +system.physmem.avgGap 30764211.88 # Average gap between requests +system.physmem.pageHitRate 73.69 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1653765120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 902352000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2504080800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3163322160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3380670399600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1281472530255 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29931523073250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34601889523185 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.514508 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49793449587940 # Time in different power states +system.physmem_0.memoryStateTime::REF 1728359100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 254553819585 # Time in different power states +system.physmem_0.memoryStateTime::ACT 237560965810 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1705369680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 930509250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4617873000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3137194800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3384068597520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1296366805530 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29949674553000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34640500902780 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.588432 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49823352477739 # Time in different power states -system.physmem_1.memoryStateTime::REF 1730096420000 # Time in different power states +system.physmem_1.actEnergy 1686439440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 920180250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2898409800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3230863200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3380670399600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1285016955840 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29928413928000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34602837176130 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.532817 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49788231100713 # Time in different power states +system.physmem_1.memoryStateTime::REF 1728359100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 257948478511 # Time in different power states +system.physmem_1.memoryStateTime::ACT 242783406787 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -372,70 +371,71 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 185086 # Table walker walks requested -system.cpu.dtb.walker.walksLong 185086 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12788 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 144037 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 15 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 185071 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 0.216133 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 70.811526 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-2047 185069 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 187211 # Table walker walks requested +system.cpu.dtb.walker.walksLong 187211 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12337 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 146092 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 187194 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.213682 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 70.408839 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 187192 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 185071 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 156840 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 24753.656593 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 20840.255945 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 17740.873102 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 155696 99.27% 99.27% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 5 0.00% 99.27% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 981 0.63% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 24 0.02% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 68 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 23 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 36 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 156840 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -374556148 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 5.053125 # Table walker pending requests distribution +system.cpu.dtb.walker.walkWaitTime::total 187194 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 158446 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 24872.701110 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 20850.948689 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 18486.762457 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 157188 99.21% 99.21% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 99.21% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 1079 0.68% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 28 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 66 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 21 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 47 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 158446 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -5153633892 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 1.304072 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 1518122704 -405.31% -405.31% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::1 -1892678852 505.31% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -374556148 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 144038 91.85% 91.85% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 12788 8.15% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 156826 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 185086 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walksPending::0 1567075704 -30.41% -30.41% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 -6720709596 130.41% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -5153633892 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 146093 92.21% 92.21% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 12337 7.79% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 158430 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 187211 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 185086 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 156826 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 187211 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 158430 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 156826 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 341912 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 158430 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 345641 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 156026006 # DTB read hits -system.cpu.dtb.read_misses 137641 # DTB read misses -system.cpu.dtb.write_hits 141600690 # DTB write hits -system.cpu.dtb.write_misses 47445 # DTB write misses +system.cpu.dtb.read_hits 157500215 # DTB read hits +system.cpu.dtb.read_misses 138721 # DTB read misses +system.cpu.dtb.write_hits 142992331 # DTB write hits +system.cpu.dtb.write_misses 48490 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 37806 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 70612 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 71001 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 6537 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 6932 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 18565 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 156163647 # DTB read accesses -system.cpu.dtb.write_accesses 141648135 # DTB write accesses +system.cpu.dtb.perms_faults 18784 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 157638936 # DTB read accesses +system.cpu.dtb.write_accesses 143040821 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 297626696 # DTB hits -system.cpu.dtb.misses 185086 # DTB misses -system.cpu.dtb.accesses 297811782 # DTB accesses +system.cpu.dtb.hits 300492546 # DTB hits +system.cpu.dtb.misses 187211 # DTB misses +system.cpu.dtb.accesses 300679757 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -465,232 +465,234 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 118473 # Table walker walks requested -system.cpu.itb.walker.walksLong 118473 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1110 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 107045 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 118473 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 118473 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 118473 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 108155 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28668.184550 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24838.617630 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 20892.143337 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 106773 98.72% 98.72% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 1223 1.13% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 21 0.02% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 63 0.06% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 24 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 37 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 9 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 108155 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 119486 # Table walker walks requested +system.cpu.itb.walker.walksLong 119486 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 107916 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 119486 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 119486 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 119486 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 109038 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28670.651516 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24724.680347 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 21871.977834 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 107545 98.63% 98.63% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 4 0.00% 98.63% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 1290 1.18% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 34 0.03% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 71 0.07% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 41 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 42 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 109038 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 1449611704 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 1449611704 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 1449611704 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 107045 98.97% 98.97% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1110 1.03% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 108155 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 107916 98.97% 98.97% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1122 1.03% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 109038 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 118473 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 118473 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 119486 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 119486 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 108155 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 108155 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 226628 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 829023400 # ITB inst hits -system.cpu.itb.inst_misses 118473 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 109038 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 109038 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 228524 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 837449249 # ITB inst hits +system.cpu.itb.inst_misses 119486 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 37806 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 50418 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 50677 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 829141873 # ITB inst accesses -system.cpu.itb.hits 829023400 # DTB hits -system.cpu.itb.misses 118473 # DTB misses -system.cpu.itb.accesses 829141873 # DTB accesses -system.cpu.numCycles 103622799989 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 837568735 # ITB inst accesses +system.cpu.itb.hits 837449249 # DTB hits +system.cpu.itb.misses 119486 # DTB misses +system.cpu.itb.accesses 837568735 # DTB accesses +system.cpu.numCycles 103518748529 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 15972 # number of quiesce instructions executed -system.cpu.committedInsts 828512987 # Number of instructions committed -system.cpu.committedOps 973664549 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 895161313 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 899443 # Number of float alu accesses -system.cpu.num_func_calls 49782138 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 125600972 # number of instructions that are conditional controls -system.cpu.num_int_insts 895161313 # number of integer instructions -system.cpu.num_fp_insts 899443 # number of float instructions -system.cpu.num_int_register_reads 1295047006 # number of times the integer registers were read -system.cpu.num_int_register_writes 709396185 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1452745 # number of times the floating registers were read -system.cpu.num_fp_register_writes 757712 # number of times the floating registers were written -system.cpu.num_cc_register_reads 214441530 # number of times the CC registers were read -system.cpu.num_cc_register_writes 213833710 # number of times the CC registers were written -system.cpu.num_mem_refs 297604519 # number of memory refs -system.cpu.num_load_insts 156015499 # Number of load instructions -system.cpu.num_store_insts 141589020 # Number of store instructions -system.cpu.num_idle_cycles 100541051528.316055 # Number of idle cycles -system.cpu.num_busy_cycles 3081748460.683940 # Number of busy cycles -system.cpu.not_idle_fraction 0.029740 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.970260 # Percentage of idle cycles -system.cpu.Branches 184855625 # Number of branches fetched +system.cpu.kern.inst.quiesce 16028 # number of quiesce instructions executed +system.cpu.committedInsts 836933434 # Number of instructions committed +system.cpu.committedOps 983519389 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 904020212 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 901230 # Number of float alu accesses +system.cpu.num_func_calls 50188688 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 127012937 # number of instructions that are conditional controls +system.cpu.num_int_insts 904020212 # number of integer instructions +system.cpu.num_fp_insts 901230 # number of float instructions +system.cpu.num_int_register_reads 1309570840 # number of times the integer registers were read +system.cpu.num_int_register_writes 716549182 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1454726 # number of times the floating registers were read +system.cpu.num_fp_register_writes 760848 # number of times the floating registers were written +system.cpu.num_cc_register_reads 217149735 # number of times the CC registers were read +system.cpu.num_cc_register_writes 216544825 # number of times the CC registers were written +system.cpu.num_mem_refs 300471292 # number of memory refs +system.cpu.num_load_insts 157490392 # Number of load instructions +system.cpu.num_store_insts 142980900 # Number of store instructions +system.cpu.num_idle_cycles 100455078038.626068 # Number of idle cycles +system.cpu.num_busy_cycles 3063670490.373941 # Number of busy cycles +system.cpu.not_idle_fraction 0.029595 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.970405 # Percentage of idle cycles +system.cpu.Branches 186768786 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 674284702 69.21% 69.21% # Class of executed instruction -system.cpu.op_class::IntMult 2119126 0.22% 69.43% # Class of executed instruction -system.cpu.op_class::IntDiv 97314 0.01% 69.44% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 8 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 13 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 21 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 112382 0.01% 69.45% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu.op_class::MemRead 156015499 16.01% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 141589020 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 681265861 69.23% 69.23% # Class of executed instruction +system.cpu.op_class::IntMult 2131844 0.22% 69.45% # Class of executed instruction +system.cpu.op_class::IntDiv 96991 0.01% 69.46% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 8 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 13 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 21 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 112297 0.01% 69.47% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu.op_class::MemRead 157490392 16.00% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 142980900 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 974218086 # Class of executed instruction -system.cpu.dcache.tags.replacements 9250712 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.942785 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 288177954 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9251224 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 31.150251 # Average number of references to valid blocks. +system.cpu.op_class::total 984078328 # Class of executed instruction +system.cpu.dcache.tags.replacements 9381962 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.942718 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 290912714 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9382474 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 31.005971 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 5830299500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.942785 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.942718 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1199424100 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1199424100 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 146113650 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146113650 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 134461846 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 134461846 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 373199 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 373199 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 333438 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 333438 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3286002 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3286002 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3568410 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3568410 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 280575496 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 280575496 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 280948695 # number of overall hits -system.cpu.dcache.overall_hits::total 280948695 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4827178 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4827178 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1968166 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1968166 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1108268 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1108268 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1219027 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1219027 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 284027 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 284027 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 6795344 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6795344 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7903612 # number of overall misses -system.cpu.dcache.overall_misses::total 7903612 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 82868566500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 82868566500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 66733586000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 66733586000 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 73334603500 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 73334603500 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4341861000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4341861000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 149602152500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 149602152500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 149602152500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 149602152500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 150940828 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 150940828 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 136430012 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 136430012 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1481467 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1481467 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1552465 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1552465 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3570029 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3570029 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3568412 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3568412 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 287370840 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 287370840 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 288852307 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 288852307 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031981 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.031981 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014426 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.014426 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.748088 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.748088 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785220 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.785220 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079559 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079559 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023647 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023647 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.027362 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.027362 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17167.083232 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17167.083232 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33906.482482 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33906.482482 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 60158.309455 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 60158.309455 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15286.789636 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15286.789636 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22015.390612 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22015.390612 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18928.327010 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18928.327010 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 1211017846 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1211017846 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 147435449 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 147435449 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 135766146 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 135766146 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 374114 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 374114 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 332621 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 332621 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3338150 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3338150 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3623891 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3623891 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 283201595 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 283201595 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 283575709 # number of overall hits +system.cpu.dcache.overall_hits::total 283575709 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4894991 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4894991 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1998130 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1998130 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1136451 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1136451 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1221510 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1221510 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 287378 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 287378 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 6893121 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6893121 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8029572 # number of overall misses +system.cpu.dcache.overall_misses::total 8029572 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 84471929500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 84471929500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 70206054500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 70206054500 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 48228758000 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 48228758000 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4418678000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4418678000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 154677984000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 154677984000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 154677984000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 154677984000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 152330440 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 152330440 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 137764276 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 137764276 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1510565 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1510565 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1554131 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1554131 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3625528 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3625528 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3623892 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3623892 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 290094716 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 290094716 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 291605281 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 291605281 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032134 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032134 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014504 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.014504 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.752335 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.752335 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785976 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.785976 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079265 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079265 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023762 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023762 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.027536 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.027536 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17256.809972 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17256.809972 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35135.879297 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35135.879297 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 39482.900672 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 39482.900672 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15375.839487 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15375.839487 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22439.470307 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22439.470307 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19263.540323 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19263.540323 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -699,154 +701,154 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7246265 # number of writebacks -system.cpu.dcache.writebacks::total 7246265 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 23319 # 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number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6217623500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12417276500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 12417276500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031826 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031826 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014270 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014270 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.746887 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.746887 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785220 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785220 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060619 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060619 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023491 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.023491 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027201 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027201 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15964.950470 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15964.950470 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32772.321750 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32772.321750 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18964.116647 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18964.116647 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 59158.309455 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 59158.309455 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13728.343491 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13728.343491 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20812.092609 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20812.092609 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20551.852406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20551.852406 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183955.047178 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.047178 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184455.426012 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184455.426012 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184205.258864 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184205.258864 # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 78281972500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 78281972500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67251605000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 67251605000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21441642000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21441642000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 47007248000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 47007248000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3007041000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3007041000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145533577500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 145533577500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 166975219500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 166975219500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199681500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199681500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6217603000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6217603000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12417284500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 12417284500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031990 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031990 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014350 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014350 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751167 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751167 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785976 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785976 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060344 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060344 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023613 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.023613 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027381 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027381 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16064.398082 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16064.398082 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34019.131701 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34019.131701 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18896.542303 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18896.542303 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 38482.900672 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 38482.900672 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13744.713819 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13744.713819 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21246.131322 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21246.131322 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20912.231676 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20912.231676 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183955.892825 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.892825 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184454.817847 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184454.817847 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184205.377540 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184205.377540 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13387387 # number of replacements -system.cpu.icache.tags.tagsinuse 511.782420 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 815635496 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13387899 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 60.923338 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 61704805500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.782420 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999575 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999575 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 13331164 # number of replacements +system.cpu.icache.tags.tagsinuse 511.820795 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 824117568 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13331676 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 61.816501 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 49363844500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.820795 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999650 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999650 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 188 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 842411304 # Number of tag accesses -system.cpu.icache.tags.data_accesses 842411304 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 815635496 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 815635496 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 815635496 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 815635496 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 815635496 # number of overall hits -system.cpu.icache.overall_hits::total 815635496 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13387904 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13387904 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13387904 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13387904 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13387904 # number of overall misses -system.cpu.icache.overall_misses::total 13387904 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 182784455500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 182784455500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 182784455500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 182784455500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 182784455500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 182784455500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 829023400 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 829023400 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 829023400 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 829023400 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 829023400 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 829023400 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13652.955347 # average overall miss latency +system.cpu.icache.tags.tag_accesses 850780930 # Number of tag accesses +system.cpu.icache.tags.data_accesses 850780930 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 824117568 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 824117568 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 824117568 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 824117568 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 824117568 # number of overall hits +system.cpu.icache.overall_hits::total 824117568 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13331681 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13331681 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13331681 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13331681 # 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number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 837449249 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 837449249 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 837449249 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015919 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015919 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015919 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015919 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015919 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015919 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13673.648694 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13673.648694 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13673.648694 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13673.648694 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13673.648694 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13673.648694 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -855,231 +857,230 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 13387387 # number of writebacks -system.cpu.icache.writebacks::total 13387387 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13387904 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 13387904 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 13387904 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 13387904 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 13387904 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 13387904 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 13331164 # number of writebacks +system.cpu.icache.writebacks::total 13331164 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13331681 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 13331681 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 13331681 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 169396551500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 169396551500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168961041500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 168961041500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168961041500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 168961041500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168961041500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 168961041500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 5436787000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 5436787000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 5436787000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 5436787000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016149 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016149 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016149 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016149 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016149 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016149 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12652.955347 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12652.955347 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12652.955347 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12652.955347 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12652.955347 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12652.955347 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015919 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015919 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015919 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.015919 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015919 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.015919 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12673.648694 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12673.648694 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12673.648694 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12673.648694 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12673.648694 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12673.648694 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 18455.629136 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.575829 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.003210 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.004790 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.129542 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.281611 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994982 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 253 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 61992 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 252 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 400 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2440 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5510 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53605 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003860 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945923 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 371220882 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 371220882 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 309149 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 242072 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 551221 # 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number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006706 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.009079 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.007749 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.786413 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.786413 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607551500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 16505276000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008763 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.786099 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.786099 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.166206 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.166206 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005196 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005196 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036011 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036011 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.393790 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.393790 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006706 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009079 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005196 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.066897 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.027813 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006706 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009079 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005196 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.066897 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.027813 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125901.054145 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126519.612263 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126219.744483 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67946.365507 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67946.365507 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121102.587946 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121102.587946 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122363.271760 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122363.271760 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123109.369405 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123109.369405 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 120254.867813 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 120254.867813 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125901.054145 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126519.612263 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122363.271760 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 121926.589148 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 122006.529756 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125901.054145 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126519.612263 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122363.271760 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 121926.589148 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122006.529756 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.176574 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.176574 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005359 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036511 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036511 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.394346 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.394346 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.069712 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.029260 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.069712 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.029260 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127907.648495 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67931.831155 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67931.831155 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121217.409569 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121217.409569 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122484.427492 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122484.427492 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123381.721390 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123381.721390 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 67656.435152 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 67656.435152 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122484.427492 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 122082.245632 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 122171.152080 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122484.427492 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 122082.245632 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122171.152080 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171431.205863 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.438596 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172955.099680 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172955.099680 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171432.007003 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.790035 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172954.491515 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172954.491515 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172193.220590 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149321.658298 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172193.317015 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149321.717103 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 45794965 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 23155820 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1753 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2699 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2699 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 45953712 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 23239521 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1757 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2704 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2704 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 972147 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 20487667 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 981994 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 20540984 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8203050 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13387387 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2163174 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 41410 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 41412 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1905461 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1905461 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 13387904 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6135636 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1325691 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1219027 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40249445 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27971705 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 598323 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 852523 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 69671996 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1713791124 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 978068334 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1954320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2489888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2696303666 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1571708 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 24917471 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.019294 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.137557 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 8300157 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13331164 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2233602 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 42345 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 42346 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1934534 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1934534 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 13331681 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6235371 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1328174 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1221510 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40080776 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28367342 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 601942 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 864211 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 69914271 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1706594580 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 990623790 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1959056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2528832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2701706258 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1612380 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 25039605 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.019510 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.138308 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 24436707 98.07% 98.07% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 480764 1.93% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 24551092 98.05% 98.05% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 488513 1.95% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 24917471 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 43812763500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 25039605 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 43904381000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1591387 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1555895 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20124981000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20040646500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 12729124462 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 12924004979 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 354033000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 357060000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 541287000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 548107000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40324 # Transaction distribution -system.iobus.trans_dist::ReadResp 40324 # Transaction distribution +system.iobus.trans_dist::ReadReq 40345 # Transaction distribution +system.iobus.trans_dist::ReadResp 40345 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1289,11 +1290,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231006 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231006 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231048 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231048 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353790 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353832 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1308,20 +1309,20 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334456 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334456 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334624 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492376 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42148500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492544 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42150500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1331,77 +1332,77 @@ system.iobus.reqLayer14.occupancy 11000 # La system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25712000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25723500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38603000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38603500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 566837671 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 566919864 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147766000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147808000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115484 # number of replacements -system.iocache.tags.tagsinuse 10.446945 # Cycle average of tags in use +system.iocache.tags.replacements 115506 # number of replacements +system.iocache.tags.tagsinuse 10.446851 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115522 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13183709781000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.511462 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.935482 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219466 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433468 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.652934 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13171623640000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.511150 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.935701 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219447 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433481 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652928 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039884 # Number of tag accesses -system.iocache.tags.data_accesses 1039884 # Number of data accesses +system.iocache.tags.tag_accesses 1040073 # Number of tag accesses +system.iocache.tags.data_accesses 1040073 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8860 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8897 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8839 # number of demand (read+write) misses -system.iocache.demand_misses::total 8879 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8860 # number of demand (read+write) misses +system.iocache.demand_misses::total 8900 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8839 # number of overall misses -system.iocache.overall_misses::total 8879 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1648554138 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1653624638 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8860 # number of overall misses +system.iocache.overall_misses::total 8900 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1628892126 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1633962126 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13411902033 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13411902033 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1648554138 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1653975638 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1648554138 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1653975638 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13410994738 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13410994738 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1628892126 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1634313126 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1628892126 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1634313126 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8860 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8897 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8839 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8860 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8900 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8839 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8879 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8860 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8900 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1415,55 +1416,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 186509.122978 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 186302.910996 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 183847.869752 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 183653.155670 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125739.725053 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125739.725053 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 186509.122978 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 186279.495213 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 186509.122978 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 186279.495213 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32796 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125731.218949 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125731.218949 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 183847.869752 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183630.688315 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 183847.869752 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183630.688315 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32190 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3360 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3353 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.760714 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.600358 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106630 # number of writebacks -system.iocache.writebacks::total 106630 # number of writebacks +system.iocache.writebacks::writebacks 106631 # number of writebacks +system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8860 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8897 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8839 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8879 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8860 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8900 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1206604138 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1209824638 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8860 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8900 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1185892126 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1189112126 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073565122 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8073565122 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1206604138 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1210025638 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1206604138 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1210025638 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8072604881 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8072604881 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1185892126 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1189313126 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1185892126 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1189313126 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1477,72 +1478,72 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136509.122978 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 136302.910996 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133847.869752 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 133653.155670 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.565308 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.565308 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 136509.122978 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 136279.495213 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 136509.122978 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 136279.495213 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75682.562823 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75682.562823 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 133847.869752 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 133630.688315 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 133847.869752 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 133630.688315 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 76827 # Transaction distribution -system.membus.trans_dist::ReadResp 380206 # Transaction distribution +system.membus.trans_dist::ReadResp 389416 # Transaction distribution system.membus.trans_dist::WriteReq 33708 # Transaction distribution system.membus.trans_dist::WriteResp 33708 # Transaction distribution -system.membus.trans_dist::WritebackDirty 956725 # Transaction distribution -system.membus.trans_dist::CleanEvict 157718 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33138 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 796168 # Transaction distribution -system.membus.trans_dist::ReadExResp 796168 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 303379 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution +system.membus.trans_dist::WritebackDirty 986454 # Transaction distribution +system.membus.trans_dist::CleanEvict 164302 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33853 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7 # Transaction distribution +system.membus.trans_dist::ReadExReq 341030 # Transaction distribution +system.membus.trans_dist::ReadExResp 341030 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 312589 # Transaction distribution +system.membus.trans_dist::InvalidateReq 588355 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3304162 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3433854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237247 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237247 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3671101 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2930961 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3060653 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237312 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237312 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3297965 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 124360288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 124530114 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7222400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7222400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 131752514 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3318 # Total snoops (count) -system.membus.snoop_fanout::samples 2464390 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 97722208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 97892034 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7223872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7223872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 105115906 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3315 # Total snoops (count) +system.membus.snoop_fanout::samples 2537144 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2464390 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2537144 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2464390 # Request fanout histogram -system.membus.reqLayer0.occupancy 106890000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2537144 # Request fanout histogram +system.membus.reqLayer0.occupancy 106903500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5800500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5766500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 6292280855 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 6541365638 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5974901047 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3628181019 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44724954 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44825406 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index e3f33ed21..16266538d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111167 # Nu sim_ticks 51111167216500 # Number of ticks simulated final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1097269 # Simulator instruction rate (inst/s) -host_op_rate 1289528 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57098875481 # Simulator tick rate (ticks/s) -host_mem_usage 677960 # Number of bytes of host memory used -host_seconds 895.13 # Real time elapsed on the host +host_inst_rate 1764627 # Simulator instruction rate (inst/s) +host_op_rate 2073818 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 91826344419 # Simulator tick rate (ticks/s) +host_mem_usage 678044 # Number of bytes of host memory used +host_seconds 556.61 # Real time elapsed on the host sim_insts 982203438 # Number of instructions simulated sim_ops 1154301153 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -16,13 +16,13 @@ system.clk_domain.clock 1000 # Cl system.physmem.bytes_read::cpu0.dtb.walker 206336 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 188160 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 3278004 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 64990856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 38030280 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 207616 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 185216 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 2205952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 45263168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 36881856 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory -system.physmem.bytes_read::total 116962108 # Number of bytes read from this memory +system.physmem.bytes_read::total 81620220 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 3278004 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 2205952 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 5483956 # Number of instructions bytes read from this memory @@ -32,26 +32,26 @@ system.physmem.bytes_written::total 103298148 # Nu system.physmem.num_reads::cpu0.dtb.walker 3224 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2940 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 91626 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1015495 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 594236 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 3244 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 2894 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 34468 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 707237 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 576279 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1867953 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1315736 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1613712 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::total 1616285 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 4037 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 3681 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 64135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1271559 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 744070 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 4062 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 3624 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 43160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 885583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 721601 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2288387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1596916 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 64135 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 43160 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 107295 # Instruction read bandwidth from this memory (bytes/s) @@ -62,13 +62,13 @@ system.physmem.bw_total::writebacks 2020646 # To system.physmem.bw_total::cpu0.dtb.walker 4037 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 3681 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 64135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1271961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 744473 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 4062 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 3624 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 43160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 885583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 721601 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4309435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3617964 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -1007,11 +1007,11 @@ system.membus.trans_dist::CleanEvict 226309 # Tr system.membus.trans_dist::UpgradeReq 40494 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 40495 # Transaction distribution -system.membus.trans_dist::ReadExReq 1379260 # Transaction distribution -system.membus.trans_dist::ReadExResp 1379260 # Transaction distribution +system.membus.trans_dist::ReadExReq 827043 # Transaction distribution +system.membus.trans_dist::ReadExResp 827043 # Transaction distribution system.membus.trans_dist::ReadSharedReq 448255 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution +system.membus.trans_dist::InvalidateReq 658881 # Transaction distribution +system.membus.trans_dist::InvalidateResp 658881 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) @@ -1023,11 +1023,11 @@ system.membus.pkt_count::total 6009939 # Pa system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 213040864 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 213209914 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 177698976 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 177868026 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 220600698 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 185258810 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 3924980 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt index b9cfad15e..90977c91b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -1,193 +1,193 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.278396 # Number of seconds simulated -sim_ticks 51278396244000 # Number of ticks simulated -final_tick 51278396244000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.278323 # Number of seconds simulated +sim_ticks 51278322908000 # Number of ticks simulated +final_tick 51278322908000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 287420 # Simulator instruction rate (inst/s) -host_op_rate 337741 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17381457033 # Simulator tick rate (ticks/s) -host_mem_usage 688188 # Number of bytes of host memory used -host_seconds 2950.18 # Real time elapsed on the host -sim_insts 847940135 # Number of instructions simulated -sim_ops 996397451 # Number of ops (including micro ops) simulated +host_inst_rate 391318 # Simulator instruction rate (inst/s) +host_op_rate 459835 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23610419083 # Simulator tick rate (ticks/s) +host_mem_usage 689044 # Number of bytes of host memory used +host_seconds 2171.85 # Real time elapsed on the host +sim_insts 849885052 # Number of instructions simulated +sim_ops 998692344 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 80128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 85632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2427380 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 43615880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 26944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 22528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 448704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 6225152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 27008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 28160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 1496000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 7976640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 59008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.itb.walker 56384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 1720000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 14392384 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 422080 # Number of bytes read from this memory -system.physmem.bytes_read::total 79110012 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2427380 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 448704 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 1496000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 1720000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6092084 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67404672 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 79744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 81088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2584308 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 18551240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 21056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 18624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 450240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4979392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 31808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 29568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 1509568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 6342336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 66432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.itb.walker 61184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 1749760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 11675328 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 416192 # Number of bytes read from this memory +system.physmem.bytes_read::total 48647868 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2584308 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 450240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 1509568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 1749760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6293876 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 68210816 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 67425252 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1252 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1338 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 78335 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 681511 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 421 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 352 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7011 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 97268 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 422 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 440 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 23375 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 124635 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 922 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.itb.walker 881 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 26875 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 224881 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6595 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1276514 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1053198 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 68231396 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1246 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1267 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 80787 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 289876 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 329 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 291 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7035 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 77803 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 497 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 462 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 23587 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 99099 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 1038 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.itb.walker 956 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 27340 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 182427 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6503 # Number of read requests responded to by this memory +system.physmem.num_reads::total 800543 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1065794 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1055771 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 47337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 850570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 439 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 8750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 121399 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 549 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 29174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 155556 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1151 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.itb.walker 1100 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 33542 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 280671 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8231 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1542755 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 47337 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 8750 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 29174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 33542 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 118804 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1314485 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1068367 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1555 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 50398 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 361775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 411 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 8780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 97105 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 29439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 123685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.itb.walker 1193 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 34123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 227685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8116 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 948702 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 50398 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 8780 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 29439 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 34123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 122740 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1330208 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1314886 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1314485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 47337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 850972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 439 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 8750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 121399 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 549 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 29174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 155556 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1151 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.itb.walker 1100 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 33542 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 280671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8231 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2857641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 511823 # Number of read requests accepted -system.physmem.writeReqs 447580 # Number of write requests accepted -system.physmem.readBursts 511823 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 447580 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 32737280 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19392 # Total number of bytes read from write queue -system.physmem.bytesWritten 28644032 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 32756672 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 28645120 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 303 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1330609 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1330208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 50398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 362177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 8780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 97105 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 29439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 123685 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.itb.walker 1193 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 34123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 227685 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2279311 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 425112 # Number of read requests accepted +system.physmem.writeReqs 454625 # Number of write requests accepted +system.physmem.readBursts 425112 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 454625 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27178752 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 28416 # Total number of bytes read from write queue +system.physmem.bytesWritten 29094208 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27207168 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 29096000 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 444 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 29703 # Per bank write bursts -system.physmem.perBankRdBursts::1 34345 # Per bank write bursts -system.physmem.perBankRdBursts::2 31026 # Per bank write bursts -system.physmem.perBankRdBursts::3 30271 # Per bank write bursts -system.physmem.perBankRdBursts::4 32199 # Per bank write bursts -system.physmem.perBankRdBursts::5 37423 # Per bank write bursts -system.physmem.perBankRdBursts::6 31570 # Per bank write bursts -system.physmem.perBankRdBursts::7 30956 # Per bank write bursts -system.physmem.perBankRdBursts::8 30714 # Per bank write bursts -system.physmem.perBankRdBursts::9 34361 # Per bank write bursts -system.physmem.perBankRdBursts::10 33202 # Per bank write bursts -system.physmem.perBankRdBursts::11 32791 # Per bank write bursts -system.physmem.perBankRdBursts::12 32230 # Per bank write bursts -system.physmem.perBankRdBursts::13 32440 # Per bank write bursts -system.physmem.perBankRdBursts::14 29459 # Per bank write bursts -system.physmem.perBankRdBursts::15 28830 # Per bank write bursts -system.physmem.perBankWrBursts::0 25970 # Per bank write bursts -system.physmem.perBankWrBursts::1 28442 # Per bank write bursts -system.physmem.perBankWrBursts::2 26808 # Per bank write bursts -system.physmem.perBankWrBursts::3 27272 # Per bank write bursts -system.physmem.perBankWrBursts::4 29035 # Per bank write bursts -system.physmem.perBankWrBursts::5 31977 # Per bank write bursts -system.physmem.perBankWrBursts::6 28169 # Per bank write bursts -system.physmem.perBankWrBursts::7 28603 # Per bank write bursts -system.physmem.perBankWrBursts::8 27151 # Per bank write bursts -system.physmem.perBankWrBursts::9 29537 # Per bank write bursts -system.physmem.perBankWrBursts::10 28051 # Per bank write bursts -system.physmem.perBankWrBursts::11 28561 # Per bank write bursts -system.physmem.perBankWrBursts::12 27796 # Per bank write bursts -system.physmem.perBankWrBursts::13 28123 # Per bank write bursts -system.physmem.perBankWrBursts::14 26050 # Per bank write bursts -system.physmem.perBankWrBursts::15 26018 # Per bank write bursts +system.physmem.perBankRdBursts::0 27658 # Per bank write bursts +system.physmem.perBankRdBursts::1 29828 # Per bank write bursts +system.physmem.perBankRdBursts::2 28706 # Per bank write bursts +system.physmem.perBankRdBursts::3 26688 # Per bank write bursts +system.physmem.perBankRdBursts::4 26134 # Per bank write bursts +system.physmem.perBankRdBursts::5 30288 # Per bank write bursts +system.physmem.perBankRdBursts::6 24980 # Per bank write bursts +system.physmem.perBankRdBursts::7 26114 # Per bank write bursts +system.physmem.perBankRdBursts::8 23639 # Per bank write bursts +system.physmem.perBankRdBursts::9 28679 # Per bank write bursts +system.physmem.perBankRdBursts::10 26865 # Per bank write bursts +system.physmem.perBankRdBursts::11 27723 # Per bank write bursts +system.physmem.perBankRdBursts::12 26411 # Per bank write bursts +system.physmem.perBankRdBursts::13 25648 # Per bank write bursts +system.physmem.perBankRdBursts::14 22535 # Per bank write bursts +system.physmem.perBankRdBursts::15 22772 # Per bank write bursts +system.physmem.perBankWrBursts::0 28961 # Per bank write bursts +system.physmem.perBankWrBursts::1 29340 # Per bank write bursts +system.physmem.perBankWrBursts::2 30073 # Per bank write bursts +system.physmem.perBankWrBursts::3 30333 # Per bank write bursts +system.physmem.perBankWrBursts::4 28091 # Per bank write bursts +system.physmem.perBankWrBursts::5 30746 # Per bank write bursts +system.physmem.perBankWrBursts::6 26981 # Per bank write bursts +system.physmem.perBankWrBursts::7 28675 # Per bank write bursts +system.physmem.perBankWrBursts::8 26142 # Per bank write bursts +system.physmem.perBankWrBursts::9 29950 # Per bank write bursts +system.physmem.perBankWrBursts::10 27880 # Per bank write bursts +system.physmem.perBankWrBursts::11 29356 # Per bank write bursts +system.physmem.perBankWrBursts::12 28075 # Per bank write bursts +system.physmem.perBankWrBursts::13 28226 # Per bank write bursts +system.physmem.perBankWrBursts::14 25398 # Per bank write bursts +system.physmem.perBankWrBursts::15 26370 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 29 # Number of times write queue was full causing retry -system.physmem.totGap 51277395805500 # Total gap between requests +system.physmem.numWrRetry 27 # Number of times write queue was full causing retry +system.physmem.totGap 51277322578500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 511823 # Read request sizes (log2) +system.physmem.readPktSize::6 425112 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 447580 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 363555 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 93711 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 31585 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 420 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 356 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 769 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 87 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 66 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 454625 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 320658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 71523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20097 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 348 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 332 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 736 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 78 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 75 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -198,182 +198,195 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 565 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 564 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 8731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 19434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 21637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 24704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 25741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 25599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 25799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 26255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 26532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 27053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 28426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 27490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 27929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 30961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 26710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 26732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 25592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 71 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 257915 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 237.988981 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 144.092695 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 278.727383 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 118797 46.06% 46.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 64316 24.94% 71.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 23486 9.11% 80.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 11936 4.63% 84.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 8805 3.41% 88.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 5543 2.15% 90.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4520 1.75% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3591 1.39% 93.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16921 6.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 257915 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 24705 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.705080 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 14.399508 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-63 24532 99.30% 99.30% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::64-127 158 0.64% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-191 5 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::192-255 5 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-319 1 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-575 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::640-703 2 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1088-1151 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 24705 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 24705 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.116292 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.314740 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.551029 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 22 0.09% 0.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 13 0.05% 0.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 13 0.05% 0.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 49 0.20% 0.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 23047 93.29% 93.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 446 1.81% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 165 0.67% 96.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 178 0.72% 96.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 51 0.21% 97.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 35 0.14% 97.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 69 0.28% 97.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 9 0.04% 97.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 185 0.75% 98.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 38 0.15% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 14 0.06% 98.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 28 0.11% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 125 0.51% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 16 0.06% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 10 0.04% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 68 0.28% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 94 0.38% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 5 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 5 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 10 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 24705 # Writes before turning the bus around for reads -system.physmem.totQLat 10604540202 # Total ticks spent queuing -system.physmem.totMemAccLat 20195540202 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2557600000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20731.43 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::11 560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 10142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 11914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 20808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 22265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 25126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 25463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 25664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 25947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 26600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 26580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 27124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 28654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 27815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 28161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 29398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 26416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 26013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 25235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 63 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 264549 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 212.710628 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 133.311116 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 253.186946 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 128347 48.52% 48.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 68595 25.93% 74.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 23489 8.88% 83.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11716 4.43% 87.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8015 3.03% 90.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4779 1.81% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3761 1.42% 94.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2799 1.06% 95.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 13048 4.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 264549 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 24602 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 17.259532 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 12.570080 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-31 22973 93.38% 93.38% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32-63 1501 6.10% 99.48% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::64-95 103 0.42% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::96-127 9 0.04% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-159 2 0.01% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::160-191 2 0.01% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::192-223 4 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::224-255 3 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-287 1 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::352-383 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::416-447 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::480-511 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::608-639 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 24602 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 24602 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.478051 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.651979 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 9.004636 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 26 0.11% 0.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 15 0.06% 0.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 5 0.02% 0.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 55 0.22% 0.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 22328 90.76% 91.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 965 3.92% 95.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 224 0.91% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 206 0.84% 96.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 77 0.31% 97.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 56 0.23% 97.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 71 0.29% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 24 0.10% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 154 0.63% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 44 0.18% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 15 0.06% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 22 0.09% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 116 0.47% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 24 0.10% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 8 0.03% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 50 0.20% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 75 0.30% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.01% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 11 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::236-239 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 24602 # Writes before turning the bus around for reads +system.physmem.totQLat 8333966979 # Total ticks spent queuing +system.physmem.totMemAccLat 16296491979 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2123340000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19624.66 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39481.43 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.64 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.64 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.56 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38374.66 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.53 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.53 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.57 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.01 # Data bus utilization in percentage system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 6.40 # Average write queue length when enqueuing -system.physmem.readRowHits 390042 # Number of row buffer hits during reads -system.physmem.writeRowHits 311121 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 69.51 # Row buffer hit rate for writes -system.physmem.avgGap 53447191.44 # Average gap between requests -system.physmem.pageHitRate 73.11 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 987139440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 536905875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2008390800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1466203680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3310428600960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1177085104875 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 30106909725750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34599422071380 # Total energy per rank (pJ) -system.physmem_0.averagePower 666.667509 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 48872262134916 # Time in different power states -system.physmem_0.memoryStateTime::REF 1692448160000 # Time in different power states +system.physmem.avgWrQLen 6.41 # Average write queue length when enqueuing +system.physmem.readRowHits 310449 # Number of row buffer hits during reads +system.physmem.writeRowHits 304265 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.10 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.93 # Row buffer hit rate for writes +system.physmem.avgGap 58287104.64 # Average gap between requests +system.physmem.pageHitRate 69.91 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1040339160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 565834500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1719073200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1511136000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3310423515360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1181162631510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 30835777461750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 35332199991480 # Total energy per rank (pJ) +system.physmem_0.averagePower 665.141706 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 48866215203670 # Time in different power states +system.physmem_0.memoryStateTime::REF 1692445560000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 119734785584 # Time in different power states +system.physmem_0.memoryStateTime::ACT 125694518580 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 962629920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 523549125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1981395000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1433900880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3310428600960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1177786265580 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29667035331750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34160151673215 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.621174 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 48871271616428 # Time in different power states -system.physmem_1.memoryStateTime::REF 1692448160000 # Time in different power states +system.physmem_1.actEnergy 959651280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 522080625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1593267000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1434652560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3310423515360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1174137422265 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29654012520750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34143083109840 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.640404 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 48876586216946 # Time in different power states +system.physmem_1.memoryStateTime::REF 1692445560000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 120718837572 # Time in different power states +system.physmem_1.memoryStateTime::ACT 115306042554 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -433,47 +446,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 90127 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 90127 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 90127 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 90127 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 90127 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 389002834492 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.524244 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -203932266508 -52.42% -52.42% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 592935101000 152.42% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 389002834492 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 65772 85.00% 85.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 11604 15.00% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 77376 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 90127 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 90589 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 90589 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 90589 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 90589 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 90589 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 384648913196 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.541506 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -208289583554 -54.15% -54.15% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 592938496750 154.15% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 384648913196 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 66121 84.68% 84.68% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11962 15.32% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 78083 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 90589 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 90127 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 77376 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 90589 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 78083 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 77376 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 167503 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 78083 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 168672 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 64859725 # DTB read hits -system.cpu0.dtb.read_misses 68631 # DTB read misses -system.cpu0.dtb.write_hits 59094124 # DTB write hits -system.cpu0.dtb.write_misses 21496 # DTB write misses +system.cpu0.dtb.read_hits 64905943 # DTB read hits +system.cpu0.dtb.read_misses 68632 # DTB read misses +system.cpu0.dtb.write_hits 59387283 # DTB write hits +system.cpu0.dtb.write_misses 21957 # DTB write misses system.cpu0.dtb.flush_tlb 1195 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 16177 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 384 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 40401 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 16181 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 404 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 41245 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2751 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 2795 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 7419 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 64928356 # DTB read accesses -system.cpu0.dtb.write_accesses 59115620 # DTB write accesses +system.cpu0.dtb.perms_faults 7554 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 64974575 # DTB read accesses +system.cpu0.dtb.write_accesses 59409240 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 123953849 # DTB hits -system.cpu0.dtb.misses 90127 # DTB misses -system.cpu0.dtb.accesses 124043976 # DTB accesses +system.cpu0.dtb.hits 124293226 # DTB hits +system.cpu0.dtb.misses 90589 # DTB misses +system.cpu0.dtb.accesses 124383815 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -503,699 +516,699 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 53226 # Table walker walks requested -system.cpu0.itb.walker.walksLong 53226 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 53226 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 53226 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 53226 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 389002834492 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.524351 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -203974019508 -52.44% -52.44% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 592976854000 152.44% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 389002834492 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 46188 94.90% 94.90% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2484 5.10% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 48672 # Table walker page sizes translated +system.cpu0.itb.walker.walks 53629 # Table walker walks requested +system.cpu0.itb.walker.walksLong 53629 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 53629 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 53629 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 53629 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 384648913196 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.541605 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -208327943554 -54.16% -54.16% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 592976856750 154.16% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 384648913196 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 46675 94.93% 94.93% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2493 5.07% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 49168 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53226 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53226 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53629 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53629 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 48672 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 48672 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 101898 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 346140401 # ITB inst hits -system.cpu0.itb.inst_misses 53226 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 49168 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 49168 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 102797 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 346758065 # ITB inst hits +system.cpu0.itb.inst_misses 53629 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 1195 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 16177 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 384 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 28414 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 16181 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 404 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 28950 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 346193627 # ITB inst accesses -system.cpu0.itb.hits 346140401 # DTB hits -system.cpu0.itb.misses 53226 # DTB misses -system.cpu0.itb.accesses 346193627 # DTB accesses -system.cpu0.numCycles 417471005 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 346811694 # ITB inst accesses +system.cpu0.itb.hits 346758065 # DTB hits +system.cpu0.itb.misses 53629 # DTB misses +system.cpu0.itb.accesses 346811694 # DTB accesses +system.cpu0.numCycles 418356627 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16511 # number of quiesce instructions executed -system.cpu0.committedInsts 345998217 # Number of instructions committed -system.cpu0.committedOps 406905705 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 373867604 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 363074 # Number of float alu accesses -system.cpu0.num_func_calls 20947482 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 52475381 # number of instructions that are conditional controls -system.cpu0.num_int_insts 373867604 # number of integer instructions -system.cpu0.num_fp_insts 363074 # number of float instructions -system.cpu0.num_int_register_reads 545388282 # number of times the integer registers were read -system.cpu0.num_int_register_writes 296679828 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 584270 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 311304 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 89963697 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 89731719 # number of times the CC registers were written -system.cpu0.num_mem_refs 124026394 # number of memory refs -system.cpu0.num_load_insts 64916857 # Number of load instructions -system.cpu0.num_store_insts 59109537 # Number of store instructions -system.cpu0.num_idle_cycles 408121506.428325 # Number of idle cycles -system.cpu0.num_busy_cycles 9349498.571675 # Number of busy cycles -system.cpu0.not_idle_fraction 0.022396 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.977604 # Percentage of idle cycles -system.cpu0.Branches 77230042 # Number of branches fetched +system.cpu0.kern.inst.quiesce 16523 # number of quiesce instructions executed +system.cpu0.committedInsts 346615446 # Number of instructions committed +system.cpu0.committedOps 407794224 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 374692963 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 359996 # Number of float alu accesses +system.cpu0.num_func_calls 21015198 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 52493274 # number of instructions that are conditional controls +system.cpu0.num_int_insts 374692963 # number of integer instructions +system.cpu0.num_fp_insts 359996 # number of float instructions +system.cpu0.num_int_register_reads 546961774 # number of times the integer registers were read +system.cpu0.num_int_register_writes 297330498 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 576159 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 315016 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 89964300 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 89735253 # number of times the CC registers were written +system.cpu0.num_mem_refs 124366560 # number of memory refs +system.cpu0.num_load_insts 64963335 # Number of load instructions +system.cpu0.num_store_insts 59403225 # Number of store instructions +system.cpu0.num_idle_cycles 408478241.491071 # Number of idle cycles +system.cpu0.num_busy_cycles 9878385.508929 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023612 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976388 # Percentage of idle cycles +system.cpu0.Branches 77357953 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 282115014 69.29% 69.29% # Class of executed instruction -system.cpu0.op_class::IntMult 908017 0.22% 69.51% # Class of executed instruction -system.cpu0.op_class::IntDiv 41532 0.01% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 48729 0.01% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::MemRead 64916857 15.94% 85.48% # Class of executed instruction -system.cpu0.op_class::MemWrite 59109537 14.52% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 282690768 69.28% 69.28% # Class of executed instruction +system.cpu0.op_class::IntMult 882754 0.22% 69.50% # Class of executed instruction +system.cpu0.op_class::IntDiv 40502 0.01% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 48552 0.01% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::MemRead 64963335 15.92% 85.44% # Class of executed instruction +system.cpu0.op_class::MemWrite 59403225 14.56% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 407139686 # Class of executed instruction -system.cpu0.dcache.tags.replacements 9649816 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999717 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 292739937 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 9650328 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.334714 # Average number of references to valid blocks. +system.cpu0.op_class::total 408029136 # Class of executed instruction +system.cpu0.dcache.tags.replacements 9683863 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999715 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 293338565 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 9684375 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.289881 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.097568 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.975954 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 4.503732 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 4.422464 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.972847 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.009719 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.008796 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.008638 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.042783 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 6.501939 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.121621 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 4.333371 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968834 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.012699 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.010003 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.008464 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1240452518 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1240452518 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 60697634 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 18777257 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 26142693 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 44948482 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 150566066 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 55906928 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 17271712 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 23345865 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 37782358 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 134306863 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 159073 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 47007 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 77709 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 113008 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 396797 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 126017 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 45823 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu2.data 59716 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu3.data 97286 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 328842 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1444166 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 434424 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 579867 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 933968 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3392425 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1534667 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 472976 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 630117 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1067463 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3705223 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 116604562 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 36048969 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 49488558 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 82730840 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 284872929 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 116763635 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 36095976 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 49566267 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 82843848 # number of overall hits -system.cpu0.dcache.overall_hits::total 285269726 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2054873 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 645438 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 971207 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 3440752 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7112270 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 839053 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 258864 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 597119 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu3.data 3449762 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 5144798 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 459594 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 152322 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 206104 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu3.data 350750 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1168770 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 686647 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 108408 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu2.data 151049 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu3.data 279871 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1225975 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 91254 # 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number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 23041710 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu3.data 37927921 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 134614136 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 159339 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 46933 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 75224 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu3.data 113852 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 395348 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 127860 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 45150 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu2.data 58313 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu3.data 97655 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 328978 # 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number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu3.data 89900424 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 297759988 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 120441036 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 37547313 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 50977026 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu3.data 90365422 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 299330797 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032347 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032842 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.037400 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.071285 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.045231 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014823 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014679 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.025258 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.083585 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.036930 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.744733 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.767784 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.730858 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.755156 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.748316 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.841556 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.706675 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.726727 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.743817 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788503 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060509 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.077945 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.076231 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.160503 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.095081 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000002 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024217 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024472 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.030717 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu3.data 0.076885 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.041252 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027919 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028440 # 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average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 34331.719061 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 34818.174897 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 39573.470845 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 16359.673206 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14200.946877 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14882.189368 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13340.594163 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10202.699483 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 82000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 41000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 22765.541821 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24734.316717 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 25629.357569 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19252.389245 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19483.681045 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21861.370694 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 24387.931049 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17576.395912 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 14582944 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 41803 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 883633 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 391 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.503395 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 106.913043 # average number of cycles each access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024005 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024226 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.031738 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu3.data 0.076948 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.041334 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027740 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028228 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.035571 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu3.data 0.080438 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.045044 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16595.733179 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17134.662892 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17324.907778 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12308.442417 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38106.130933 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 36408.783116 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 35611.288245 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 29996.822269 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24382.445415 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 24950.997588 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 27300.440525 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 11628.340613 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14234.063983 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14874.774232 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13321.581304 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10135.049469 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 48000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 32000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 22778.468113 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24286.633902 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 26469.587595 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19727.062944 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19443.526215 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21550.736546 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 25190.872141 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18007.249075 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 13349622 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 42813 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 888017 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 383 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.033070 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 111.783290 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 7469710 # number of writebacks -system.cpu0.dcache.writebacks::total 7469710 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3285 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 124429 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1909922 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 2037636 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 4905 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 264011 # 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number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1305231500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1342048955 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3950684955 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2666265500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2671367500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 2710568955 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 8048201955 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033062 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031230 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031636 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019151 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014487 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013913 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.014123 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008386 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.762262 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.716912 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.740462 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.446359 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.702894 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.716561 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.736431 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.345497 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064632 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.063514 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.059942 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036560 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # 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average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17146.322257 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16390.897160 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 37114.933907 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35144.915463 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 36557.702052 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36276.276532 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20535.013591 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 19858.995719 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 19726.411276 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19940.829702 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 33331.719061 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 33815.541695 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 38418.062499 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36097.627366 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12955.759736 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13304.665451 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14259.752308 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13689.169844 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21492.495358 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21291.487906 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 22495.535957 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21941.849637 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21353.684880 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21080.791626 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 22108.446764 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21655.774548 # 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number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1186994000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1151196455 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3623469955 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2623209500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2439970500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 2326262455 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7389442455 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032675 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.032416 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031780 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019371 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014402 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014068 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.014160 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008397 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.765899 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.721366 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.739952 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.445942 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.706675 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.726586 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.738093 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.350487 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061205 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.059356 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.061145 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.035727 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024007 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023861 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.023668 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.014220 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028000 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027685 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.027354 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.016485 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15340.500253 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15731.091824 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17105.467384 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16341.630766 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36998.163703 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34908.995501 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 38174.844185 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36993.768673 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20012.342130 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20404.044262 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 19216.739906 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19734.289569 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23382.445415 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 23944.506076 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 25963.030709 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 24874.087915 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13072.723284 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13311.172783 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14210.195133 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13716.690006 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 47000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 47000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21503.808577 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21003.096659 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 22908.405526 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22066.629614 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21284.207818 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20917.516350 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 22394.539528 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21735.536852 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196119.906186 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 193629.500850 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 189679.741727 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193245.715312 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 201929.222310 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 198926.428691 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 193608.552809 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 198242.146570 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 198923.902328 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 196170.646406 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 191603.859237 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 195663.889610 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 15707105 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.971411 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 557754178 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 15707617 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.508517 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 11785355500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 478.312770 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 3.251841 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 23.846438 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 6.560362 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.934205 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.006351 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.046575 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu3.inst 0.012813 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 15734993 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.971408 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 559674194 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 15735505 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 35.567603 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 11770190500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 476.852160 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 4.999201 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 23.919768 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu3.inst 6.200279 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.931352 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.009764 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.046718 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu3.inst 0.012110 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999944 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 589528421 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 589528421 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 340625874 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 105592046 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 63997933 # 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number of overall misses -system.cpu0.icache.overall_misses::cpu3.inst 4969275 # number of overall misses -system.cpu0.icache.overall_misses::total 16066549 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 22564855500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 53176348000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 67096069815 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 142837273315 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 22564855500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 53176348000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu3.inst 67096069815 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 142837273315 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 22564855500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 53176348000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu3.inst 67096069815 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 142837273315 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 346189073 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 107259862 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 67864192 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu3.inst 52507600 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 573820727 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 346189073 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 107259862 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 67864192 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu3.inst 52507600 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 573820727 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 346189073 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 107259862 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 67864192 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu3.inst 52507600 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 573820727 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016070 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015549 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.056971 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.094639 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.027999 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016070 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015549 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.056971 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu3.inst 0.094639 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.027999 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016070 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015549 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.056971 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu3.inst 0.094639 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.027999 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.583299 # 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average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1226,70 +1239,68 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 31889 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 31889 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4559 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 23393 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walks 31825 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 31825 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4653 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 23077 # Level at which table walker walks with long descriptors terminate system.cpu1.dtb.walker.walksSquashedBefore 6 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 31883 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.878211 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 156.811692 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-2047 31882 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 31883 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 27958 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 25168.842550 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21742.406424 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 16076.029843 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 18219 65.17% 65.17% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 9556 34.18% 99.35% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 2 0.01% 99.35% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 143 0.51% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 15 0.05% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 4 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 12 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 1 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 2 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 27958 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1140126012 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 1.890541 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1015329500 -89.05% -89.05% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -2155455512 189.05% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1140126012 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 23393 83.69% 83.69% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 4559 16.31% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 27952 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31889 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::samples 31819 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 1.099972 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 196.211646 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 31818 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 31819 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 27736 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 24896.776752 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21479.770946 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15609.675218 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 27586 99.46% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2 0.01% 99.47% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 129 0.47% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 2 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 11 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 2 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 2 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 27736 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 3125373784 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.674826 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.468440 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1016289500 32.52% 32.52% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 2109084284 67.48% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 3125373784 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 23077 83.22% 83.22% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 4653 16.78% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 27730 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31825 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31889 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27952 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31825 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27730 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27952 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 59841 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27730 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 59555 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 20102110 # DTB read hits -system.cpu1.dtb.read_misses 24529 # DTB read misses -system.cpu1.dtb.write_hits 18166884 # DTB write hits -system.cpu1.dtb.write_misses 7360 # DTB write misses +system.cpu1.dtb.read_hits 20322566 # DTB read hits +system.cpu1.dtb.read_misses 24426 # DTB read misses +system.cpu1.dtb.write_hits 18362474 # DTB write hits +system.cpu1.dtb.write_misses 7399 # DTB write misses system.cpu1.dtb.flush_tlb 1186 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 5389 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 137 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 18327 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 5702 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 134 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 18006 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 952 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 961 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 2685 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 20126639 # DTB read accesses -system.cpu1.dtb.write_accesses 18174244 # DTB write accesses +system.cpu1.dtb.perms_faults 2721 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 20346992 # DTB read accesses +system.cpu1.dtb.write_accesses 18369873 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 38268994 # DTB hits -system.cpu1.dtb.misses 31889 # DTB misses -system.cpu1.dtb.accesses 38300883 # DTB accesses +system.cpu1.dtb.hits 38685040 # DTB hits +system.cpu1.dtb.misses 31825 # DTB misses +system.cpu1.dtb.accesses 38716865 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1319,130 +1330,133 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 20281 # Table walker walks requested -system.cpu1.itb.walker.walksLong 20281 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 944 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17917 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 20281 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 20281 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 20281 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 18861 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 28459.466624 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 25212.666818 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18596.263354 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 18677 99.02% 99.02% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 158 0.84% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 7 0.04% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 10 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 5 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 18861 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 20346 # Table walker walks requested +system.cpu1.itb.walker.walksLong 20346 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 938 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17905 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 20346 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 20346 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 20346 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 18843 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 28149.073927 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24906.041063 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 17543.804263 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 9517 50.51% 50.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 9170 48.67% 99.17% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 113 0.60% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 25 0.13% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 7 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 1 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 2 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 4 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 3 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 18843 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 17917 94.99% 94.99% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 944 5.01% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 18861 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 17905 95.02% 95.02% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 938 4.98% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 18843 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20281 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20281 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20346 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20346 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18861 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18861 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 39142 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 107259862 # ITB inst hits -system.cpu1.itb.inst_misses 20281 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18843 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18843 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 39189 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 108575555 # ITB inst hits +system.cpu1.itb.inst_misses 20346 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 1186 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 5389 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 137 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 13712 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 5702 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 134 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 13443 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 107280143 # ITB inst accesses -system.cpu1.itb.hits 107259862 # DTB hits -system.cpu1.itb.misses 20281 # DTB misses -system.cpu1.itb.accesses 107280143 # DTB accesses -system.cpu1.numCycles 1186091604 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 108595901 # ITB inst accesses +system.cpu1.itb.hits 108575555 # DTB hits +system.cpu1.itb.misses 20346 # DTB misses +system.cpu1.itb.accesses 108595901 # DTB accesses +system.cpu1.numCycles 1186099317 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 107180280 # Number of instructions committed -system.cpu1.committedOps 125798339 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 115609456 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 108829 # Number of float alu accesses -system.cpu1.num_func_calls 6343191 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 16252887 # number of instructions that are conditional controls -system.cpu1.num_int_insts 115609456 # number of integer instructions -system.cpu1.num_fp_insts 108829 # number of float instructions -system.cpu1.num_int_register_reads 167399256 # number of times the integer registers were read -system.cpu1.num_int_register_writes 91770929 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 176307 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 89468 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 27813306 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27752983 # number of times the CC registers were written -system.cpu1.num_mem_refs 38266694 # number of memory refs -system.cpu1.num_load_insts 20101554 # Number of load instructions -system.cpu1.num_store_insts 18165140 # Number of store instructions -system.cpu1.num_idle_cycles 1160685667.067715 # Number of idle cycles -system.cpu1.num_busy_cycles 25405936.932285 # Number of busy cycles -system.cpu1.not_idle_fraction 0.021420 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.978580 # Percentage of idle cycles -system.cpu1.Branches 23816903 # Number of branches fetched +system.cpu1.committedInsts 108493989 # Number of instructions committed +system.cpu1.committedOps 127332484 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 116990571 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 112697 # Number of float alu accesses +system.cpu1.num_func_calls 6392203 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 16488906 # number of instructions that are conditional controls +system.cpu1.num_int_insts 116990571 # number of integer instructions +system.cpu1.num_fp_insts 112697 # number of float instructions +system.cpu1.num_int_register_reads 169322857 # number of times the integer registers were read +system.cpu1.num_int_register_writes 92877962 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 186200 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 85320 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 28186380 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 28117162 # number of times the CC registers were written +system.cpu1.num_mem_refs 38682469 # number of memory refs +system.cpu1.num_load_insts 20321860 # Number of load instructions +system.cpu1.num_store_insts 18360609 # Number of store instructions +system.cpu1.num_idle_cycles 1161291203.919647 # Number of idle cycles +system.cpu1.num_busy_cycles 24808113.080353 # Number of busy cycles +system.cpu1.not_idle_fraction 0.020916 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.979084 # Percentage of idle cycles +system.cpu1.Branches 24140854 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 87315881 69.37% 69.37% # Class of executed instruction -system.cpu1.op_class::IntMult 273375 0.22% 69.58% # Class of executed instruction -system.cpu1.op_class::IntDiv 10716 0.01% 69.59% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 11213 0.01% 69.60% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.60% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.60% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.60% # Class of executed instruction -system.cpu1.op_class::MemRead 20101554 15.97% 85.57% # Class of executed instruction -system.cpu1.op_class::MemWrite 18165140 14.43% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 88426718 69.40% 69.40% # Class of executed instruction +system.cpu1.op_class::IntMult 282557 0.22% 69.62% # Class of executed instruction +system.cpu1.op_class::IntDiv 11066 0.01% 69.63% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.63% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 11198 0.01% 69.64% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.64% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.64% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.64% # Class of executed instruction +system.cpu1.op_class::MemRead 20321860 15.95% 85.59% # Class of executed instruction +system.cpu1.op_class::MemWrite 18360609 14.41% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 125877921 # Class of executed instruction -system.cpu2.branchPred.lookups 39521108 # Number of BP lookups -system.cpu2.branchPred.condPredicted 27394498 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1977688 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 28624019 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 20176228 # Number of BTB hits +system.cpu1.op_class::total 127414050 # Class of executed instruction +system.cpu2.branchPred.lookups 39333191 # Number of BP lookups +system.cpu2.branchPred.condPredicted 27294641 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 2001884 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 28467796 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 20146403 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 70.487055 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 4882878 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 320724 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 70.769100 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 4823620 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 322221 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1472,60 +1486,60 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 93699 # Table walker walks requested -system.cpu2.dtb.walker.walksLong 93699 # Table walker walks initiated with long descriptors -system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 6670 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 29108 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 93699 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 93699 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 93699 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 35778 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 25406.269216 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 22092.991962 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 16331.424603 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-65535 35575 99.43% 99.43% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::131072-196607 169 0.47% 99.90% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::196608-262143 8 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::262144-327679 13 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::327680-393215 3 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::393216-458751 7 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::524288-589823 2 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 35778 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walks 93913 # Table walker walks requested +system.cpu2.dtb.walker.walksLong 93913 # Table walker walks initiated with long descriptors +system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 6917 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 29157 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 93913 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 93913 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 93913 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 36074 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 25782.752121 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 22543.379913 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 16665.993144 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-65535 35851 99.38% 99.38% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::131072-196607 193 0.54% 99.92% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::196608-262143 7 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::262144-327679 7 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::327680-393215 2 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::393216-458751 12 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 36074 # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walksPending::samples 2000224000 # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::0 2000224000 100.00% 100.00% # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::total 2000224000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 29108 81.36% 81.36% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::2M 6670 18.64% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 35778 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93699 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkPageSizes::4K 29157 80.83% 80.83% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::2M 6917 19.17% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 36074 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93913 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93699 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 35778 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93913 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 36074 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 35778 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 129477 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 36074 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 129987 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 28306173 # DTB read hits -system.cpu2.dtb.read_misses 78188 # DTB read misses -system.cpu2.dtb.write_hits 24883433 # DTB write hits -system.cpu2.dtb.write_misses 15511 # DTB write misses +system.cpu2.dtb.read_hits 28226009 # DTB read hits +system.cpu2.dtb.read_misses 78415 # DTB read misses +system.cpu2.dtb.write_hits 24563003 # DTB write hits +system.cpu2.dtb.write_misses 15498 # DTB write misses system.cpu2.dtb.flush_tlb 1186 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 6582 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 193 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 22329 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 81 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 1959 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_tlb_mva_asid 6329 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 174 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 21839 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 87 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 2106 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 3725 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 28384361 # DTB read accesses -system.cpu2.dtb.write_accesses 24898944 # DTB write accesses +system.cpu2.dtb.perms_faults 3581 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 28304424 # DTB read accesses +system.cpu2.dtb.write_accesses 24578501 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 53189606 # DTB hits -system.cpu2.dtb.misses 93699 # DTB misses -system.cpu2.dtb.accesses 53283305 # DTB accesses +system.cpu2.dtb.hits 52789012 # DTB hits +system.cpu2.dtb.misses 93913 # DTB misses +system.cpu2.dtb.accesses 52882925 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1555,86 +1569,85 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 27049 # Table walker walks requested -system.cpu2.itb.walker.walksLong 27049 # Table walker walks initiated with long descriptors -system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1824 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22699 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 27049 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 27049 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 27049 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 24523 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 29055.621254 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 25956.010792 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 17576.904821 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::0-32767 12420 50.65% 50.65% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::32768-65535 11833 48.25% 98.90% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::131072-163839 203 0.83% 99.73% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::163840-196607 48 0.20% 99.92% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::196608-229375 3 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::229376-262143 2 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::262144-294911 7 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::294912-327679 2 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 24523 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walks 26523 # Table walker walks requested +system.cpu2.itb.walker.walksLong 26523 # Table walker walks initiated with long descriptors +system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1844 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22169 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 26523 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 26523 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 26523 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 24013 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 29387.415150 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 26253.368545 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 17691.333892 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-32767 11731 48.85% 48.85% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-65535 12005 49.99% 98.85% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::65536-98303 1 0.00% 98.85% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::131072-163839 207 0.86% 99.71% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::163840-196607 44 0.18% 99.90% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::196608-229375 4 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::229376-262143 5 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::262144-294911 11 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::294912-327679 4 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 24013 # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walksPending::samples 2000197500 # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::0 2000197500 100.00% 100.00% # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::total 2000197500 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 22699 92.56% 92.56% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::2M 1824 7.44% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 24523 # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::4K 22169 92.32% 92.32% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::2M 1844 7.68% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 24013 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27049 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27049 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 26523 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 26523 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24523 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24523 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 51572 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 67920418 # ITB inst hits -system.cpu2.itb.inst_misses 27049 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24013 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24013 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 50536 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 67723691 # ITB inst hits +system.cpu2.itb.inst_misses 26523 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 1186 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 6582 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 193 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 16678 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 6329 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 174 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 16138 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 53297 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 54061 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 67947467 # ITB inst accesses -system.cpu2.itb.hits 67920418 # DTB hits -system.cpu2.itb.misses 27049 # DTB misses -system.cpu2.itb.accesses 67947467 # DTB accesses -system.cpu2.numCycles 6665733461 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 67750214 # ITB inst accesses +system.cpu2.itb.hits 67723691 # DTB hits +system.cpu2.itb.misses 26523 # DTB misses +system.cpu2.itb.accesses 67750214 # DTB accesses +system.cpu2.numCycles 6659048617 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 145260015 # Number of instructions committed -system.cpu2.committedOps 170560320 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 13528820 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 1578 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 95889999557 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 45.888288 # CPI: cycles per instruction -system.cpu2.ipc 0.021792 # IPC: instructions per cycle +system.cpu2.committedInsts 144506436 # Number of instructions committed +system.cpu2.committedOps 169371182 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 13466455 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 1418 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 95896546126 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 46.081329 # CPI: cycles per instruction +system.cpu2.ipc 0.021701 # IPC: instructions per cycle system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 269818486 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 6395914975 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 73106744 # Number of BP lookups -system.cpu3.branchPred.condPredicted 49439775 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 3283160 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 49494170 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 35647247 # Number of BTB hits +system.cpu2.tickCycles 268737972 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 6390310645 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 73239801 # Number of BP lookups +system.cpu3.branchPred.condPredicted 49591629 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 3277800 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 49581893 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 35671982 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 72.023123 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 9537276 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 105421 # Number of incorrect RAS predictions. +system.cpu3.branchPred.BTBHitPct 71.945583 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 9593725 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 104101 # Number of incorrect RAS predictions. system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1664,85 +1677,86 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.walks 494727 # Table walker walks requested -system.cpu3.dtb.walker.walksLong 494727 # Table walker walks initiated with long descriptors -system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8139 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 49597 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 307402 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 187325 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 2316.431336 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 13967.085425 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-65535 186132 99.36% 99.36% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-131071 667 0.36% 99.72% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::131072-196607 353 0.19% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::196608-262143 78 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::262144-327679 59 0.03% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::327680-393215 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::393216-458751 16 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::458752-524287 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walks 505460 # Table walker walks requested +system.cpu3.dtb.walker.walksLong 505460 # Table walker walks initiated with long descriptors +system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8485 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 50148 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 317089 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 188371 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 2400.557942 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 14374.756208 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-65535 187128 99.34% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-131071 697 0.37% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::131072-196607 376 0.20% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::196608-262143 72 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::262144-327679 52 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::327680-393215 16 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::393216-458751 17 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::458752-524287 11 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 187325 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 229787 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 22726.216017 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 18353.180951 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 18914.444967 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-65535 225128 97.97% 97.97% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3594 1.56% 99.54% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::131072-196607 720 0.31% 99.85% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::196608-262143 65 0.03% 99.88% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::262144-327679 153 0.07% 99.94% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::327680-393215 80 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::393216-458751 33 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 229787 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -29283845516 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 0.245317 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-3 -29839367516 101.90% 101.90% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-7 306582000 -1.05% 100.85% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-11 107118000 -0.37% 100.48% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-15 65892000 -0.23% 100.26% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-19 24591000 -0.08% 100.18% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-23 14226000 -0.05% 100.13% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-27 14020500 -0.05% 100.08% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::28-31 18907500 -0.06% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::32-35 4030000 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::36-39 146000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::40-43 9000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -29283845516 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 49597 85.90% 85.90% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::2M 8139 14.10% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 57736 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 494727 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::total 188371 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 238710 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 23086.443802 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 18810.822067 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 18314.114651 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-65535 233850 97.96% 97.96% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3840 1.61% 99.57% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::131072-196607 732 0.31% 99.88% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::196608-262143 60 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::262144-327679 102 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::327680-393215 74 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::393216-458751 30 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::458752-524287 19 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::total 238710 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -29357088016 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 0.121049 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-3 -29941141016 101.99% 101.99% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-7 322648500 -1.10% 100.89% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-11 112094000 -0.38% 100.51% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-15 67602000 -0.23% 100.28% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-19 26479500 -0.09% 100.19% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-23 15506000 -0.05% 100.14% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-27 14594500 -0.05% 100.09% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::28-31 20339000 -0.07% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::32-35 4463500 -0.02% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::36-39 262500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::40-43 36500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::44-47 11000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::48-51 16000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -29357088016 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 50148 85.53% 85.53% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::2M 8485 14.47% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 58633 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 505460 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 494727 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 57736 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 505460 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 58633 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 57736 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 552463 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 58633 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 564093 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 58246352 # DTB read hits -system.cpu3.dtb.read_misses 339748 # DTB read misses -system.cpu3.dtb.write_hits 45232753 # DTB write hits -system.cpu3.dtb.write_misses 154979 # DTB write misses +system.cpu3.dtb.read_hits 58374270 # DTB read hits +system.cpu3.dtb.read_misses 343208 # DTB read misses +system.cpu3.dtb.write_hits 45394406 # DTB write hits +system.cpu3.dtb.write_misses 162252 # DTB write misses system.cpu3.dtb.flush_tlb 1185 # Number of times complete TLB was flushed system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.dtb.flush_tlb_mva_asid 11213 # Number of times TLB was flushed by MVA & ASID -system.cpu3.dtb.flush_tlb_asid 305 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 29617 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 79 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 4718 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_tlb_mva_asid 11285 # Number of times TLB was flushed by MVA & ASID +system.cpu3.dtb.flush_tlb_asid 309 # Number of times TLB was flushed by ASID +system.cpu3.dtb.flush_entries 30021 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 85 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 4958 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 32277 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 58586100 # DTB read accesses -system.cpu3.dtb.write_accesses 45387732 # DTB write accesses +system.cpu3.dtb.perms_faults 33059 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 58717478 # DTB read accesses +system.cpu3.dtb.write_accesses 45556658 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 103479105 # DTB hits -system.cpu3.dtb.misses 494727 # DTB misses -system.cpu3.dtb.accesses 103973832 # DTB accesses +system.cpu3.dtb.hits 103768676 # DTB hits +system.cpu3.dtb.misses 505460 # DTB misses +system.cpu3.dtb.accesses 104274136 # DTB accesses system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1772,214 +1786,220 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.walks 60127 # Table walker walks requested -system.cpu3.itb.walker.walksLong 60127 # Table walker walks initiated with long descriptors -system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1977 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksLongTerminationLevel::Level3 41370 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 8202 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 51925 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1583.187289 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 9631.832849 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-32767 51469 99.12% 99.12% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-65535 278 0.54% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-98303 39 0.08% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::98304-131071 41 0.08% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::131072-163839 70 0.13% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::163840-196607 14 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::262144-294911 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 51925 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 51549 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 29040.146269 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 24568.436348 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 21519.136506 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-65535 50502 97.97% 97.97% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::65536-131071 358 0.69% 98.66% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::131072-196607 600 1.16% 99.83% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::196608-262143 30 0.06% 99.89% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::262144-327679 32 0.06% 99.95% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::327680-393215 16 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::524288-589823 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 51549 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -29286303016 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 0.896957 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::stdev 0.299007 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 -2976637360 10.16% 10.16% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -26347752656 89.97% 100.13% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 35165500 -0.12% 100.01% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 2840000 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 71000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::5 10500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -29286303016 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 41370 95.44% 95.44% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::2M 1977 4.56% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 43347 # Table walker page sizes translated +system.cpu3.itb.walker.walks 59314 # Table walker walks requested +system.cpu3.itb.walker.walksLong 59314 # Table walker walks initiated with long descriptors +system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1821 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksLongTerminationLevel::Level3 40895 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 8206 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 51108 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1703.676528 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 11026.142257 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-65535 50913 99.62% 99.62% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-131071 102 0.20% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::131072-196607 75 0.15% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::196608-262143 8 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::262144-327679 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::327680-393215 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 51108 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 50922 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 29945.907466 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 25308.766579 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 21817.874172 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-32767 25421 49.92% 49.92% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-65535 24387 47.89% 97.81% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::65536-98303 352 0.69% 98.50% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::98304-131071 53 0.10% 98.61% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::131072-163839 469 0.92% 99.53% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::163840-196607 137 0.27% 99.80% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::196608-229375 21 0.04% 99.84% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::229376-262143 18 0.04% 99.87% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::262144-294911 34 0.07% 99.94% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::294912-327679 8 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::393216-425983 10 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::425984-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::total 50922 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -29359762516 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.915313 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.271710 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -2440067696 8.31% 8.31% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -26959816320 91.83% 100.14% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 35306500 -0.12% 100.02% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 3658500 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 936500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::5 210500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::6 9500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -29359762516 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 40895 95.74% 95.74% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::2M 1821 4.26% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 42716 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 60127 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 60127 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 59314 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 59314 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 43347 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 43347 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 103474 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 52640414 # ITB inst hits -system.cpu3.itb.inst_misses 60127 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 42716 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 42716 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 102030 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 52851082 # ITB inst hits +system.cpu3.itb.inst_misses 59314 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses system.cpu3.itb.flush_tlb 1185 # Number of times complete TLB was flushed system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.itb.flush_tlb_mva_asid 11213 # Number of times TLB was flushed by MVA & ASID -system.cpu3.itb.flush_tlb_asid 305 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 23184 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_tlb_mva_asid 11285 # Number of times TLB was flushed by MVA & ASID +system.cpu3.itb.flush_tlb_asid 309 # Number of times TLB was flushed by ASID +system.cpu3.itb.flush_entries 23077 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 115097 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 115085 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 52700541 # ITB inst accesses -system.cpu3.itb.hits 52640414 # DTB hits -system.cpu3.itb.misses 60127 # DTB misses -system.cpu3.itb.accesses 52700541 # DTB accesses -system.cpu3.numCycles 367415947 # number of cpu cycles simulated +system.cpu3.itb.inst_accesses 52910396 # ITB inst accesses +system.cpu3.itb.hits 52851082 # DTB hits +system.cpu3.itb.misses 59314 # DTB misses +system.cpu3.itb.accesses 52910396 # DTB accesses +system.cpu3.numCycles 366771262 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 138047852 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 324925438 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 73106744 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 45184523 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 206488551 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 7421915 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 1494390 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 8711 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 1919 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 2933513 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 92576 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 5529 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 52507671 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 2023167 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 24008 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 352783845 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.078296 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.326372 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 138418640 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 325485816 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 73239801 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 45265707 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 205393679 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 7423141 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 1497672 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 9430 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 1874 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 2924706 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 99692 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 5815 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 52718711 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 2024184 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 23519 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 352062887 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.083114 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.330461 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 272678491 77.29% 77.29% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 9999177 2.83% 80.13% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 10154215 2.88% 83.01% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 7447502 2.11% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 15397984 4.36% 89.48% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 5025734 1.42% 90.91% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 5401897 1.53% 92.44% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 4807386 1.36% 93.80% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 21871459 6.20% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 271718451 77.18% 77.18% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 10078354 2.86% 80.04% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 10184487 2.89% 82.93% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 7481893 2.13% 85.06% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 15414285 4.38% 89.44% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 5033705 1.43% 90.87% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 5437919 1.54% 92.41% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 4732299 1.34% 93.76% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 21981494 6.24% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 352783845 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.198975 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.884353 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 112906719 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 170627658 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 59194480 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 7143620 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2909626 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 10993587 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 812434 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 355125435 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 2492983 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 2909626 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 117007450 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 13956942 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 135354583 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 62147599 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 21405678 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 346848000 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 65680 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 1218522 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 931993 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 11105485 # Number of times rename has blocked due to SQ full -system.cpu3.rename.FullRegisterEvents 2097 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 331495484 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 531299079 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 409883872 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 498256 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 278579121 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 52916358 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 7952838 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 6842362 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 39655118 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 56090576 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 47550992 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 7265418 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 7939600 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 329496362 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 7936863 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 329269236 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 468664 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 44300133 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 28411196 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 197124 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 352783845 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.933346 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.659424 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 352062887 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.199688 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.887435 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 113153102 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 169455061 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 59387304 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 7156871 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2908724 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 10935425 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 813859 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 356017985 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 2501114 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 2908724 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 117268615 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 13616294 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 135215564 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 62340466 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 20711186 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 347737029 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 54468 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 1175747 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 937238 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 10392106 # Number of times rename has blocked due to SQ full +system.cpu3.rename.FullRegisterEvents 2088 # Number of times there has been no free registers +system.cpu3.rename.RenamedOperands 332468090 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 532744217 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 410951019 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 499537 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 279653291 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 52814794 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 7988531 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 6878375 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 39718769 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 56231921 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 47708003 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 7270204 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 7954464 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 330360579 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 7980408 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 330210395 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 469256 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 44146528 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 28275391 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 197239 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 352062887 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.937930 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.662080 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 224815035 63.73% 63.73% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 52801661 14.97% 78.69% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 24147394 6.84% 85.54% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 17186087 4.87% 90.41% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 12829115 3.64% 94.05% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 9014914 2.56% 96.60% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 6070700 1.72% 98.32% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 3552216 1.01% 99.33% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 2366723 0.67% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 223668227 63.53% 63.53% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 53015699 15.06% 78.59% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 24255391 6.89% 85.48% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 17227433 4.89% 90.37% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 12830165 3.64% 94.02% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 9047221 2.57% 96.59% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 6060563 1.72% 98.31% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 3584032 1.02% 99.33% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 2374156 0.67% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 352783845 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 352062887 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 1655726 25.42% 25.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 16802 0.26% 25.68% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 1467 0.02% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 2658135 40.82% 66.52% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 2180482 33.48% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 1667670 25.64% 25.64% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 16900 0.26% 25.90% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 1465 0.02% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 2 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.93% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 2634602 40.51% 66.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 2182377 33.56% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 27 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 223168493 67.78% 67.78% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 780707 0.24% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 40175 0.01% 68.03% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 174 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 223824222 67.78% 67.78% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 774202 0.23% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 40056 0.01% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 168 0.00% 68.03% # Type of FU issued system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.03% # Type of FU issued system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.03% # Type of FU issued system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.03% # Type of FU issued @@ -1992,7 +2012,7 @@ system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.03% # Ty system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.03% # Type of FU issued system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.03% # Type of FU issued system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 1 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.03% # Type of FU issued system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.03% # Type of FU issued system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.03% # Type of FU issued system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.03% # Type of FU issued @@ -2001,100 +2021,100 @@ system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.03% # Ty system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.03% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.03% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 42531 0.01% 68.04% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 44646 0.01% 68.04% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.04% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.04% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 59412355 18.04% 86.08% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 45824773 13.92% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 59535864 18.03% 86.07% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 45991226 13.93% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 329269236 # Type of FU issued -system.cpu3.iq.rate 0.896176 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 6512612 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.019779 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 1017639354 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 381768294 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 317351059 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 664239 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 330816 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 296027 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 335426759 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 355062 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 2617033 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 330210395 # Type of FU issued +system.cpu3.iq.rate 0.900317 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 6503016 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.019694 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 1018785662 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 382537276 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 318334132 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 670287 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 332759 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 299480 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 336355093 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 358307 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 2644941 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 8910571 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 11930 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 371819 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 4873914 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 8880043 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 11323 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 388636 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 4860112 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 2093383 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 4209996 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 2108647 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 4155835 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2909626 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 8686652 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 4058716 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 337508586 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 999497 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 56090576 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 47550992 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 6693033 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 115188 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 3897473 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 371819 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 1479948 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1304525 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 2784473 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 325518299 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 58237072 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 3261982 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 2908724 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 8517603 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 3858124 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 338416485 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 997667 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 56231921 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 47708003 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 6730848 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 119383 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 3692835 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 388636 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 1480307 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1295138 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 2775445 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 326459428 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 58365019 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 3251449 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 75361 # number of nop insts executed -system.cpu3.iew.exec_refs 103468304 # number of memory reference insts executed -system.cpu3.iew.exec_branches 60421077 # Number of branches executed -system.cpu3.iew.exec_stores 45231232 # Number of stores executed -system.cpu3.iew.exec_rate 0.885967 # Inst execution rate -system.cpu3.iew.wb_sent 318319204 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 317647086 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 156971025 # num instructions producing a value -system.cpu3.iew.wb_consumers 272519290 # num instructions consuming a value -system.cpu3.iew.wb_rate 0.864544 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.576000 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 44325764 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7739739 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 2481675 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 345244332 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.849060 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.846955 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 75498 # number of nop insts executed +system.cpu3.iew.exec_refs 103758179 # number of memory reference insts executed +system.cpu3.iew.exec_branches 60585574 # Number of branches executed +system.cpu3.iew.exec_stores 45393160 # Number of stores executed +system.cpu3.iew.exec_rate 0.890090 # Inst execution rate +system.cpu3.iew.wb_sent 319299995 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 318633612 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 157331551 # num instructions producing a value +system.cpu3.iew.wb_consumers 273213532 # num instructions consuming a value +system.cpu3.iew.wb_rate 0.868753 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.575856 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 44171670 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7783169 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 2474762 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 344535281 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.853888 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.850951 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 238738698 69.15% 69.15% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 51567808 14.94% 84.09% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 18622481 5.39% 89.48% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8388535 2.43% 91.91% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 6065452 1.76% 93.67% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 3663652 1.06% 94.73% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 3429214 0.99% 95.72% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 2148576 0.62% 96.34% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 12619916 3.66% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 237617500 68.97% 68.97% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 51794932 15.03% 84.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 18673564 5.42% 89.42% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8409945 2.44% 91.86% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 6103204 1.77% 93.63% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 3702818 1.07% 94.71% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 3412254 0.99% 95.70% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 2146383 0.62% 96.32% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 12674681 3.68% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 345244332 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 249501623 # Number of instructions committed -system.cpu3.commit.committedOps 293133087 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 344535281 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 250269181 # Number of instructions committed +system.cpu3.commit.committedOps 294194454 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 89857082 # Number of memory references committed -system.cpu3.commit.loads 47180004 # Number of loads committed -system.cpu3.commit.membars 1961101 # Number of memory barriers committed -system.cpu3.commit.branches 55730410 # Number of branches committed -system.cpu3.commit.fp_insts 284466 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 269318634 # Number of committed integer instructions. -system.cpu3.commit.function_calls 7382541 # Number of function calls committed. +system.cpu3.commit.refs 90199768 # Number of memory references committed +system.cpu3.commit.loads 47351877 # Number of loads committed +system.cpu3.commit.membars 1984419 # Number of memory barriers committed +system.cpu3.commit.branches 55927856 # Number of branches committed +system.cpu3.commit.fp_insts 287957 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 270378967 # Number of committed integer instructions. +system.cpu3.commit.function_calls 7437415 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 202599565 69.12% 69.12% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 609386 0.21% 69.32% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 30413 0.01% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 203317857 69.11% 69.11% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 607807 0.21% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 30328 0.01% 69.33% # Class of committed instruction system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction @@ -2117,39 +2137,39 @@ system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.33% # system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 36641 0.01% 69.35% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.35% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.35% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.35% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 47180004 16.10% 85.44% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 42677078 14.56% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 38694 0.01% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 47351877 16.10% 85.44% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 42847891 14.56% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 293133087 # Class of committed instruction -system.cpu3.commit.bw_lim_events 12619916 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 668027626 # The number of ROB reads -system.cpu3.rob.rob_writes 682469296 # The number of ROB writes -system.cpu3.timesIdled 2366991 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 14632102 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 98631076285 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 249501623 # Number of Instructions Simulated -system.cpu3.committedOps 293133087 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.472599 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.472599 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.679071 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.679071 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 383683244 # number of integer regfile reads -system.cpu3.int_regfile_writes 227091338 # number of integer regfile writes -system.cpu3.fp_regfile_reads 575742 # number of floating regfile reads -system.cpu3.fp_regfile_writes 354224 # number of floating regfile writes -system.cpu3.cc_regfile_reads 69408942 # number of cc regfile reads -system.cpu3.cc_regfile_writes 70047711 # number of cc regfile writes -system.cpu3.misc_regfile_reads 653726404 # number of misc regfile reads -system.cpu3.misc_regfile_writes 7798013 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40238 # Transaction distribution -system.iobus.trans_dist::ReadResp 40238 # Transaction distribution -system.iobus.trans_dist::WriteReq 136511 # Transaction distribution -system.iobus.trans_dist::WriteResp 136511 # Transaction distribution +system.cpu3.commit.op_class_0::total 294194454 # Class of committed instruction +system.cpu3.commit.bw_lim_events 12674681 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 668190501 # The number of ROB reads +system.cpu3.rob.rob_writes 684271435 # The number of ROB writes +system.cpu3.timesIdled 2367007 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 14708375 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 98631571593 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 250269181 # Number of Instructions Simulated +system.cpu3.committedOps 294194454 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.465507 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.465507 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.682358 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.682358 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 384861666 # number of integer regfile reads +system.cpu3.int_regfile_writes 227851781 # number of integer regfile writes +system.cpu3.fp_regfile_reads 577247 # number of floating regfile reads +system.cpu3.fp_regfile_writes 366452 # number of floating regfile writes +system.cpu3.cc_regfile_reads 69640374 # number of cc regfile reads +system.cpu3.cc_regfile_writes 70304463 # number of cc regfile writes +system.cpu3.misc_regfile_reads 653638120 # number of misc regfile reads +system.cpu3.misc_regfile_writes 7847503 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40268 # Transaction distribution +system.iobus.trans_dist::ReadResp 40268 # Transaction distribution +system.iobus.trans_dist::WriteReq 136537 # Transaction distribution +system.iobus.trans_dist::WriteResp 136537 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47686 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) @@ -2161,14 +2181,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29444 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122464 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122568 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353498 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353610 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47706 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -2180,90 +2200,94 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155640 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155698 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7491974 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 34324500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 30025500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 5500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 218500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 84500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 5500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13530000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 12632000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 21519000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 21450000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 268744919 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 266387325 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 59904000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 55488000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 77390000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 76928000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115459 # number of replacements -system.iocache.tags.tagsinuse 10.420604 # Cycle average of tags in use +system.iocache.tags.replacements 115463 # number of replacements +system.iocache.tags.tagsinuse 10.420638 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13089166746509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.547315 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.873289 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 13089107754009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.547310 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.873329 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.221707 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429581 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651288 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429583 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651290 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039650 # Number of tag accesses -system.iocache.tags.data_accesses 1039650 # Number of data accesses +system.iocache.tags.tag_accesses 1039686 # Number of tag accesses +system.iocache.tags.data_accesses 1039686 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses -system.iocache.demand_misses::total 8853 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses +system.iocache.demand_misses::total 8857 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8813 # number of overall misses -system.iocache.overall_misses::total 8853 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 1097461741 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1097461741 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 6290187178 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 6290187178 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 1097461741 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1097461741 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 1097461741 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1097461741 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8817 # number of overall misses +system.iocache.overall_misses::total 8857 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 1084750278 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1084750278 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 6232375047 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 6232375047 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 1084750278 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1084750278 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 1084750278 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1084750278 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2277,506 +2301,507 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124527.600250 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124006.976384 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 58971.979093 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 58971.979093 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124527.600250 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 123964.954366 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124527.600250 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 123964.954366 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22895 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123029.406601 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122515.278744 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 58429.976815 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 58429.976815 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123029.406601 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122473.780964 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123029.406601 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122473.780964 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22350 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2302 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2283 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.945699 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.789750 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 5727 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 5727 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 50000 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 50000 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 5727 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 5727 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 5727 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 5727 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 811111741 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 811111741 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3787932075 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3787932075 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 811111741 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 811111741 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 811111741 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 811111741 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.649835 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.647119 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.468762 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.468762 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.649835 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.646899 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.649835 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.646899 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141629.429195 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 141629.429195 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75758.641500 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75758.641500 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 141629.429195 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 141629.429195 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 141629.429195 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 141629.429195 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::realview.ide 5720 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 5720 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 49552 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 49552 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 5720 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 5720 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 5720 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 5720 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 798750278 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 798750278 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3752561184 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3752561184 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 798750278 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 798750278 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 798750278 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 798750278 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.648747 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.646036 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.464562 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.464562 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.648747 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.645817 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.648747 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.645817 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139641.656993 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 139641.656993 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75729.762351 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75729.762351 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 139641.656993 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 139641.656993 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 139641.656993 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 139641.656993 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1134655 # number of replacements -system.l2c.tags.tagsinuse 65348.585655 # Cycle average of tags in use -system.l2c.tags.total_refs 47218951 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1196839 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 39.453052 # Average number of references to valid blocks. +system.l2c.tags.replacements 1152001 # number of replacements +system.l2c.tags.tagsinuse 65364.503704 # Cycle average of tags in use +system.l2c.tags.total_refs 47325190 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1214241 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 38.975121 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36858.424918 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 139.336234 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 207.961932 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3464.040368 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 8073.434256 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 31.851614 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 46.563538 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 388.442961 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2039.653767 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 38.632115 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 59.555007 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1814.509325 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3538.387838 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 81.542571 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.itb.walker 121.893588 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2682.398731 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 5761.956894 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562415 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002126 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003173 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.052857 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.123191 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000486 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000711 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.005927 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.031123 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000589 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000909 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.027687 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.053992 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001244 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.itb.walker 0.001860 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.040930 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.087920 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.997140 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 269 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 61915 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 268 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 568 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2797 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5091 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53356 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004105 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.944748 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 417874191 # Number of tag accesses -system.l2c.tags.data_accesses 417874191 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 157547 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 107991 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 56540 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 42358 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 150716 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 57617 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.dtb.walker 285535 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.itb.walker 108659 # number of ReadReq hits -system.l2c.ReadReq_hits::total 966963 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 7469710 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 7469710 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 15704683 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 15704683 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 3849 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1299 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 1546 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3.data 2673 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9367 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 642784 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 197897 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 265419 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3.data 474003 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1580103 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 5527952 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 1660805 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 3842883 # 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number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2.data 39147 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3.data 77644 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 251264 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 397385 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 19162 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu2.data 25286 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu3.data 48757 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 490590 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1252 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1338 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 35247 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 284791 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 421 # 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average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 68485.733493 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 68702.723845 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 68460.730027 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122395.136778 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127532.646048 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121627.007818 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121918.499480 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 129667.002012 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 125545.454545 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123645.201246 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123319.645345 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 128997.597303 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 128168.938285 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 126144.790929 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 134826.814885 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 128258.541568 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122395.136778 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127532.646048 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121627.007818 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121918.499480 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 129667.002012 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 125545.454545 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123645.201246 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123319.645345 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 128997.597303 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 128168.938285 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 126144.790929 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 134826.814885 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 128258.541568 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183609.571973 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 181128.959975 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 177170.863600 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 180739.095854 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190429.222310 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 187413.608178 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 182098.721493 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 186734.762994 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 186901.228483 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 184143.954012 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 179584.259781 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 183640.880633 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 76702 # Transaction distribution -system.membus.trans_dist::ReadResp 435346 # Transaction distribution -system.membus.trans_dist::WriteReq 33616 # Transaction distribution -system.membus.trans_dist::WriteResp 33616 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1053198 # Transaction distribution -system.membus.trans_dist::CleanEvict 195936 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34438 # Transaction distribution +system.membus.trans_dist::ReadReq 76733 # Transaction distribution +system.membus.trans_dist::ReadResp 441177 # Transaction distribution +system.membus.trans_dist::WriteReq 33644 # Transaction distribution +system.membus.trans_dist::WriteResp 33644 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1065794 # Transaction distribution +system.membus.trans_dist::CleanEvict 200684 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34575 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14271 # Transaction distribution -system.membus.trans_dist::ReadExReq 877665 # Transaction distribution -system.membus.trans_dist::ReadExResp 877665 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 358644 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution -system.membus.trans_dist::InvalidateResp 56664 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122464 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 14206 # Transaction distribution +system.membus.trans_dist::ReadExReq 395991 # Transaction distribution +system.membus.trans_dist::ReadExResp 395991 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 364444 # Transaction distribution +system.membus.trans_dist::InvalidateReq 598844 # Transaction distribution +system.membus.trans_dist::InvalidateResp 451105 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122568 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 61 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6736 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3728417 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3857678 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 295106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 295106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4152784 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6750 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3680339 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3809718 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 295481 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 295481 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4105199 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155698 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 139314336 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 139483644 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7302016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7302016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 146785660 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1643 # Total snoops (count) -system.membus.snoop_fanout::samples 2736894 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13500 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 109670240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 109839634 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7296832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7296832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 117136466 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1635 # Total snoops (count) +system.membus.snoop_fanout::samples 2770738 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2736894 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2770738 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2736894 # Request fanout histogram -system.membus.reqLayer0.occupancy 69642000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2770738 # Request fanout histogram +system.membus.reqLayer0.occupancy 64261000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1869502 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1770502 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 3024540179 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 3078925491 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2745498213 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2289724659 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 28895247 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 28858376 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3170,61 +3191,61 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 51377281 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 26019251 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2963 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1998 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1998 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 51493979 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 26073999 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 3069 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2287 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 1480293 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 23646990 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33616 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33616 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 7917317 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 15707105 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2286569 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 43130 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 43132 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1967850 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1967850 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 15707694 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 6464392 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1273831 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1223831 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47208661 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29171496 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 814900 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1708889 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 78903946 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2010714388 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1017569896 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2939088 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6022496 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3037245868 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1649773 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 37956541 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.016464 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.127251 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 1482158 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 23699758 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33644 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33644 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 7970176 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 15734993 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2276280 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 43214 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 43217 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1978540 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1978540 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 15735581 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6487298 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1273838 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1224286 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47292320 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29274050 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 815247 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1729718 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 79111335 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2014283796 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1022659326 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2960744 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6155576 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3046059442 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1649768 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 38047944 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.016242 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.126407 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 37331626 98.35% 98.35% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 624915 1.65% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 37429952 98.38% 98.38% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 617992 1.62% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 37956541 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 30638283989 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 38047944 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 30711072482 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 663187 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 825172 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 15222114677 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 15222500163 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 7813255878 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 7880833554 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 290580214 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 287037671 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 698608876 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 701756875 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index d04b59f4b..e1c1def32 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -1,162 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.408461 # Number of seconds simulated -sim_ticks 51408461373000 # Number of ticks simulated -final_tick 51408461373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.284914 # Number of seconds simulated +sim_ticks 51284914333000 # Number of ticks simulated +final_tick 51284914333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 195616 # Simulator instruction rate (inst/s) -host_op_rate 229875 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11322692573 # Simulator tick rate (ticks/s) -host_mem_usage 696388 # Number of bytes of host memory used -host_seconds 4540.30 # Real time elapsed on the host -sim_insts 888155433 # Number of instructions simulated -sim_ops 1043703833 # Number of ops (including micro ops) simulated +host_inst_rate 235872 # Simulator instruction rate (inst/s) +host_op_rate 277167 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13557886882 # Simulator tick rate (ticks/s) +host_mem_usage 696464 # Number of bytes of host memory used +host_seconds 3782.66 # Real time elapsed on the host +sim_insts 892223547 # Number of instructions simulated +sim_ops 1048428696 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 142656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 137152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3491584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 41406368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 143936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 139584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3767424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 42881448 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 438400 # Number of bytes read from this memory -system.physmem.bytes_read::total 92548552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3491584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3767424 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7259008 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 78363136 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 145024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 130496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3660544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 27123808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 158784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 143040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3643072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 26095080 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 424512 # Number of bytes read from this memory +system.physmem.bytes_read::total 61524360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3660544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3643072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7303616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 79842048 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory -system.physmem.bytes_written::total 78383716 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2229 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2143 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 54556 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 646983 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2249 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2181 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 58866 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 670027 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6850 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1446084 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1224424 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 79862628 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2266 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2039 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 57196 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 423818 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2481 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2235 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 407740 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6633 # Number of read requests responded to by this memory +system.physmem.num_reads::total 961331 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1247532 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1226997 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2668 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 67918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 805439 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2800 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2715 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 73284 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 834132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8528 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1800259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 67918 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 73284 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 141203 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1524324 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1250105 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2828 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 71377 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 528885 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2789 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 71036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 508826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1199658 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 71377 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 71036 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 142413 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1556833 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 400 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1524724 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1524324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2668 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 67918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 805439 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2800 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2715 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 73284 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 834532 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8528 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3324983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1446084 # Number of read requests accepted -system.physmem.writeReqs 1226997 # Number of write requests accepted -system.physmem.readBursts 1446084 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1226997 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 92503744 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 45632 # Total number of bytes read from write queue -system.physmem.bytesWritten 78384064 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 92548552 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 78383716 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 713 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::cpu1.data 401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1557234 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1556833 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 71377 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 528885 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 71036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 509227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2756892 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 961331 # Number of read requests accepted +system.physmem.writeReqs 1250105 # Number of write requests accepted +system.physmem.readBursts 961331 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1250105 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61479104 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 46080 # Total number of bytes read from write queue +system.physmem.bytesWritten 79862656 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 61524360 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 79862628 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 720 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 88572 # Per bank write bursts -system.physmem.perBankRdBursts::1 91936 # Per bank write bursts -system.physmem.perBankRdBursts::2 86142 # Per bank write bursts -system.physmem.perBankRdBursts::3 85794 # Per bank write bursts -system.physmem.perBankRdBursts::4 86883 # Per bank write bursts -system.physmem.perBankRdBursts::5 96343 # Per bank write bursts -system.physmem.perBankRdBursts::6 89494 # Per bank write bursts -system.physmem.perBankRdBursts::7 87879 # Per bank write bursts -system.physmem.perBankRdBursts::8 83471 # Per bank write bursts -system.physmem.perBankRdBursts::9 112607 # Per bank write bursts -system.physmem.perBankRdBursts::10 93875 # Per bank write bursts -system.physmem.perBankRdBursts::11 93808 # Per bank write bursts -system.physmem.perBankRdBursts::12 88268 # Per bank write bursts -system.physmem.perBankRdBursts::13 91281 # Per bank write bursts -system.physmem.perBankRdBursts::14 84984 # Per bank write bursts -system.physmem.perBankRdBursts::15 84034 # Per bank write bursts -system.physmem.perBankWrBursts::0 75348 # Per bank write bursts -system.physmem.perBankWrBursts::1 77371 # Per bank write bursts -system.physmem.perBankWrBursts::2 73838 # Per bank write bursts -system.physmem.perBankWrBursts::3 75932 # Per bank write bursts -system.physmem.perBankWrBursts::4 75756 # Per bank write bursts -system.physmem.perBankWrBursts::5 80933 # Per bank write bursts -system.physmem.perBankWrBursts::6 75453 # Per bank write bursts -system.physmem.perBankWrBursts::7 77252 # Per bank write bursts -system.physmem.perBankWrBursts::8 72443 # Per bank write bursts -system.physmem.perBankWrBursts::9 79503 # Per bank write bursts -system.physmem.perBankWrBursts::10 78639 # Per bank write bursts -system.physmem.perBankWrBursts::11 80056 # Per bank write bursts -system.physmem.perBankWrBursts::12 76299 # Per bank write bursts -system.physmem.perBankWrBursts::13 79068 # Per bank write bursts -system.physmem.perBankWrBursts::14 73755 # Per bank write bursts -system.physmem.perBankWrBursts::15 73105 # Per bank write bursts +system.physmem.perBankRdBursts::0 54441 # Per bank write bursts +system.physmem.perBankRdBursts::1 61427 # Per bank write bursts +system.physmem.perBankRdBursts::2 55898 # Per bank write bursts +system.physmem.perBankRdBursts::3 54692 # Per bank write bursts +system.physmem.perBankRdBursts::4 58805 # Per bank write bursts +system.physmem.perBankRdBursts::5 68407 # Per bank write bursts +system.physmem.perBankRdBursts::6 58313 # Per bank write bursts +system.physmem.perBankRdBursts::7 55590 # Per bank write bursts +system.physmem.perBankRdBursts::8 55296 # Per bank write bursts +system.physmem.perBankRdBursts::9 81756 # Per bank write bursts +system.physmem.perBankRdBursts::10 60407 # Per bank write bursts +system.physmem.perBankRdBursts::11 65146 # Per bank write bursts +system.physmem.perBankRdBursts::12 55694 # Per bank write bursts +system.physmem.perBankRdBursts::13 60470 # Per bank write bursts +system.physmem.perBankRdBursts::14 57025 # Per bank write bursts +system.physmem.perBankRdBursts::15 57244 # Per bank write bursts +system.physmem.perBankWrBursts::0 74045 # Per bank write bursts +system.physmem.perBankWrBursts::1 78136 # Per bank write bursts +system.physmem.perBankWrBursts::2 75823 # Per bank write bursts +system.physmem.perBankWrBursts::3 77240 # Per bank write bursts +system.physmem.perBankWrBursts::4 78053 # Per bank write bursts +system.physmem.perBankWrBursts::5 84172 # Per bank write bursts +system.physmem.perBankWrBursts::6 76930 # Per bank write bursts +system.physmem.perBankWrBursts::7 76507 # Per bank write bursts +system.physmem.perBankWrBursts::8 76285 # Per bank write bursts +system.physmem.perBankWrBursts::9 81372 # Per bank write bursts +system.physmem.perBankWrBursts::10 77794 # Per bank write bursts +system.physmem.perBankWrBursts::11 82580 # Per bank write bursts +system.physmem.perBankWrBursts::12 74509 # Per bank write bursts +system.physmem.perBankWrBursts::13 79277 # Per bank write bursts +system.physmem.perBankWrBursts::14 77656 # Per bank write bursts +system.physmem.perBankWrBursts::15 77475 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 38 # Number of times write queue was full causing retry -system.physmem.totGap 51408460130000 # Total gap between requests +system.physmem.numWrRetry 33 # Number of times write queue was full causing retry +system.physmem.totGap 51284913090000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1446069 # Read request sizes (log2) +system.physmem.readPktSize::6 961316 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1224424 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 664932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 398664 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 216465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 159288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1228 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 757 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 142 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1247532 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 543719 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 274396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 94312 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 42532 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 592 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 687 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -165,185 +165,172 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 13236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 16854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 31810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 43103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 72394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 72889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 73918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 75976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 75696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 76621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 81917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 79068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 92468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 101068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 77598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 81385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 73598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 92 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 563019 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 303.519817 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.962282 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.070466 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 224938 39.95% 39.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 128250 22.78% 62.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 55139 9.79% 72.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 26598 4.72% 77.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 23698 4.21% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13004 2.31% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 13485 2.40% 86.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9030 1.60% 87.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 68877 12.23% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 563019 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 69941 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.665075 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 231.098088 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 69936 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-6143 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-8191 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::59392-61439 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 69941 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 69941 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.511202 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.923338 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.360496 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 37 0.05% 0.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 29 0.04% 0.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 15 0.02% 0.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 59 0.08% 0.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 66137 94.56% 94.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1542 2.20% 96.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 224 0.32% 97.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 273 0.39% 97.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 66 0.09% 97.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 90 0.13% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 208 0.30% 98.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 42 0.06% 98.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 345 0.49% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 68 0.10% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 33 0.05% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 68 0.10% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 312 0.45% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 25 0.04% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 24 0.03% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 113 0.16% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 171 0.24% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 6 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 4 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 25 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 69941 # Writes before turning the bus around for reads -system.physmem.totQLat 42029385276 # Total ticks spent queuing -system.physmem.totMemAccLat 69130091526 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 7226855000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29078.61 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 28650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 34467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 48429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 53938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 67048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 70774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 72215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 72774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 73979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 82935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 76409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 89855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 76735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 77015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 82497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 72294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 70858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 68160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 96 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 561177 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 251.866630 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 150.815130 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 291.463467 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 247728 44.14% 44.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 140365 25.01% 69.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53282 9.49% 78.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 26503 4.72% 83.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 19913 3.55% 86.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11301 2.01% 88.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10454 1.86% 90.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6842 1.22% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 44789 7.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 561177 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 64799 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.824287 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 53.599336 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 64791 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 4 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-3071 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-5119 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7680-8191 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-9727 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 64799 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 64799 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.257303 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.378904 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.471332 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-7 96 0.15% 0.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-15 63 0.10% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 55368 85.45% 85.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 6790 10.48% 96.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 705 1.09% 97.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 466 0.72% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 493 0.76% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 108 0.17% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 328 0.51% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 159 0.25% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 155 0.24% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 9 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 3 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 5 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 16 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 4 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 10 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 7 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::328-335 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 64799 # Writes before turning the bus around for reads +system.physmem.totQLat 25248874155 # Total ticks spent queuing +system.physmem.totMemAccLat 43260330405 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4803055000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26284.18 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47828.61 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.80 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.52 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.52 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 45034.18 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.20 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.08 # Average write queue length when enqueuing -system.physmem.readRowHits 1187061 # Number of row buffer hits during reads -system.physmem.writeRowHits 920040 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.13 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.12 # Row buffer hit rate for writes -system.physmem.avgGap 19231912.59 # Average gap between requests -system.physmem.pageHitRate 78.91 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2145112200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1170448125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5561735400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3965001840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3357750617520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1242334329840 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29755308399000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34368235643925 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.532696 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49500352455310 # Time in different power states -system.physmem_0.memoryStateTime::REF 1716641420000 # Time in different power states +system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.54 # Average write queue length when enqueuing +system.physmem.readRowHits 736430 # Number of row buffer hits during reads +system.physmem.writeRowHits 910858 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.99 # Row buffer hit rate for writes +system.physmem.avgGap 23190774.27 # Average gap between requests +system.physmem.pageHitRate 74.59 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2124654840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1159285875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3647069400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4023470880 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3349681296000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1235871193320 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29686851168000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34283358138315 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.488160 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49386595452825 # Time in different power states +system.physmem_0.memoryStateTime::REF 1712515740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 191465063440 # Time in different power states +system.physmem_0.memoryStateTime::ACT 185803070925 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2111311440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1152005250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5712111600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3971384640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3357750617520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1241846921700 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29755735950000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34368280302150 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.533565 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49501052297586 # Time in different power states -system.physmem_1.memoryStateTime::REF 1716641420000 # Time in different power states +system.physmem_1.actEnergy 2117843280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1155569250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3845696400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4062623040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3349681296000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1240883143470 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29682454712250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34284200883690 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.504593 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49379236035062 # Time in different power states +system.physmem_1.memoryStateTime::REF 1712515740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 190767036414 # Time in different power states +system.physmem_1.memoryStateTime::ACT 193162474938 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 1088 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -373,15 +360,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 131317234 # Number of BP lookups -system.cpu0.branchPred.condPredicted 89033308 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5711784 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 89061890 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 64034993 # Number of BTB hits +system.cpu0.branchPred.lookups 131222767 # Number of BP lookups +system.cpu0.branchPred.condPredicted 88895341 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5715566 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 88848195 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 63996903 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.899432 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17159386 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 186222 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.029491 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17247708 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 186935 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -412,89 +399,89 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 882165 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 882165 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 16962 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90283 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 541135 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 341030 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2470.671202 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 14842.312664 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 338635 99.30% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1231 0.36% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 836 0.25% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 125 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 123 0.04% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 27 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 22 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 27 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 341030 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 406695 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 23181.687751 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18594.894940 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 20266.186322 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 397583 97.76% 97.76% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 6749 1.66% 99.42% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1620 0.40% 99.82% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 124 0.03% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 348 0.09% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 158 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 81 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 17 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 406695 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 362445074540 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.202763 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.718091 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-3 361444437540 99.72% 99.72% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-7 559911000 0.15% 99.88% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-11 188863000 0.05% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-15 117378000 0.03% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-19 44663000 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-23 25341500 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-27 26888500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-31 30794500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::32-35 6481000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::36-39 299000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::40-43 11000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::44-47 3000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::48-51 3500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 362445074540 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 90283 84.18% 84.18% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 16962 15.82% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 107245 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 882165 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 901787 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 901787 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17510 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90865 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 558240 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 343547 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2647.495103 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 15829.601271 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 340846 99.21% 99.21% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1379 0.40% 99.62% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 917 0.27% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 154 0.04% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 149 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 34 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 34 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 32 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 343547 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 423455 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23285.712768 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18859.753792 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 19582.519957 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 414421 97.87% 97.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 6698 1.58% 99.45% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1655 0.39% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 124 0.03% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 334 0.08% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 125 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 53 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 24 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 17 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 423455 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 376351808512 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.148701 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.701209 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-3 375305951012 99.72% 99.72% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-7 568976500 0.15% 99.87% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-11 204601500 0.05% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-15 126494000 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-19 49142500 0.01% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-23 26958000 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-27 28402000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-31 34222000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::32-35 6583500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::36-39 370000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::40-43 35500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::44-47 29500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::48-51 42000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::52-55 500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 376351808512 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 90865 83.84% 83.84% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 17510 16.16% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 108375 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 901787 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 882165 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107245 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 901787 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 108375 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107245 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 989410 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 108375 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 1010162 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 104764153 # DTB read hits -system.cpu0.dtb.read_misses 607812 # DTB read misses -system.cpu0.dtb.write_hits 82241693 # DTB write hits -system.cpu0.dtb.write_misses 274353 # DTB write misses -system.cpu0.dtb.flush_tlb 1109 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 104844993 # DTB read hits +system.cpu0.dtb.read_misses 617686 # DTB read misses +system.cpu0.dtb.write_hits 81833158 # DTB write hits +system.cpu0.dtb.write_misses 284101 # DTB write misses +system.cpu0.dtb.flush_tlb 1099 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 21084 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 563 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 55854 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 162 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9058 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 21489 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 548 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 56009 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 176 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9405 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 56832 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 105371965 # DTB read accesses -system.cpu0.dtb.write_accesses 82516046 # DTB write accesses +system.cpu0.dtb.perms_faults 58104 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 105462679 # DTB read accesses +system.cpu0.dtb.write_accesses 82117259 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 187005846 # DTB hits -system.cpu0.dtb.misses 882165 # DTB misses -system.cpu0.dtb.accesses 187888011 # DTB accesses +system.cpu0.dtb.hits 186678151 # DTB hits +system.cpu0.dtb.misses 901787 # DTB misses +system.cpu0.dtb.accesses 187579938 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -524,838 +511,831 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 108290 # Table walker walks requested -system.cpu0.itb.walker.walksLong 108290 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3192 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 74908 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 14795 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 93495 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1790.395208 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 11668.511629 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 92494 98.93% 98.93% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 513 0.55% 99.48% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 98 0.10% 99.58% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 116 0.12% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 207 0.22% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 24 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 17 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 10 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 93495 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 92895 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 29889.315894 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 24974.829894 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 23485.865012 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 49009 52.76% 52.76% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 41574 44.75% 97.51% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 612 0.66% 98.17% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 79 0.09% 98.26% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 1038 1.12% 99.37% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 333 0.36% 99.73% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 46 0.05% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 56 0.06% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 94 0.10% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 13 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 15 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 9 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 12 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 92895 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 289428770008 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.837978 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -242453514464 -83.77% -83.77% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 531809766472 183.74% 99.97% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 64887000 0.02% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 6499500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 871000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 248000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::6 12500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 289428770008 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 74908 95.91% 95.91% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 3192 4.09% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 78100 # Table walker page sizes translated +system.cpu0.itb.walker.walks 105051 # Table walker walks requested +system.cpu0.itb.walker.walksLong 105051 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3103 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 71842 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 14498 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 90553 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1891.361965 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 11942.072265 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 89471 98.81% 98.81% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 577 0.64% 99.44% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 86 0.09% 99.54% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 126 0.14% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 214 0.24% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 41 0.05% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 17 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 90553 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 89443 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 29726.837204 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 24825.436238 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 23450.909148 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 87272 97.57% 97.57% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 672 0.75% 98.32% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 1265 1.41% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 85 0.10% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 111 0.12% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 21 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 12 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 89443 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 402102979288 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.378343 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -152052427072 -37.81% -37.81% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 554084756860 137.80% 99.98% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 62143500 0.02% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 7613500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 640000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 190500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::6 62000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 402102979288 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 71842 95.86% 95.86% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 3103 4.14% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 74945 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 108290 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 108290 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 105051 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 105051 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 78100 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 78100 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 186390 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 94461785 # ITB inst hits -system.cpu0.itb.inst_misses 108290 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 74945 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 74945 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 179996 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 94456447 # ITB inst hits +system.cpu0.itb.inst_misses 105051 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1109 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1099 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 21084 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 563 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 41856 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 21489 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 548 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 41420 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 202434 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 203143 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 94570075 # ITB inst accesses -system.cpu0.itb.hits 94461785 # DTB hits -system.cpu0.itb.misses 108290 # DTB misses -system.cpu0.itb.accesses 94570075 # DTB accesses -system.cpu0.numCycles 692991159 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 94561498 # ITB inst accesses +system.cpu0.itb.hits 94456447 # DTB hits +system.cpu0.itb.misses 105051 # DTB misses +system.cpu0.itb.accesses 94561498 # DTB accesses +system.cpu0.numCycles 688838520 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 244811791 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 585398201 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 131317234 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 81194379 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 404384012 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 13047908 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2817091 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 21621 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 5789 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 5286158 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 175205 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 3136 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 94240840 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 3527611 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 42921 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 664028482 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.032942 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.287290 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 245587927 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 584587978 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 131222767 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 81244611 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 399140958 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 13083080 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2697287 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 23591 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 4020 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 5373314 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 168933 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 3234 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 94235768 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 3541356 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 41927 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 659540531 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.038718 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.291266 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 519576745 78.25% 78.25% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 18052759 2.72% 80.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 18229592 2.75% 83.71% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 13406945 2.02% 85.73% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 28061689 4.23% 89.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 8964232 1.35% 91.31% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 9738895 1.47% 92.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 8312010 1.25% 94.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 39685615 5.98% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 515133348 78.10% 78.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 18089863 2.74% 80.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 18214710 2.76% 83.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 13345415 2.02% 85.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 28172960 4.27% 89.90% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 9014281 1.37% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 9743812 1.48% 92.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 8313958 1.26% 94.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 39512184 5.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 664028482 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.189493 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.844741 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 199609312 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 340272761 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 105735491 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 13276963 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5131471 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19616175 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 1412684 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 640319872 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 4351333 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5131471 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 207083748 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 31652470 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 258696093 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 111398501 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 50063478 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 625547022 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 86953 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2120320 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 1651060 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 31054223 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 4011 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 597792979 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 961356441 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 739385367 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 793267 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 505102127 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 92690852 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 14931756 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 12960965 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 74096600 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 100382456 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 86370742 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 13395217 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 14366752 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 594049171 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 14966536 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 595443977 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 833379 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 77816816 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 49417916 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 356669 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 664028482 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.896715 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.636729 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 659540531 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.190499 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.848658 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 199724344 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 336015345 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 105250676 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 13405220 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5142823 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19593113 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 1418693 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 638893412 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4361205 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5142823 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 207245201 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 27037727 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 261836460 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 110999671 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 47276188 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 624046996 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 101675 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2286594 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1931238 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 27774354 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 3807 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 596597233 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 959951672 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 737729971 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 774177 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 503848315 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 92748918 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 15071360 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13097285 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 74895654 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 100276299 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 85965913 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 13583222 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 14599367 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 592457087 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 15151612 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 594148769 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 834633 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 77960575 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 49583395 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 368092 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 659540531 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.900853 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.637513 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 431629347 65.00% 65.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 97195183 14.64% 79.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 43390380 6.53% 86.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 30835149 4.64% 90.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 23006785 3.46% 94.28% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 16163925 2.43% 96.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 10905989 1.64% 98.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 6533904 0.98% 99.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 4367820 0.66% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 427069171 64.75% 64.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 97668979 14.81% 79.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 43298472 6.56% 86.13% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 30774138 4.67% 90.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 22917395 3.47% 94.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 16090465 2.44% 96.71% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 10921608 1.66% 98.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 6493545 0.98% 99.35% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 4306758 0.65% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 664028482 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 659540531 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 3037620 25.70% 25.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 25191 0.21% 25.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 2899 0.02% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 1 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4781762 40.45% 66.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 3973331 33.61% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 3033811 25.57% 25.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 25491 0.21% 25.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 3073 0.03% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 1 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4852849 40.90% 66.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3949019 33.29% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 44 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 403794947 67.81% 67.81% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1402722 0.24% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 64715 0.01% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 26 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 1 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 70887 0.01% 68.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.07% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 106816149 17.94% 86.01% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 83294486 13.99% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 26 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 402837369 67.80% 67.80% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1388159 0.23% 68.03% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 66027 0.01% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 24 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 5 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 70383 0.01% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 106898292 17.99% 86.05% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 82888484 13.95% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 595443977 # Type of FU issued -system.cpu0.iq.rate 0.859237 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 11820804 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019852 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1866487578 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 687019560 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 573922610 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1083041 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 536746 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 483014 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 606686496 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 578241 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 4705214 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 594148769 # Type of FU issued +system.cpu0.iq.rate 0.862537 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11864244 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019968 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1859480838 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 685772005 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 572455649 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1056108 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 523485 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 471348 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 605449446 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 563541 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 4712997 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 15648573 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 20037 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 735656 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 8693789 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 15710215 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 20540 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 737635 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 8733080 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 3938518 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 7949396 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 3961996 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 8114796 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5131471 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 16124670 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 13736061 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 609148290 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 1755735 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 100382456 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 86370742 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 12679523 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 224965 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 13426906 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 735656 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2579656 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2261003 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 4840659 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 588863732 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 104752148 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 5709737 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 5142823 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15863683 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 9219529 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 607741320 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 1739282 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 100276299 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 85965913 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 12807299 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 229576 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 8904673 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 737635 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2585247 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2254078 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 4839325 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 587599487 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 104834587 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 5659877 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 132583 # number of nop insts executed -system.cpu0.iew.exec_refs 186992207 # number of memory reference insts executed -system.cpu0.iew.exec_branches 108909859 # Number of branches executed -system.cpu0.iew.exec_stores 82240059 # Number of stores executed -system.cpu0.iew.exec_rate 0.849742 # Inst execution rate -system.cpu0.iew.wb_sent 575604648 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 574405624 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 283543762 # num instructions producing a value -system.cpu0.iew.wb_consumers 491943015 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.828879 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.576375 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 77856968 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 14609867 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4319026 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 650724527 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.816319 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.818422 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 132621 # number of nop insts executed +system.cpu0.iew.exec_refs 186666893 # number of memory reference insts executed +system.cpu0.iew.exec_branches 108670121 # Number of branches executed +system.cpu0.iew.exec_stores 81832306 # Number of stores executed +system.cpu0.iew.exec_rate 0.853029 # Inst execution rate +system.cpu0.iew.wb_sent 574140659 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 572926997 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 282868675 # num instructions producing a value +system.cpu0.iew.wb_consumers 490940827 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.831729 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.576177 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 78001898 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 14783520 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4316576 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 646201132 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.819634 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.819531 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 457095790 70.24% 70.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 94826206 14.57% 84.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 32956684 5.06% 89.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 15335469 2.36% 92.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 10858481 1.67% 93.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 6641395 1.02% 94.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6158141 0.95% 95.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3955723 0.61% 96.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 22896638 3.52% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 452584963 70.04% 70.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 95102471 14.72% 84.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 32986108 5.10% 89.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 15275406 2.36% 92.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 10838243 1.68% 93.90% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 6597010 1.02% 94.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6118779 0.95% 95.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3888693 0.60% 96.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 22809459 3.53% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 650724527 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 451838462 # Number of instructions committed -system.cpu0.commit.committedOps 531198891 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 646201132 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 450421520 # Number of instructions committed +system.cpu0.commit.committedOps 529648124 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 162410836 # Number of memory references committed -system.cpu0.commit.loads 84733883 # Number of loads committed -system.cpu0.commit.membars 3641724 # Number of memory barriers committed -system.cpu0.commit.branches 100706106 # Number of branches committed -system.cpu0.commit.fp_insts 463962 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 487973755 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13314640 # Number of function calls committed. +system.cpu0.commit.refs 161798917 # Number of memory references committed +system.cpu0.commit.loads 84566084 # Number of loads committed +system.cpu0.commit.membars 3697077 # Number of memory barriers committed +system.cpu0.commit.branches 100455887 # Number of branches committed +system.cpu0.commit.fp_insts 452989 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 486555488 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13358896 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 367585865 69.20% 69.20% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1092900 0.21% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 48363 0.01% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 60927 0.01% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 84733883 15.95% 85.38% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 77676953 14.62% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 366654710 69.23% 69.23% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1084981 0.20% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 49052 0.01% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 60464 0.01% 69.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.45% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 84566084 15.97% 85.42% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 77232833 14.58% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 531198891 # Class of committed instruction -system.cpu0.commit.bw_lim_events 22896638 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1233051269 # The number of ROB reads -system.cpu0.rob.rob_writes 1231435060 # The number of ROB writes -system.cpu0.timesIdled 4157054 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 28962677 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 49016383217 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 451838462 # Number of Instructions Simulated -system.cpu0.committedOps 531198891 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.533714 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.533714 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.652012 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.652012 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 694247819 # number of integer regfile reads -system.cpu0.int_regfile_writes 410288637 # number of integer regfile writes -system.cpu0.fp_regfile_reads 858111 # number of floating regfile reads -system.cpu0.fp_regfile_writes 534016 # number of floating regfile writes -system.cpu0.cc_regfile_reads 125553876 # number of cc regfile reads -system.cpu0.cc_regfile_writes 126720582 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1210004868 # number of misc regfile reads -system.cpu0.misc_regfile_writes 14749855 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 10444529 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.973029 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 299923189 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10445041 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.714410 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 529648124 # Class of committed instruction +system.cpu0.commit.bw_lim_events 22809459 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1227111262 # The number of ROB reads +system.cpu0.rob.rob_writes 1228659759 # The number of ROB writes +system.cpu0.timesIdled 4168425 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 29297989 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 52558178888 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 450421520 # Number of Instructions Simulated +system.cpu0.committedOps 529648124 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.529320 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.529320 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.653885 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.653885 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 692871015 # number of integer regfile reads +system.cpu0.int_regfile_writes 409283768 # number of integer regfile writes +system.cpu0.fp_regfile_reads 840073 # number of floating regfile reads +system.cpu0.fp_regfile_writes 520676 # number of floating regfile writes +system.cpu0.cc_regfile_reads 125256927 # number of cc regfile reads +system.cpu0.cc_regfile_writes 126444735 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1205784103 # number of misc regfile reads +system.cpu0.misc_regfile_writes 14898501 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 10501142 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.972965 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 301139944 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10501654 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.675478 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 2716190500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 311.726470 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 200.246559 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.608841 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.391107 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 283.786006 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 228.186958 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.554270 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.445678 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1323036221 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1323036221 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 80376534 # 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average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13843.498505 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 33071.428571 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 47875 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 38454.545455 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31253.922197 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 30551.263373 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 30901.969733 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29723.875825 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 29084.260048 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 29403.658346 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 88263884 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 112957 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3497847 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 1120 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 25.233775 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 100.854464 # average number of cycles each access was blocked +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.079468 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.079287 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.079379 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.083177 # 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number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 31637 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 35737 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 49619026500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 49901360000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 99520386500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 51614124513 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 50207961574 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 101822086087 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14084347500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 11245248000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 25329595500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 22590719708 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 29035857698 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 51626577406 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1881542500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1747721000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3629263500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 77000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 189500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 266500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 101233151013 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 100109321574 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 201342472587 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115317498513 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 111354569574 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 226672068087 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3087653000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3143213500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6230866500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2916803000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3290991498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6207794498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6004456000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6434204998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12438660998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033106 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032843 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032976 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014576 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014729 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014651 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.745059 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.750266 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.747569 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.759594 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.813594 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787264 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062236 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058391 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060327 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000003 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023996 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025001 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.024489 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027766 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028858 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028301 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17080.614946 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17908.550556 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17496.587984 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47385.337906 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45276.574241 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46339.777521 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20468.077112 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19212.786721 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19844.972410 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 71240.963466 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 74663.612573 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 73006.154288 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14301.002634 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14728.719703 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14504.806079 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 32071.428571 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 46875 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 37454.545455 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25508.166873 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25375.112123 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25441.559328 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24801.130810 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24523.114346 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24662.118444 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 181695.610624 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187690.734738 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184990.143396 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 188083.171206 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181333.479619 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184216.104068 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184805.022831 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 184445.117037 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184603.031833 # average overall mshr uncacheable latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024528 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024513 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024521 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028440 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028265 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028354 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17353.927566 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17886.272928 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17616.834367 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47572.682423 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47135.880559 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47356.290457 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21536.193491 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18340.035847 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19989.610840 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 39015.237232 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44550.264590 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 41946.295275 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14451.060284 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14509.206681 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14479.003180 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12833.333333 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 47375 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26650 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25666.385159 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25968.021990 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25815.480762 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25078.960317 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24921.276744 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25001.248351 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185947.184583 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184104.346043 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185012.960983 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 194039.582225 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176328.305722 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184229.418863 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189792.205329 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 180043.232448 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184621.085255 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 16002915 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.921323 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 168727471 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 16003427 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.543209 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 23708267500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 280.765706 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 231.155617 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.548371 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.451476 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999846 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 16001570 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.932596 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 169345332 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 16002082 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.582706 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 19421691500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 277.339337 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 234.593260 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.541678 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.458190 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 79 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 201964404 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 201964404 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 85532749 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 83194722 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 168727471 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 85532749 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 83194722 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 168727471 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 85532749 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 83194722 # number of overall hits -system.cpu0.icache.overall_hits::total 168727471 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 8694942 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 8538418 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 17233360 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 8694942 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 8538418 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 17233360 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 8694942 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 8538418 # number of overall misses -system.cpu0.icache.overall_misses::total 17233360 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 116564920862 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 116224713334 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 232789634196 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 116564920862 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 116224713334 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 232789634196 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 116564920862 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 116224713334 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 232789634196 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 94227691 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 91733140 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 185960831 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 94227691 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 91733140 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 185960831 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 94227691 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 91733140 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 185960831 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.092276 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.093079 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.092672 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.092276 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.093079 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.092672 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.092276 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.093079 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.092672 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13406.060772 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13611.972772 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13508.081662 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13406.060772 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13611.972772 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13508.081662 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13406.060772 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13611.972772 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13508.081662 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 124982 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 202579626 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 202579626 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 85484031 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 83861301 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 169345332 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 85484031 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 83861301 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 169345332 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 85484031 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 83861301 # number of overall hits +system.cpu0.icache.overall_hits::total 169345332 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 8738579 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 8493502 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 17232081 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 8738579 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 8493502 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 17232081 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 8738579 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 8493502 # number of overall misses +system.cpu0.icache.overall_misses::total 17232081 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 117560688351 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 115310089841 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 232870778192 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 117560688351 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 115310089841 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 232870778192 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 117560688351 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 115310089841 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 232870778192 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 94222610 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 92354803 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 186577413 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 94222610 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 92354803 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 186577413 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 94222610 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 92354803 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 186577413 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.092744 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.091966 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.092359 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.092744 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.091966 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.092359 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.092744 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.091966 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.092359 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13453.066952 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13576.271583 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13513.793151 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13453.066952 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13576.271583 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13513.793151 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13453.066952 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13576.271583 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13513.793151 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 123875 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 8393 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 8516 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.891219 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.546148 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 16002915 # number of writebacks -system.cpu0.icache.writebacks::total 16002915 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 618920 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 610867 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 1229787 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 618920 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 610867 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 1229787 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 618920 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 610867 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 1229787 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8076022 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 7927551 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 16003573 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 8076022 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 7927551 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 16003573 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 8076022 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 7927551 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 16003573 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 16001570 # number of writebacks +system.cpu0.icache.writebacks::total 16001570 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 623725 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 606143 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 1229868 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 623725 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 606143 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 1229868 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 623725 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 606143 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 1229868 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8114854 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 7887359 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 16002213 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 8114854 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 7887359 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 16002213 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 8114854 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 7887359 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 16002213 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 13120 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 7526 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 20646 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 13120 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 7526 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 20646 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 102996587403 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 102473648883 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 205470236286 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 102996587403 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 102473648883 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 205470236286 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 102996587403 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 102473648883 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 205470236286 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 103804344898 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 101735391889 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 205539736787 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 103804344898 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 101735391889 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 205539736787 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 103804344898 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 101735391889 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 205539736787 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1675493000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 960890000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2636383000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1675493000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 960890000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 2636383000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085708 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.086420 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086059 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085708 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.086420 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.086059 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085708 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.086420 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.086059 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12753.381232 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12926.268009 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12839.022654 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12753.381232 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12926.268009 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12839.022654 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12753.381232 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12926.268009 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12839.022654 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086124 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.085403 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085767 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086124 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.085403 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.085767 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086124 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.085403 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.085767 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12791.893101 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12898.536999 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12844.457000 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12791.893101 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12898.536999 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12844.457000 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12791.893101 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12898.536999 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12844.457000 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127694.613969 # average ReadReq mshr uncacheable latency @@ -1363,15 +1343,15 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127694.613969 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 128216560 # Number of BP lookups -system.cpu1.branchPred.condPredicted 87052179 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5647036 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 87531901 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 62765206 # Number of BTB hits +system.cpu1.branchPred.lookups 129319671 # Number of BP lookups +system.cpu1.branchPred.condPredicted 87966891 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5641555 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 87944289 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 63362458 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 71.705521 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16746465 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 188086 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.048406 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16739508 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 187311 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1401,90 +1381,89 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 886664 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 886664 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 16465 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 89324 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 548056 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 338608 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2680.249728 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 15884.122714 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 335881 99.19% 99.19% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1416 0.42% 99.61% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 912 0.27% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 152 0.04% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 149 0.04% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 41 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 27 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-524287 24 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 338608 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 414311 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23113.131199 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18566.304673 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 20214.309005 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 405108 97.78% 97.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 6775 1.64% 99.41% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1700 0.41% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 115 0.03% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 357 0.09% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 138 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 86 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 23 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 414311 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 341299530060 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.159336 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.721695 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-3 340284229060 99.70% 99.70% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-7 551479000 0.16% 99.86% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-11 203508500 0.06% 99.92% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-15 121654000 0.04% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-19 47328500 0.01% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-23 25233500 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-27 25945000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-31 34128500 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::32-35 5458500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::36-39 539500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::40-43 14000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::44-47 6000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::48-51 6000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 341299530060 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 89325 84.44% 84.44% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 16465 15.56% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 105790 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 886664 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 895803 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 895803 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 16863 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 90438 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 556335 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 339468 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2716.724404 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 17179.301997 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-131071 338161 99.61% 99.61% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-262143 1033 0.30% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-393215 187 0.06% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-524287 66 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-655359 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::655360-786431 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::786432-917503 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::917504-1.04858e+06 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::1.04858e+06-1.17965e+06 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 339468 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 421969 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23447.781709 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18889.456511 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 20397.447622 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 412488 97.75% 97.75% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 6847 1.62% 99.38% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1883 0.45% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 119 0.03% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 376 0.09% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 119 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 93 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 24 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 15 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 421969 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 329421639756 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.099906 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.712348 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-3 328385721256 99.69% 99.69% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-7 558806000 0.17% 99.86% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-11 205948500 0.06% 99.92% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-15 123798000 0.04% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-19 49482000 0.02% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-23 27267000 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-27 29508000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-31 34215500 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::32-35 6315000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::36-39 466000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::40-43 60500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::44-47 19000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::48-51 33000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 329421639756 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 90439 84.28% 84.28% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 16863 15.72% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 107302 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 895803 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 886664 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105790 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 895803 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 107302 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105790 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 992454 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 107302 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 1003105 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 101829672 # DTB read hits -system.cpu1.dtb.read_misses 610637 # DTB read misses -system.cpu1.dtb.write_hits 78493819 # DTB write hits -system.cpu1.dtb.write_misses 276027 # DTB write misses -system.cpu1.dtb.flush_tlb 1099 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 102542814 # DTB read hits +system.cpu1.dtb.read_misses 610673 # DTB read misses +system.cpu1.dtb.write_hits 79662745 # DTB write hits +system.cpu1.dtb.write_misses 285130 # DTB write misses +system.cpu1.dtb.flush_tlb 1093 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 21345 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 494 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 53264 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 214 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 9173 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 21297 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 513 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 54160 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 170 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 9133 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 54344 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 102440309 # DTB read accesses -system.cpu1.dtb.write_accesses 78769846 # DTB write accesses +system.cpu1.dtb.perms_faults 55274 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 103153487 # DTB read accesses +system.cpu1.dtb.write_accesses 79947875 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 180323491 # DTB hits -system.cpu1.dtb.misses 886664 # DTB misses -system.cpu1.dtb.accesses 181210155 # DTB accesses +system.cpu1.dtb.hits 182205559 # DTB hits +system.cpu1.dtb.misses 895803 # DTB misses +system.cpu1.dtb.accesses 183101362 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1514,381 +1493,383 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 102782 # Table walker walks requested -system.cpu1.itb.walker.walksLong 102782 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 2883 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 68745 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 14394 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 88388 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1935.822736 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 12537.694172 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-65535 87864 99.41% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-131071 223 0.25% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-196607 254 0.29% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-262143 26 0.03% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-327679 12 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-393215 6 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 104787 # Table walker walks requested +system.cpu1.itb.walker.walksLong 104787 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 2997 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 70975 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 14401 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 90386 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1987.890824 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 12865.387454 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-65535 89845 99.40% 99.40% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-131071 221 0.24% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-196607 266 0.29% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-262143 26 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-327679 17 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-393215 7 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 88388 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 86022 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 29627.804515 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24484.599023 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 24553.065811 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 83801 97.42% 97.42% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 633 0.74% 98.15% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 1356 1.58% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 58 0.07% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 124 0.14% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 30 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 13 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 86022 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 285462324712 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 1.863931 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -246539938456 -86.37% -86.37% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 531932332168 186.34% 99.98% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 61889000 0.02% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 6735500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 960500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 221000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::6 125000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 285462324712 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 68745 95.98% 95.98% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 2883 4.02% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 71628 # Table walker page sizes translated +system.cpu1.itb.walker.walkWaitTime::total 90386 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 88373 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 30169.316420 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 25114.673173 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 23994.465704 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 86083 97.41% 97.41% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 728 0.82% 98.23% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 1319 1.49% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 85 0.10% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 120 0.14% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 18 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 16 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 88373 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 612887048792 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.894295 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.308036 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 64872157396 10.58% 10.58% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 547942164396 89.40% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 62720500 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 7937000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 1056500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 430500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::6 357000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::7 15000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::8 210500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 612887048792 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 70975 95.95% 95.95% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 2997 4.05% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 73972 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 102782 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 102782 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 104787 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 104787 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 71628 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 71628 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 174410 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 91967963 # ITB inst hits -system.cpu1.itb.inst_misses 102782 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 73972 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 73972 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 178759 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 92590548 # ITB inst hits +system.cpu1.itb.inst_misses 104787 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1099 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1093 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 21345 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 494 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 39701 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 21297 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 513 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 40602 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 205263 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 205634 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 92070745 # ITB inst accesses -system.cpu1.itb.hits 91967963 # DTB hits -system.cpu1.itb.misses 102782 # DTB misses -system.cpu1.itb.accesses 92070745 # DTB accesses -system.cpu1.numCycles 688789566 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 92695335 # ITB inst accesses +system.cpu1.itb.hits 92590548 # DTB hits +system.cpu1.itb.misses 104787 # DTB misses +system.cpu1.itb.accesses 92695335 # DTB accesses +system.cpu1.numCycles 681850895 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 239433402 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 569353182 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 128216560 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 79511671 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 405943168 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 12894098 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2616962 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 25257 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 5725 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 5490519 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 162267 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 4008 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 91740705 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 3476633 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 41341 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 660128083 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.009568 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.262441 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 239388954 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 575024708 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 129319671 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 80101966 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 399222814 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 12867675 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2725843 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 25092 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 3697 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 5482930 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 182777 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 3937 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 92362358 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 3459969 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 41770 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 653469609 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.029599 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.281240 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 519338149 78.67% 78.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 17657421 2.67% 81.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 17720975 2.68% 84.03% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 13023211 1.97% 86.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 27851950 4.22% 90.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 8753673 1.33% 91.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 9450814 1.43% 92.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 8261049 1.25% 94.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 38070841 5.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 511473047 78.27% 78.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 17746068 2.72% 80.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 17876069 2.74% 83.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13147863 2.01% 85.73% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 28062649 4.29% 90.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 8778442 1.34% 91.37% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 9526239 1.46% 92.83% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 8304050 1.27% 94.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 38555182 5.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 660128083 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.186148 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.826600 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 194262443 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 345472686 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 102025852 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 13293227 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5071579 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 19043746 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1394530 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 620472933 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 4297557 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5071579 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 201685746 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 31240093 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 261429717 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 107754222 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 52944105 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 605820743 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 130951 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 2142931 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 2140614 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 33385135 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 3753 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 580698698 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 936110112 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 716711881 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 767618 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 488837378 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 91861315 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 14967870 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13038182 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 74719709 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 97839319 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 82555667 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 13435403 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 14269542 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 574617477 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15094560 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 575613551 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 822312 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 77207090 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 49700091 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 361677 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 660128083 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.871973 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.612023 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 653469609 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.189660 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.843329 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 194540645 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 337340525 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 103135857 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 13376974 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5073310 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 19204285 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1379859 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 627304700 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 4258915 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5073310 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 201998899 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 27311844 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 261169019 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 108909949 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 49003878 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 612618911 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 137031 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1952354 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 1962506 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 29516744 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 3823 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 587164162 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 946758307 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 724795926 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 781641 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 494885886 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 92278271 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15082252 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13144529 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 75005032 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 98707880 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 83757072 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 13358555 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 14229040 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 581184996 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15164742 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 582092616 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 825653 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 77569161 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 49788978 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 351791 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 653469609 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.890772 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.626680 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 433148093 65.62% 65.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 96441838 14.61% 80.23% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 42095455 6.38% 86.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 30017553 4.55% 91.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 22180461 3.36% 94.51% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 15486932 2.35% 96.86% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 10578992 1.60% 98.46% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 6132384 0.93% 99.39% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 4046375 0.61% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 424481416 64.96% 64.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 97055692 14.85% 79.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 42445288 6.50% 86.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 30251514 4.63% 90.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 22439866 3.43% 94.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 15693652 2.40% 96.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 10715111 1.64% 98.41% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 6223144 0.95% 99.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 4163926 0.64% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 660128083 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 653469609 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2899692 25.45% 25.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 23212 0.20% 25.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 2493 0.02% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 1 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4727772 41.50% 67.18% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 3739545 32.82% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2929813 25.60% 25.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 22943 0.20% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 2467 0.02% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4683520 40.92% 66.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3806309 33.26% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 87 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 390631647 67.86% 67.86% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1449252 0.25% 68.12% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 67728 0.01% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 81 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 18 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 4 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 58665 0.01% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 103885376 18.05% 86.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 79520645 13.81% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 395178561 67.89% 67.89% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1472120 0.25% 68.14% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 66548 0.01% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 83 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 18 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 58655 0.01% 68.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.16% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 104607338 17.97% 86.13% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 80709157 13.87% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 575613551 # Type of FU issued -system.cpu1.iq.rate 0.835689 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 11392715 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019792 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1822546817 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 667071123 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 554642407 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1023395 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 508279 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 454369 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 586459289 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 546890 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 4569014 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 582092616 # Type of FU issued +system.cpu1.iq.rate 0.853695 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 11445052 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019662 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1828886082 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 674065927 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 561183745 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1039464 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 516201 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 461714 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 592981793 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 555788 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 4619757 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 15724428 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 20010 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 670978 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 8558712 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 15740565 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 19881 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 674311 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 8622171 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 3761249 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 7804669 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 3783711 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 7638228 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5071579 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 16680640 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 12329901 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 589846063 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 1702837 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 97839319 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 82555667 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12741950 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 233925 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 12007104 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 670978 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2558274 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2229598 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4787872 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 569204299 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 101821264 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 5535672 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 5073310 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 16098431 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 8955476 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 596484662 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 1704911 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 98707880 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 83757072 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12853261 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 236300 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 8632331 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 674311 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2559005 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2239379 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4798384 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 575610941 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 102532690 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 5599160 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 134026 # number of nop insts executed -system.cpu1.iew.exec_refs 180319145 # number of memory reference insts executed -system.cpu1.iew.exec_branches 105773243 # Number of branches executed -system.cpu1.iew.exec_stores 78497881 # Number of stores executed -system.cpu1.iew.exec_rate 0.826383 # Inst execution rate -system.cpu1.iew.wb_sent 556304876 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 555096776 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 274163162 # num instructions producing a value -system.cpu1.iew.wb_consumers 476408431 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.805902 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.575479 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 77255744 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14732883 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4271292 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 646929445 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.792211 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.788945 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 134924 # number of nop insts executed +system.cpu1.iew.exec_refs 182199156 # number of memory reference insts executed +system.cpu1.iew.exec_branches 106955524 # Number of branches executed +system.cpu1.iew.exec_stores 79666466 # Number of stores executed +system.cpu1.iew.exec_rate 0.844189 # Inst execution rate +system.cpu1.iew.wb_sent 562846195 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 561645459 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 277406088 # num instructions producing a value +system.cpu1.iew.wb_consumers 482095859 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.823707 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.575417 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 77620005 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14812951 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4280755 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 640233275 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.810299 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.807739 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 457763793 70.76% 70.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 93973346 14.53% 85.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 32152826 4.97% 90.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 14713797 2.27% 92.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 10604817 1.64% 94.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 6244010 0.97% 95.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5818154 0.90% 96.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3733305 0.58% 96.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 21925397 3.39% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 449273024 70.17% 70.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 94745433 14.80% 84.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 32328499 5.05% 90.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 14864939 2.32% 92.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 10716802 1.67% 94.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 6304065 0.98% 95.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5887950 0.92% 95.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3832413 0.60% 96.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 22280150 3.48% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 646929445 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 436316971 # Number of instructions committed -system.cpu1.commit.committedOps 512504942 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 640233275 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 441802027 # Number of instructions committed +system.cpu1.commit.committedOps 518780572 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 156111845 # Number of memory references committed -system.cpu1.commit.loads 82114890 # Number of loads committed -system.cpu1.commit.membars 3660763 # Number of memory barriers committed -system.cpu1.commit.branches 97634182 # Number of branches committed -system.cpu1.commit.fp_insts 435169 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 470255893 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12926033 # Number of function calls committed. +system.cpu1.commit.refs 158102215 # Number of memory references committed +system.cpu1.commit.loads 82967314 # Number of loads committed +system.cpu1.commit.membars 3638779 # Number of memory barriers committed +system.cpu1.commit.branches 98771468 # Number of branches committed +system.cpu1.commit.fp_insts 442327 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 475908422 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12958317 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 355174724 69.30% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1118155 0.22% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 50641 0.01% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 49535 0.01% 69.54% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 82114890 16.02% 85.56% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 73996955 14.44% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 359445517 69.29% 69.29% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1133059 0.22% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 49873 0.01% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 49866 0.01% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 82967314 15.99% 85.52% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 75134901 14.48% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 512504942 # Class of committed instruction -system.cpu1.commit.bw_lim_events 21925397 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1210740079 # The number of ROB reads -system.cpu1.rob.rob_writes 1192741700 # The number of ROB writes -system.cpu1.timesIdled 4053845 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 28661483 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 52418384154 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 436316971 # Number of Instructions Simulated -system.cpu1.committedOps 512504942 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.578645 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.578645 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.633455 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.633455 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 671693836 # number of integer regfile reads -system.cpu1.int_regfile_writes 396256302 # number of integer regfile writes -system.cpu1.fp_regfile_reads 829382 # number of floating regfile reads -system.cpu1.fp_regfile_writes 475398 # number of floating regfile writes -system.cpu1.cc_regfile_reads 122695419 # number of cc regfile reads -system.cpu1.cc_regfile_writes 123792123 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1193620211 # number of misc regfile reads -system.cpu1.misc_regfile_writes 14812328 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40298 # Transaction distribution -system.iobus.trans_dist::ReadResp 40298 # Transaction distribution +system.cpu1.commit.op_class_0::total 518780572 # Class of committed instruction +system.cpu1.commit.bw_lim_events 22280150 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1210397617 # The number of ROB reads +system.cpu1.rob.rob_writes 1206057669 # The number of ROB writes +system.cpu1.timesIdled 4036845 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 28381286 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 48640587426 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 441802027 # Number of Instructions Simulated +system.cpu1.committedOps 518780572 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.543340 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.543340 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.647945 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.647945 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 679308932 # number of integer regfile reads +system.cpu1.int_regfile_writes 400707036 # number of integer regfile writes +system.cpu1.fp_regfile_reads 840716 # number of floating regfile reads +system.cpu1.fp_regfile_writes 480942 # number of floating regfile writes +system.cpu1.cc_regfile_reads 124429179 # number of cc regfile reads +system.cpu1.cc_regfile_writes 125518608 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1192080281 # number of misc regfile reads +system.cpu1.misc_regfile_writes 14931224 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40297 # Transaction distribution +system.iobus.trans_dist::ReadResp 40297 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1905,11 +1886,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353738 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353736 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1924,100 +1905,100 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492168 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 47816000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 47817000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 344500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 346500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25477500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25488000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 40153500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 40144000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 567153724 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 567038102 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147714000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147712000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115458 # number of replacements -system.iocache.tags.tagsinuse 10.431703 # Cycle average of tags in use +system.iocache.tags.replacements 115457 # number of replacements +system.iocache.tags.tagsinuse 10.419652 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13100979259000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.538083 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.893621 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221130 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.430851 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651981 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13096643979000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.546599 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.873052 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221662 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429566 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651228 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039650 # Number of tag accesses -system.iocache.tags.data_accesses 1039650 # Number of data accesses +system.iocache.tags.tag_accesses 1039641 # Number of tag accesses +system.iocache.tags.data_accesses 1039641 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # 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number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1695101545 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1700187545 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13410969438 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13410969438 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13413700557 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13413700557 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1703214286 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1708651286 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1695101545 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1700538545 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1703214286 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1708651286 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1695101545 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1700538545 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8812 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8852 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8812 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8852 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2032,54 +2013,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 193261.577896 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 193028.280904 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 192362.862574 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 192133.296983 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125730.981756 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125730.981756 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125756.586637 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125756.586637 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 193261.577896 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 193002.517339 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 192362.862574 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 192107.833823 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 193261.577896 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 193002.517339 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 35415 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 192362.862574 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 192107.833823 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34986 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3508 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3448 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.095496 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.146752 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8813 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8850 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8812 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8849 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8813 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8853 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8812 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8852 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8813 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8853 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8812 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8852 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1262564286 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1265800286 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1254501545 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1257737545 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8072705642 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8072705642 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8075439072 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8075439072 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1262564286 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1266001286 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1254501545 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1257938545 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1262564286 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1266001286 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1254501545 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1257938545 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2094,311 +2075,308 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 143261.577896 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 143028.280904 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142362.862574 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 142133.296983 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75683.507481 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75683.507481 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75709.134028 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75709.134028 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 143261.577896 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 143002.517339 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 142362.862574 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 142107.833823 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 143261.577896 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 143002.517339 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 142362.862574 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 142107.833823 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1326374 # number of replacements -system.l2c.tags.tagsinuse 65265.362084 # Cycle average of tags in use -system.l2c.tags.total_refs 49524083 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1389631 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 35.638298 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 22398666000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 35423.869586 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 183.395025 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 263.757590 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3339.523943 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 11653.727077 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 182.196722 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 269.878356 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3963.200555 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 9985.813228 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.540525 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002798 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.004025 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.050957 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.177822 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002780 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.004118 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.060474 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.152371 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995870 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 308 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62949 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 307 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 578 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2748 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5097 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54406 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.960526 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 439713882 # Number of tag accesses -system.l2c.tags.data_accesses 439713882 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 520227 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 197797 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 519049 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 183181 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1420254 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 8006090 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 8006090 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 15999481 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 15999481 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 4949 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4988 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9937 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits +system.l2c.tags.replacements 1354167 # number of replacements +system.l2c.tags.tagsinuse 65271.664072 # Cycle average of tags in use +system.l2c.tags.total_refs 49616884 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1417173 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 35.011169 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 4319323500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 35375.234634 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 164.760345 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 244.127977 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3171.033439 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 12870.716892 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 164.761556 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 248.464431 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4106.850597 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 8925.714203 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.539783 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002514 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003725 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.048386 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.196392 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002514 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136392.628753 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129415.741218 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 129146.950940 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125970.169055 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136020.568810 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 135062.582465 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 140399.686068 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 140587.494768 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 140492.034327 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125396.222462 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125800.991927 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125610.150396 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 131638.003599 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130023.737927 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130850.066868 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69900.433281 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69835.019825 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69862.657544 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128330.319506 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 127766.062776 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125396.222462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 137136.143903 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 128202.542523 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 129077.852796 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125800.991927 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136688.281844 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 135703.488356 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128330.319506 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 127766.062776 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125396.222462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 137136.143903 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 128202.542523 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 129077.852796 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125800.991927 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136688.281844 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 135703.488356 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169190.865353 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173442.788317 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175186.169638 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149571.674391 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 176579.940245 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169749.909256 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172666.844654 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171599.455280 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149583.710662 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182535.258116 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 164742.686455 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172680.065883 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 172787.806528 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 177762.983216 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 172410.754370 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 158412.999228 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 168018.440272 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 158425.505544 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 54329 # Transaction distribution -system.membus.trans_dist::ReadResp 466235 # Transaction distribution -system.membus.trans_dist::WriteReq 33699 # Transaction distribution -system.membus.trans_dist::WriteResp 33699 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1224424 # Transaction distribution -system.membus.trans_dist::CleanEvict 216307 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36790 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.membus.trans_dist::ReadReq 54324 # Transaction distribution +system.membus.trans_dist::ReadResp 474547 # Transaction distribution +system.membus.trans_dist::WriteReq 33696 # Transaction distribution +system.membus.trans_dist::WriteResp 33696 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1247532 # Transaction distribution +system.membus.trans_dist::CleanEvict 221010 # Transaction distribution +system.membus.trans_dist::UpgradeReq 37031 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 1016209 # Transaction distribution -system.membus.trans_dist::ReadExResp 1016209 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 411906 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution +system.membus.trans_dist::ReadExReq 523357 # Transaction distribution +system.membus.trans_dist::ReadExResp 523357 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 420223 # Transaction distribution +system.membus.trans_dist::InvalidateReq 618325 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6874 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4246337 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4375991 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237825 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237825 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4613816 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3816979 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3946617 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237606 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237606 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4184223 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13748 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 163669548 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 163841278 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7262720 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7262720 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 171103998 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2667 # Total snoops (count) -system.membus.snoop_fanout::samples 3100373 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 134138156 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 134309854 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7248832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7248832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 141558686 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2885 # Total snoops (count) +system.membus.snoop_fanout::samples 3155536 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3100373 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3155536 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3100373 # Request fanout histogram -system.membus.reqLayer0.occupancy 113885000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3155536 # Request fanout histogram +system.membus.reqLayer0.occupancy 113887000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 50156 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5470002 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5512000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8294790249 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8359087618 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7676329675 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5141778971 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44628309 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44612371 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2711,11 +2685,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -2748,64 +2722,64 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 53748943 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 27300315 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 4554 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2137 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2137 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 53860854 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 27356918 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 4389 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2115 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2115 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 2032183 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 25147760 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33699 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33699 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 9230552 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 16002915 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2655847 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 45875 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 45886 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2102499 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2102499 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 16003573 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 7120105 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1337967 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1231303 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 48051162 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31561925 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 916568 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2490426 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 83020081 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2049724352 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1102308286 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3082904 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8350216 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3163465758 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2107044 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 30117798 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.027021 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.162144 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2036938 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 25194555 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 9275862 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 16001570 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2694937 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 46206 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 46216 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2116229 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2116229 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 16002213 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 7163507 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1337442 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1230778 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 48047123 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31732395 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 915561 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2519584 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 83214663 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2049552896 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1107385822 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3096672 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8523576 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3168558966 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2116170 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 30205961 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.026968 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.161993 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 29303991 97.30% 97.30% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 813807 2.70% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 29391361 97.30% 97.30% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 814592 2.70% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 8 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 30117798 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 51529807954 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 30205961 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 51608527894 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1428891 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1422395 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 24051879645 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 24050258287 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 14516066687 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 14601873318 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 531626613 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 528950493 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1449630863 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1457147305 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16333 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 16352 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt index d09bb714e..8a6768cf2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -1,158 +1,158 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.771727 # Number of seconds simulated -sim_ticks 51771726701500 # Number of ticks simulated -final_tick 51771726701500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.799232 # Number of seconds simulated +sim_ticks 51799232151500 # Number of ticks simulated +final_tick 51799232151500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 821234 # Simulator instruction rate (inst/s) -host_op_rate 965096 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51452236494 # Simulator tick rate (ticks/s) -host_mem_usage 677452 # Number of bytes of host memory used -host_seconds 1006.21 # Real time elapsed on the host -sim_insts 826333887 # Number of instructions simulated -sim_ops 971088679 # Number of ops (including micro ops) simulated +host_inst_rate 1085172 # Simulator instruction rate (inst/s) +host_op_rate 1275227 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67259328222 # Simulator tick rate (ticks/s) +host_mem_usage 678040 # Number of bytes of host memory used +host_seconds 770.14 # Real time elapsed on the host +sim_insts 835736802 # Number of instructions simulated +sim_ops 982105580 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 69952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 75072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2290776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 31969648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 59200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 65024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2387996 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 32286808 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 387264 # Number of bytes read from this memory -system.physmem.bytes_read::total 69591740 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2290776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2387996 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4678772 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 60611648 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 74880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 80448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2375384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 17755184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 76352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 77888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2376540 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 17975768 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 395840 # Number of bytes read from this memory +system.physmem.bytes_read::total 41188284 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2375384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2376540 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 4751924 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 62641792 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 15860 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4720 # Number of bytes written to this memory -system.physmem.bytes_written::total 60632228 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1093 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1173 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 56454 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 499529 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 925 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1016 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 57059 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 504491 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6051 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1127791 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 947057 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 62662372 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1170 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1257 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 57776 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 277428 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1193 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1217 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56880 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 280881 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6185 # Number of read requests responded to by this memory +system.physmem.num_reads::total 683987 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 978778 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 1983 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 590 # Number of write requests responded to by this memory -system.physmem.num_writes::total 949630 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1450 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 44248 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 617512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1143 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 46125 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 623638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7480 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1344204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 44248 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 46125 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 90373 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1170748 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 981351 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1446 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 45858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 342769 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 45880 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 347028 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 795152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 45858 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 45880 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 91737 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1209319 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 306 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 91 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1171146 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1170748 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1450 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 44248 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 617818 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1143 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 46125 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 623729 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2515349 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1127791 # Number of read requests accepted -system.physmem.writeReqs 949630 # Number of write requests accepted -system.physmem.readBursts 1127791 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 949630 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 72133184 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 45440 # Total number of bytes read from write queue -system.physmem.bytesWritten 60631936 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 69591740 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 60632228 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 710 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2256 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1209716 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1209319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1446 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 45858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 343075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 45880 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 347119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2004869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 683987 # Number of read requests accepted +system.physmem.writeReqs 981351 # Number of write requests accepted +system.physmem.readBursts 683987 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 981351 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 43730304 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 44864 # Total number of bytes read from write queue +system.physmem.bytesWritten 62662336 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 41188284 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 62662372 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 701 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 72704 # Per bank write bursts -system.physmem.perBankRdBursts::1 73689 # Per bank write bursts -system.physmem.perBankRdBursts::2 70161 # Per bank write bursts -system.physmem.perBankRdBursts::3 65996 # Per bank write bursts -system.physmem.perBankRdBursts::4 66834 # Per bank write bursts -system.physmem.perBankRdBursts::5 71242 # Per bank write bursts -system.physmem.perBankRdBursts::6 65196 # Per bank write bursts -system.physmem.perBankRdBursts::7 62079 # Per bank write bursts -system.physmem.perBankRdBursts::8 64428 # Per bank write bursts -system.physmem.perBankRdBursts::9 108710 # Per bank write bursts -system.physmem.perBankRdBursts::10 67339 # Per bank write bursts -system.physmem.perBankRdBursts::11 66743 # Per bank write bursts -system.physmem.perBankRdBursts::12 64268 # Per bank write bursts -system.physmem.perBankRdBursts::13 71345 # Per bank write bursts -system.physmem.perBankRdBursts::14 65944 # Per bank write bursts -system.physmem.perBankRdBursts::15 70403 # Per bank write bursts -system.physmem.perBankWrBursts::0 59852 # Per bank write bursts -system.physmem.perBankWrBursts::1 61594 # Per bank write bursts -system.physmem.perBankWrBursts::2 59825 # Per bank write bursts -system.physmem.perBankWrBursts::3 58084 # Per bank write bursts -system.physmem.perBankWrBursts::4 58217 # Per bank write bursts -system.physmem.perBankWrBursts::5 60425 # Per bank write bursts -system.physmem.perBankWrBursts::6 57000 # Per bank write bursts -system.physmem.perBankWrBursts::7 56382 # Per bank write bursts -system.physmem.perBankWrBursts::8 57853 # Per bank write bursts -system.physmem.perBankWrBursts::9 59874 # Per bank write bursts -system.physmem.perBankWrBursts::10 59285 # Per bank write bursts -system.physmem.perBankWrBursts::11 60081 # Per bank write bursts -system.physmem.perBankWrBursts::12 57131 # Per bank write bursts -system.physmem.perBankWrBursts::13 62251 # Per bank write bursts -system.physmem.perBankWrBursts::14 58136 # Per bank write bursts -system.physmem.perBankWrBursts::15 61384 # Per bank write bursts +system.physmem.perBankRdBursts::0 41322 # Per bank write bursts +system.physmem.perBankRdBursts::1 41177 # Per bank write bursts +system.physmem.perBankRdBursts::2 39218 # Per bank write bursts +system.physmem.perBankRdBursts::3 39952 # Per bank write bursts +system.physmem.perBankRdBursts::4 41092 # Per bank write bursts +system.physmem.perBankRdBursts::5 49504 # Per bank write bursts +system.physmem.perBankRdBursts::6 36877 # Per bank write bursts +system.physmem.perBankRdBursts::7 36988 # Per bank write bursts +system.physmem.perBankRdBursts::8 38459 # Per bank write bursts +system.physmem.perBankRdBursts::9 81977 # Per bank write bursts +system.physmem.perBankRdBursts::10 39138 # Per bank write bursts +system.physmem.perBankRdBursts::11 41925 # Per bank write bursts +system.physmem.perBankRdBursts::12 38445 # Per bank write bursts +system.physmem.perBankRdBursts::13 41518 # Per bank write bursts +system.physmem.perBankRdBursts::14 36799 # Per bank write bursts +system.physmem.perBankRdBursts::15 38895 # Per bank write bursts +system.physmem.perBankWrBursts::0 61042 # Per bank write bursts +system.physmem.perBankWrBursts::1 63110 # Per bank write bursts +system.physmem.perBankWrBursts::2 61459 # Per bank write bursts +system.physmem.perBankWrBursts::3 62355 # Per bank write bursts +system.physmem.perBankWrBursts::4 60847 # Per bank write bursts +system.physmem.perBankWrBursts::5 67831 # Per bank write bursts +system.physmem.perBankWrBursts::6 59687 # Per bank write bursts +system.physmem.perBankWrBursts::7 59677 # Per bank write bursts +system.physmem.perBankWrBursts::8 60696 # Per bank write bursts +system.physmem.perBankWrBursts::9 62695 # Per bank write bursts +system.physmem.perBankWrBursts::10 60108 # Per bank write bursts +system.physmem.perBankWrBursts::11 60915 # Per bank write bursts +system.physmem.perBankWrBursts::12 59030 # Per bank write bursts +system.physmem.perBankWrBursts::13 62102 # Per bank write bursts +system.physmem.perBankWrBursts::14 56975 # Per bank write bursts +system.physmem.perBankWrBursts::15 60570 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 47 # Number of times write queue was full causing retry -system.physmem.totGap 51771723764500 # Total gap between requests +system.physmem.numWrRetry 35 # Number of times write queue was full causing retry +system.physmem.totGap 51799229214500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1084675 # Read request sizes (log2) +system.physmem.readPktSize::6 640871 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 947057 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1101525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 20079 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 446 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 533 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 506 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1087 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 624 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 48 # What read queue length does an incoming req see +system.physmem.writePktSize::6 978778 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 654776 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 22950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 447 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 529 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 667 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 289 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 342 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -165,187 +165,188 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 13771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 18027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 54758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 54058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 55508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 54068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 53991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 55072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 55232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 54714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 55832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 58265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 55672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 55559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 58031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 54737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 53792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 53604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 143 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 442864 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 299.787276 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.663870 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.837689 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 176801 39.92% 39.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 107708 24.32% 64.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 38340 8.66% 72.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22096 4.99% 77.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15589 3.52% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11707 2.64% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10190 2.30% 86.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8599 1.94% 88.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 51834 11.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 442864 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 52780 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.354225 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 295.252681 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 52773 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 3 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-8191 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 52780 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 52780 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.949488 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.151899 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.362849 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 96 0.18% 0.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 68 0.13% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 65 0.12% 0.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 113 0.21% 0.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 49413 93.62% 94.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 604 1.14% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 382 0.72% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 366 0.69% 96.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 106 0.20% 97.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 120 0.23% 97.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 251 0.48% 97.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 25 0.05% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 347 0.66% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 80 0.15% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 21 0.04% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 55 0.10% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 264 0.50% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 29 0.05% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 20 0.04% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 122 0.23% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 176 0.33% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 10 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 11 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 52780 # Writes before turning the bus around for reads -system.physmem.totQLat 13931485499 # Total ticks spent queuing -system.physmem.totMemAccLat 35064254249 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5635405000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12360.68 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 1596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1423 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 31896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 37595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 53715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 53386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 56244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 54082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 56988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 54298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 54807 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 89 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 437346 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 243.268076 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.507272 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 286.058540 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 195461 44.69% 44.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 115696 26.45% 71.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 38501 8.80% 79.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20148 4.61% 84.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13086 2.99% 87.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8742 2.00% 89.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7314 1.67% 91.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5744 1.31% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 32654 7.47% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 437346 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 51642 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 13.230801 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 107.035752 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 51638 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::17408-18431 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 51642 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 51642 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.959355 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.129785 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.514310 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 120 0.23% 0.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 58 0.11% 0.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 71 0.14% 0.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 110 0.21% 0.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 46610 90.26% 90.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 2201 4.26% 95.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 409 0.79% 96.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 381 0.74% 96.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 125 0.24% 96.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 97 0.19% 97.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 249 0.48% 97.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 37 0.07% 97.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 313 0.61% 98.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 78 0.15% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 24 0.05% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 64 0.12% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 317 0.61% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 20 0.04% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 23 0.04% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 120 0.23% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 150 0.29% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 3 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 12 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 17 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 51642 # Writes before turning the bus around for reads +system.physmem.totQLat 9080957107 # Total ticks spent queuing +system.physmem.totMemAccLat 21892569607 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3416430000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13290.13 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31110.68 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.39 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.34 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 32040.13 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.21 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.80 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.21 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.40 # Average write queue length when enqueuing -system.physmem.readRowHits 910554 # Number of row buffer hits during reads -system.physmem.writeRowHits 721036 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.79 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.11 # Row buffer hit rate for writes -system.physmem.avgGap 24921151.64 # Average gap between requests -system.physmem.pageHitRate 78.65 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1716089760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 936358500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4273627800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3054535920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3381477484320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1299156215670 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29923425135750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34614039447720 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.589631 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49779697907279 # Time in different power states -system.physmem_0.memoryStateTime::REF 1728771720000 # Time in different power states +system.physmem.avgWrQLen 11.30 # Average write queue length when enqueuing +system.physmem.readRowHits 503634 # Number of row buffer hits during reads +system.physmem.writeRowHits 721404 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.68 # Row buffer hit rate for writes +system.physmem.avgGap 31104333.90 # Average gap between requests +system.physmem.pageHitRate 73.69 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1696456440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 925645875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2543814000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3214131840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3383273718240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1286151175755 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29951333686500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34629138628650 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.526160 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49826371298908 # Time in different power states +system.physmem_0.memoryStateTime::REF 1729690040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 263256805221 # Time in different power states +system.physmem_0.memoryStateTime::ACT 243166128592 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1631962080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 890455500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4517588400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3084447600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3381477484320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1291204023120 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29930400751500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34613206712520 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.573546 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49791314720420 # Time in different power states -system.physmem_1.memoryStateTime::REF 1728771720000 # Time in different power states +system.physmem_1.actEnergy 1609879320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 878406375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2785777800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3130429680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3383273718240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1282982007105 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29954113659000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34628773877520 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.519119 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49831003018963 # Time in different power states +system.physmem_1.memoryStateTime::REF 1729690040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 251640005830 # Time in different power states +system.physmem_1.memoryStateTime::ACT 238538435537 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -399,69 +400,70 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 115485 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 115485 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17906 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 83637 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 11 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 115474 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.346398 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 89.645919 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 115472 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 118484 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 118484 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17724 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 86321 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 118475 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.236337 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 81.347587 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 118474 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 115474 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 101554 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 25029.885578 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21753.655577 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 15864.720522 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 100973 99.43% 99.43% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 8 0.01% 99.44% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 501 0.49% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 8 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 30 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 9 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 21 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkWaitTime::total 118475 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 104054 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 25330.679263 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21934.679716 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16178.136591 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 103422 99.39% 99.39% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1 0.00% 99.39% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 549 0.53% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 13 0.01% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 39 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 17 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 101554 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -3996350676 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.438404 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 104054 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -2515798788 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.690729 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 1752015204 -43.84% -43.84% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -5748365880 143.84% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -3996350676 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 83637 82.37% 82.37% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 17906 17.63% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 101543 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 115485 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walksPending::0 1737735704 -69.07% -69.07% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -4253534492 169.07% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -2515798788 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 86322 82.97% 82.97% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 17724 17.03% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 104046 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 118484 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 115485 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101543 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 118484 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 104046 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101543 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 217028 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 104046 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 222530 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 77968786 # DTB read hits -system.cpu0.dtb.read_misses 88587 # DTB read misses -system.cpu0.dtb.write_hits 70658355 # DTB write hits -system.cpu0.dtb.write_misses 26898 # DTB write misses -system.cpu0.dtb.flush_tlb 51778 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 78608030 # DTB read hits +system.cpu0.dtb.read_misses 90806 # DTB read misses +system.cpu0.dtb.write_hits 71283429 # DTB write hits +system.cpu0.dtb.write_misses 27678 # DTB write misses +system.cpu0.dtb.flush_tlb 51806 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 18574 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 509 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 67879 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 19521 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 503 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 69055 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4111 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4281 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9218 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 78057373 # DTB read accesses -system.cpu0.dtb.write_accesses 70685253 # DTB write accesses +system.cpu0.dtb.perms_faults 9631 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 78698836 # DTB read accesses +system.cpu0.dtb.write_accesses 71311107 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 148627141 # DTB hits -system.cpu0.dtb.misses 115485 # DTB misses -system.cpu0.dtb.accesses 148742626 # DTB accesses +system.cpu0.dtb.hits 149891459 # DTB hits +system.cpu0.dtb.misses 118484 # DTB misses +system.cpu0.dtb.accesses 150009943 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -491,281 +493,280 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 74042 # Table walker walks requested -system.cpu0.itb.walker.walksLong 74042 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4198 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 64736 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 74042 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 74042 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 74042 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 68934 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 28581.273392 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 25349.599489 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 19061.356835 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 68231 98.98% 98.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 3 0.00% 98.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 610 0.88% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 10 0.01% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 35 0.05% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 76645 # Table walker walks requested +system.cpu0.itb.walker.walksLong 76645 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4248 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 67077 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 76645 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 76645 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 76645 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 71325 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 28947.290571 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 25637.754479 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 19237.260354 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 70555 98.92% 98.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 2 0.00% 98.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 668 0.94% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 18 0.03% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 42 0.06% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::393216-458751 21 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 68934 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 71325 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 1705681704 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 1705681704 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 1705681704 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 64736 93.91% 93.91% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 4198 6.09% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 68934 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 67077 94.04% 94.04% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 4248 5.96% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 71325 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 74042 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 74042 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 76645 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 76645 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 68934 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 68934 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 142976 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 413989239 # ITB inst hits -system.cpu0.itb.inst_misses 74042 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 71325 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 71325 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 147970 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 417906874 # ITB inst hits +system.cpu0.itb.inst_misses 76645 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 51778 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 51806 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 18574 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 509 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 49997 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 19521 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 503 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 51690 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 414063281 # ITB inst accesses -system.cpu0.itb.hits 413989239 # DTB hits -system.cpu0.itb.misses 74042 # DTB misses -system.cpu0.itb.accesses 414063281 # DTB accesses -system.cpu0.numCycles 51772399583 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 417983519 # ITB inst accesses +system.cpu0.itb.hits 417906874 # DTB hits +system.cpu0.itb.misses 76645 # DTB misses +system.cpu0.itb.accesses 417983519 # DTB accesses +system.cpu0.numCycles 51800067955 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 15959 # number of quiesce instructions executed -system.cpu0.committedInsts 413737178 # Number of instructions committed -system.cpu0.committedOps 486128458 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 446921205 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 447031 # Number of float alu accesses -system.cpu0.num_func_calls 24805806 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 62762528 # number of instructions that are conditional controls -system.cpu0.num_int_insts 446921205 # number of integer instructions -system.cpu0.num_fp_insts 447031 # number of float instructions -system.cpu0.num_int_register_reads 646154735 # number of times the integer registers were read -system.cpu0.num_int_register_writes 354190798 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 724381 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 372700 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 107222136 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 106914913 # number of times the CC registers were written -system.cpu0.num_mem_refs 148617421 # number of memory refs -system.cpu0.num_load_insts 77964333 # Number of load instructions -system.cpu0.num_store_insts 70653088 # Number of store instructions -system.cpu0.num_idle_cycles 50228896973.724121 # Number of idle cycles -system.cpu0.num_busy_cycles 1543502609.275879 # Number of busy cycles -system.cpu0.not_idle_fraction 0.029813 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.970187 # Percentage of idle cycles -system.cpu0.Branches 92293251 # Number of branches fetched -system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 336607156 69.20% 69.20% # Class of executed instruction -system.cpu0.op_class::IntMult 1073484 0.22% 69.42% # Class of executed instruction -system.cpu0.op_class::IntDiv 49277 0.01% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 20 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 55202 0.01% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::MemRead 77964333 16.03% 85.47% # Class of executed instruction -system.cpu0.op_class::MemWrite 70653088 14.53% 100.00% # Class of executed instruction +system.cpu0.kern.inst.quiesce 16018 # number of quiesce instructions executed +system.cpu0.committedInsts 417645333 # Number of instructions committed +system.cpu0.committedOps 490761503 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 451046619 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 435772 # Number of float alu accesses +system.cpu0.num_func_calls 25047272 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 63386661 # number of instructions that are conditional controls +system.cpu0.num_int_insts 451046619 # number of integer instructions +system.cpu0.num_fp_insts 435772 # number of float instructions +system.cpu0.num_int_register_reads 653989680 # number of times the integer registers were read +system.cpu0.num_int_register_writes 357583746 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 703407 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 366712 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 108509856 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 108205607 # number of times the CC registers were written +system.cpu0.num_mem_refs 149883436 # number of memory refs +system.cpu0.num_load_insts 78604497 # Number of load instructions +system.cpu0.num_store_insts 71278939 # Number of store instructions +system.cpu0.num_idle_cycles 50264779959.264511 # Number of idle cycles +system.cpu0.num_busy_cycles 1535287995.735491 # Number of busy cycles +system.cpu0.not_idle_fraction 0.029639 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.970361 # Percentage of idle cycles +system.cpu0.Branches 93191056 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 339970284 69.23% 69.23% # Class of executed instruction +system.cpu0.op_class::IntMult 1088528 0.22% 69.46% # Class of executed instruction +system.cpu0.op_class::IntDiv 48838 0.01% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 4 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 11 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 16 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 53987 0.01% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::MemRead 78604497 16.01% 85.48% # Class of executed instruction +system.cpu0.op_class::MemWrite 71278939 14.52% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 486402581 # Class of executed instruction -system.cpu0.dcache.tags.replacements 9229396 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.942744 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 287404842 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 9229908 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 31.138430 # Average number of references to valid blocks. +system.cpu0.op_class::total 491045105 # Class of executed instruction +system.cpu0.dcache.tags.replacements 9348690 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.942765 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 290545917 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 9349202 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 31.077082 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 5830459500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 300.933674 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 211.009070 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.587761 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.412127 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 239.060392 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 272.882373 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.466915 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.532973 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 93 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1196218197 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1196218197 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 73007967 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 72737993 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 145745960 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 67086341 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 66998346 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 134084687 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 184406 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 186200 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 370606 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 162812 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 166437 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 329249 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1644610 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1632284 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3276894 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1785360 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1770652 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3556012 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 140094308 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 139736339 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 279830647 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 140278714 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 139922539 # number of overall hits -system.cpu0.dcache.overall_hits::total 280201253 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2418380 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 2397518 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 4815898 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 985807 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 975481 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1961288 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 555377 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 547969 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1103346 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 614035 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 608349 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1222384 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 141557 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 139184 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 280741 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 1209380446 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1209380446 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 73565050 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 73675214 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 147240264 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 67654945 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 67959241 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 135614186 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 188452 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 185421 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 373873 # 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number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6509639500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5907601500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12417241000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032157 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031714 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031935 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014579 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014038 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014308 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.753572 # 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mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023559 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023428 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023494 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027282 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027112 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027197 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15904.442617 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15934.299038 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15919.310409 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32115.607859 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32559.916812 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32336.788080 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18849.576229 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18492.015536 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18671.980987 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58245.660264 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 59610.038810 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 58924.676288 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13717.297157 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13911.385713 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13813.374144 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023815 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023312 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023563 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027669 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026952 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027310 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16118.940424 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15946.282062 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16033.164972 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32918.787684 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34477.794942 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33685.100619 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18503.015914 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19184.461278 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18834.300950 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 38122.623742 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 38839.284209 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 38477.705303 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13901.900698 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13638.545843 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13765.684553 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 79000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 80000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20576.323947 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20723.314158 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20649.514438 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20333.037491 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20410.279557 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20371.484963 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182662.807613 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185198.901291 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183957.344214 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 178957.979423 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189873.447525 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184459.592963 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 180798.124398 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 187521.613875 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184208.494667 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20999.900600 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21250.421449 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21123.977990 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20640.729941 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20962.410389 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20799.635193 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185555.072633 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182271.629536 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183941.505459 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182713.501647 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 186495.997159 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184451.526299 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184090.933514 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 184313.038188 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184196.534793 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 13374068 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.782255 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 813470115 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 13374580 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 60.822105 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 61705740500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 283.742263 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 228.039992 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.554184 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.445391 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999575 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 13311280 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.820918 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 822940675 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 13311792 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 61.820428 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 49369795500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 242.457113 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 269.363804 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.473549 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.526101 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999650 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 217 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 840219285 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 840219285 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 407282786 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 406187329 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 813470115 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 407282786 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 406187329 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 813470115 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 407282786 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 406187329 # number of overall hits -system.cpu0.icache.overall_hits::total 813470115 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6706453 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 6668132 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 13374585 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6706453 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 6668132 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 13374585 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6706453 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 6668132 # number of overall misses -system.cpu0.icache.overall_misses::total 13374585 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 91505309500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 91196930000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 182702239500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 91505309500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 91196930000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 182702239500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 91505309500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 91196930000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 182702239500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 413989239 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 412855461 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 826844700 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 413989239 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 412855461 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 826844700 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 413989239 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 412855461 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 826844700 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016200 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016151 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.016175 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016200 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016151 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.016175 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016200 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016151 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.016175 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13644.367522 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13676.533398 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13660.404379 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13644.367522 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13676.533398 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13660.404379 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13644.367522 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13676.533398 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13660.404379 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 849564269 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 849564269 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 411229460 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 411711215 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 822940675 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 411229460 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 411711215 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 822940675 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 411229460 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 411711215 # number of overall hits +system.cpu0.icache.overall_hits::total 822940675 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6677414 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 6634383 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 13311797 # 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number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 836252472 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015978 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015859 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.015918 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015978 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015859 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.015918 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015978 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015859 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.015918 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13670.540197 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13679.028329 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13674.770544 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13670.540197 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13679.028329 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13674.770544 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13670.540197 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13679.028329 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13674.770544 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -996,56 +997,56 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 13374068 # number of writebacks -system.cpu0.icache.writebacks::total 13374068 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6706453 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 6668132 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 13374585 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6706453 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 6668132 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 13374585 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6706453 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 6668132 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 13374585 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 13311280 # number of writebacks +system.cpu0.icache.writebacks::total 13311280 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6677414 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 6634383 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 13311797 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6677414 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 6634383 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 13311797 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6677414 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 6634383 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 13311797 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 22062 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 21063 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 22062 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 21063 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 84798856500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 84528798000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 169327654500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 84798856500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 84528798000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 169327654500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 84798856500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 84528798000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 169327654500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 84606442500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 84117530000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 168723972500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 84606442500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 84117530000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 168723972500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 84606442500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 84117530000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 168723972500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780591500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2656208000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5436799500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2780591500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 2656208000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 5436799500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016200 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016151 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016175 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016200 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016151 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016175 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016200 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016151 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016175 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12644.367522 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12676.533398 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12660.404379 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12644.367522 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12676.533398 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12660.404379 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12644.367522 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12676.533398 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12660.404379 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015978 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015859 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015918 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015978 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015859 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.015918 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015978 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015859 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.015918 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12670.540197 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12679.028329 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12674.770544 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12670.540197 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12679.028329 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12674.770544 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12670.540197 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12679.028329 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12674.770544 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126035.332245 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126107.771922 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.713043 # average ReadReq mshr uncacheable latency @@ -1082,70 +1083,68 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 117928 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 117928 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 18037 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85683 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 6 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 117922 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 117922 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 117922 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 103726 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 24721.569327 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21421.072660 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15374.016898 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 68517 66.06% 66.06% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 34673 33.43% 99.48% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 1 0.00% 99.48% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 7 0.01% 99.49% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 395 0.38% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 59 0.06% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 7 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 7 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 26 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 7 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 18 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 103726 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 7196110108 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.793869 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.404526 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1483343204 20.61% 20.61% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 5712766904 79.39% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 7196110108 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 85684 82.61% 82.61% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 18037 17.39% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 103721 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 117928 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 116402 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 116402 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17438 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 84735 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 8 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 116394 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.103098 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 35.173529 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-1023 116393 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::11264-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 116394 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 102181 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 25297.388947 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21878.077952 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 16308.937968 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 101549 99.38% 99.38% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2 0.00% 99.38% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 548 0.54% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 11 0.01% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 41 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 2 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 24 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 102181 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 344855740 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean -3.415840 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1522827704 441.58% 441.58% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -1177971964 -341.58% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 344855740 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 84735 82.93% 82.93% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 17438 17.07% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 102173 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 116402 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 117928 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 103721 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 116402 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 102173 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 103721 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 221649 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 102173 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 218575 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 77658339 # DTB read hits -system.cpu1.dtb.read_misses 91087 # DTB read misses -system.cpu1.dtb.write_hits 70545022 # DTB write hits -system.cpu1.dtb.write_misses 26841 # DTB write misses -system.cpu1.dtb.flush_tlb 51774 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 78662844 # DTB read hits +system.cpu1.dtb.read_misses 89684 # DTB read misses +system.cpu1.dtb.write_hits 71537174 # DTB write hits +system.cpu1.dtb.write_misses 26718 # DTB write misses +system.cpu1.dtb.flush_tlb 51800 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 19088 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 488 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 67576 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 18845 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 504 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 67247 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4039 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 3767 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9302 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 77749426 # DTB read accesses -system.cpu1.dtb.write_accesses 70571863 # DTB write accesses +system.cpu1.dtb.perms_faults 9113 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 78752528 # DTB read accesses +system.cpu1.dtb.write_accesses 71563892 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 148203361 # DTB hits -system.cpu1.dtb.misses 117928 # DTB misses -system.cpu1.dtb.accesses 148321289 # DTB accesses +system.cpu1.dtb.hits 150200018 # DTB hits +system.cpu1.dtb.misses 116402 # DTB misses +system.cpu1.dtb.accesses 150316420 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1175,126 +1174,127 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 75461 # Table walker walks requested -system.cpu1.itb.walker.walksLong 75461 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4165 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 66112 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 75461 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 75461 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 75461 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 70277 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 28243.080951 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 25107.153761 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18108.319299 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 69604 99.04% 99.04% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 2 0.00% 99.05% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 599 0.85% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 10 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 30 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 11 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 15 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 70277 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 74223 # Table walker walks requested +system.cpu1.itb.walker.walksLong 74223 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4163 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 64958 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 74223 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 74223 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 74223 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 69121 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 28935.417601 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 25541.870805 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 19930.697059 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 68364 98.90% 98.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 4 0.01% 98.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 655 0.95% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 17 0.02% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 38 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 18 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 69121 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1449734704 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1449734704 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1449734704 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 66112 94.07% 94.07% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 4165 5.93% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 70277 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 64958 93.98% 93.98% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 4163 6.02% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 69121 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 75461 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 75461 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 74223 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 74223 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 70277 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 70277 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 145738 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 412855461 # ITB inst hits -system.cpu1.itb.inst_misses 75461 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 69121 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 69121 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 143344 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 418345598 # ITB inst hits +system.cpu1.itb.inst_misses 74223 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 51774 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 51800 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 19088 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 488 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 50522 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 18845 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 504 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 49961 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 412930922 # ITB inst accesses -system.cpu1.itb.hits 412855461 # DTB hits -system.cpu1.itb.misses 75461 # DTB misses -system.cpu1.itb.accesses 412930922 # DTB accesses -system.cpu1.numCycles 51771053820 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 418419821 # ITB inst accesses +system.cpu1.itb.hits 418345598 # DTB hits +system.cpu1.itb.misses 74223 # DTB misses +system.cpu1.itb.accesses 418419821 # DTB accesses +system.cpu1.numCycles 51798396348 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 412596709 # Number of instructions committed -system.cpu1.committedOps 484960221 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 445873459 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 452061 # Number of float alu accesses -system.cpu1.num_func_calls 24841157 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 62479389 # number of instructions that are conditional controls -system.cpu1.num_int_insts 445873459 # number of integer instructions -system.cpu1.num_fp_insts 452061 # number of float instructions -system.cpu1.num_int_register_reads 645239510 # number of times the integer registers were read -system.cpu1.num_int_register_writes 353339457 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 727891 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 384564 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 106622832 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 106320597 # number of times the CC registers were written -system.cpu1.num_mem_refs 148192340 # number of memory refs -system.cpu1.num_load_insts 77653796 # Number of load instructions -system.cpu1.num_store_insts 70538544 # Number of store instructions -system.cpu1.num_idle_cycles 50233192566.855270 # Number of idle cycles -system.cpu1.num_busy_cycles 1537861253.144726 # Number of busy cycles -system.cpu1.not_idle_fraction 0.029705 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.970295 # Percentage of idle cycles -system.cpu1.Branches 92059897 # Number of branches fetched -system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 335900158 69.22% 69.22% # Class of executed instruction -system.cpu1.op_class::IntMult 1042632 0.21% 69.44% # Class of executed instruction -system.cpu1.op_class::IntDiv 47706 0.01% 69.45% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 1 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 57197 0.01% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::MemRead 77653796 16.00% 85.46% # Class of executed instruction -system.cpu1.op_class::MemWrite 70538544 14.54% 100.00% # Class of executed instruction +system.cpu1.committedInsts 418091469 # Number of instructions committed +system.cpu1.committedOps 491344077 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 451749452 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 464131 # Number of float alu accesses +system.cpu1.num_func_calls 25120971 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 63413635 # number of instructions that are conditional controls +system.cpu1.num_int_insts 451749452 # number of integer instructions +system.cpu1.num_fp_insts 464131 # number of float instructions +system.cpu1.num_int_register_reads 653305653 # number of times the integer registers were read +system.cpu1.num_int_register_writes 357922313 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 749406 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 392664 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 108141039 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 107840924 # number of times the CC registers were written +system.cpu1.num_mem_refs 150187574 # number of memory refs +system.cpu1.num_load_insts 78657446 # Number of load instructions +system.cpu1.num_store_insts 71530128 # Number of store instructions +system.cpu1.num_idle_cycles 50264307367.295029 # Number of idle cycles +system.cpu1.num_busy_cycles 1534088980.704967 # Number of busy cycles +system.cpu1.not_idle_fraction 0.029617 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.970383 # Percentage of idle cycles +system.cpu1.Branches 93317418 # Number of branches fetched +system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 340283943 69.22% 69.22% # Class of executed instruction +system.cpu1.op_class::IntMult 1041145 0.21% 69.43% # Class of executed instruction +system.cpu1.op_class::IntDiv 48269 0.01% 69.44% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 4 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 2 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 5 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 58327 0.01% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::MemRead 78657446 16.00% 85.45% # Class of executed instruction +system.cpu1.op_class::MemWrite 71530128 14.55% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 485240035 # Class of executed instruction -system.iobus.trans_dist::ReadReq 40316 # Transaction distribution -system.iobus.trans_dist::ReadResp 40316 # Transaction distribution +system.cpu1.op_class::total 491619269 # Class of executed instruction +system.iobus.trans_dist::ReadReq 40338 # Transaction distribution +system.iobus.trans_dist::ReadResp 40338 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1311,11 +1311,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230990 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230990 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231034 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231034 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353774 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353818 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1330,20 +1330,20 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334568 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42146500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492488 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42145500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 323000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1353,77 +1353,77 @@ system.iobus.reqLayer14.occupancy 11000 # La system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25708000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25719500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38602000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38601500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 566763189 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 566847151 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147750000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147794000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115482 # number of replacements -system.iocache.tags.tagsinuse 10.442873 # Cycle average of tags in use +system.iocache.tags.replacements 115499 # number of replacements +system.iocache.tags.tagsinuse 10.451110 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115498 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115515 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13183784926000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 5.854402 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 4.588472 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.365900 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.286779 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.652680 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13171691140000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.508460 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.942650 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219279 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433916 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653194 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039812 # Number of tag accesses -system.iocache.tags.data_accesses 1039812 # Number of data accesses +system.iocache.tags.tag_accesses 1040010 # Number of tag accesses +system.iocache.tags.data_accesses 1040010 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8831 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8868 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8853 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8890 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8831 # number of demand (read+write) misses -system.iocache.demand_misses::total 8871 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8853 # number of demand (read+write) misses +system.iocache.demand_misses::total 8893 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8831 # number of overall misses -system.iocache.overall_misses::total 8871 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1624550168 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1629620168 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8853 # number of overall misses +system.iocache.overall_misses::total 8893 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1618419141 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1623489641 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13409547021 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13409547021 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1624550168 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1629971168 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1624550168 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1629971168 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13411968510 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13411968510 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1618419141 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1623840641 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1618419141 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1623840641 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8831 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8868 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8853 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8890 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8831 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8871 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8853 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8893 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8831 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8871 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8853 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8893 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1437,55 +1437,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 183959.932963 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 183764.114569 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 182810.249746 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 182619.757143 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125717.646263 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125717.646263 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 183959.932963 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183741.536242 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 183959.932963 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183741.536242 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32143 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125740.348290 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125740.348290 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 182810.249746 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 182597.620713 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 182810.249746 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 182597.620713 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31642 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3321 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3353 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.678711 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.436922 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8831 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8868 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8853 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8890 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8831 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8871 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8853 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8893 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8831 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8871 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1183000168 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1186220168 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8853 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8893 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1175769141 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1178989641 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8071216147 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8071216147 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1183000168 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1186421168 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1183000168 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1186421168 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073599158 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8073599158 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1175769141 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1179190641 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1175769141 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1179190641 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1499,308 +1499,308 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133959.932963 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 133764.114569 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132810.249746 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 132619.757143 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75669.543117 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75669.543117 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 133959.932963 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 133741.536242 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 133959.932963 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 133741.536242 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.884403 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.884403 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 132810.249746 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 132597.620713 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 132810.249746 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 132597.620713 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 989396 # number of replacements -system.l2c.tags.tagsinuse 65299.098652 # Cycle average of tags in use -system.l2c.tags.total_refs 41673385 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1051747 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 39.623013 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 56075802500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37757.667550 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 108.548487 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 160.943912 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3976.741383 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9619.817220 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 97.192514 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 146.379867 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4603.768547 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 8828.039172 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.576136 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001656 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002456 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.060680 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.146787 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001483 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.002234 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.070248 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.134705 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996385 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 252 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62099 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 252 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2415 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5492 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53743 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.947556 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 372018005 # 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number of overall hits -system.l2c.overall_hits::cpu1.inst 6632136 # number of overall hits -system.l2c.overall_hits::cpu1.data 3721952 # number of overall hits -system.l2c.overall_hits::total 21507859 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1093 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1173 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 925 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1016 # number of ReadReq misses -system.l2c.ReadReq_misses::total 4207 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 16132 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 16422 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 32554 # number of UpgradeReq misses +system.l2c.tags.replacements 1026360 # number of replacements +system.l2c.tags.tagsinuse 65258.201118 # Cycle average of tags in use +system.l2c.tags.total_refs 41749797 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1088957 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 38.339252 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 12386120500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 37949.534950 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 104.286779 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 159.329733 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4753.488207 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9126.220322 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 118.614839 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 183.809686 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3411.314898 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 9451.601704 # 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Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 220 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2461 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5447 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54048 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.951797 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 372663502 # Number of tag accesses +system.l2c.tags.data_accesses 372663502 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 212373 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 162936 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 207984 # 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number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 13240229 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 3014297 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 2962809 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 5977106 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 376322 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 363170 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 739492 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 212373 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 162936 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 6641663 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 3830064 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 207984 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 157286 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 6598566 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 3738871 # number of demand (read+write) hits +system.l2c.demand_hits::total 21549743 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 212373 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 162936 # number of overall hits +system.l2c.overall_hits::cpu0.inst 6641663 # number of overall hits +system.l2c.overall_hits::cpu0.data 3830064 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 207984 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 157286 # number of overall hits +system.l2c.overall_hits::cpu1.inst 6598566 # number of overall hits +system.l2c.overall_hits::cpu1.data 3738871 # number of overall hits +system.l2c.overall_hits::total 21549743 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 1170 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1257 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121527.800696 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 121656.292566 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 121081.323173 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121211.197433 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 121147.547713 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 122043.131661 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122573.833654 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122308.727364 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 123302.386859 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 123549.783139 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 123424.211853 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 67648.903449 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 67667.222454 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 67658.102611 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125328.205128 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128312.251392 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122043.131661 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121991.405875 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125575.859179 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 129240.345111 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122573.833654 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122130.138582 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 122127.735764 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125328.205128 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128312.251392 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122043.131661 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121991.405875 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125575.859179 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 129240.345111 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122573.833654 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122130.138582 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 122127.735764 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170140.289732 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173032.961904 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172675.851645 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138953.224862 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 167457.710252 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178373.064924 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172959.266621 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169747.690636 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138947.871247 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171213.254665 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174995.577507 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172951.199976 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 168790.116209 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 172095.345154 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 175506.712293 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 149323.449318 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 172283.710845 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 149317.320740 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 76825 # Transaction distribution -system.membus.trans_dist::ReadResp 376385 # Transaction distribution -system.membus.trans_dist::WriteReq 33707 # Transaction distribution -system.membus.trans_dist::WriteResp 33707 # Transaction distribution -system.membus.trans_dist::WritebackDirty 947057 # Transaction distribution -system.membus.trans_dist::CleanEvict 156816 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33121 # Transaction distribution +system.membus.trans_dist::ReadReq 76829 # Transaction distribution +system.membus.trans_dist::ReadResp 386652 # Transaction distribution +system.membus.trans_dist::WriteReq 33709 # Transaction distribution +system.membus.trans_dist::WriteResp 33709 # Transaction distribution +system.membus.trans_dist::WritebackDirty 978778 # Transaction distribution +system.membus.trans_dist::CleanEvict 162070 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33685 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 788585 # Transaction distribution -system.membus.trans_dist::ReadExResp 788585 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 299560 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution +system.membus.trans_dist::ReadExReq 334406 # Transaction distribution +system.membus.trans_dist::ReadExResp 334406 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 309823 # Transaction distribution +system.membus.trans_dist::InvalidateReq 587971 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6924 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3270790 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3400476 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3637544 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6936 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2901743 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3031441 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237241 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237241 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3268682 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 123012320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 123182134 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7211648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7211648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 130393782 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3477 # Total snoops (count) -system.membus.snoop_fanout::samples 2442384 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 96630432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 96800270 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7220224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7220224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 104020494 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3365 # Total snoops (count) +system.membus.snoop_fanout::samples 2517308 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2442384 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2517308 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2442384 # Request fanout histogram -system.membus.reqLayer0.occupancy 106884000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2517308 # Request fanout histogram +system.membus.reqLayer0.occupancy 106894000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5641500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5659000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 6231197843 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 6490935886 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5914461286 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3578419285 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44673503 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44788681 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2124,61 +2120,61 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 45780480 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 23175972 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1745 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2220 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2220 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 45897959 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 23236926 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1749 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2692 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2692 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 1179802 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 20664144 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 8179867 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 13374068 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2154454 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 41435 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 1189053 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 20703336 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33709 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33709 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 8290323 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 13311280 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2200261 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 42068 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 41437 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1898604 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1898604 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 13374585 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 6117809 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1329048 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1222384 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 40209488 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27907755 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 753930 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1075310 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 69946483 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1712086292 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 975622370 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2512480 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3297624 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2693518766 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1597993 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 25079917 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021333 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.144493 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 42070 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1926802 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1926802 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 13311797 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6210524 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1327470 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1220806 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 40021124 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 28266989 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 766613 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1091027 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 70145753 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1704049428 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 988401530 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2581568 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3381760 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2698414286 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1625114 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 25183319 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021416 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.144767 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 24544878 97.87% 97.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 535039 2.13% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 24643989 97.86% 97.86% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 539330 2.14% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 25079917 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 43855145000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 25183319 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 43932563500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1530888 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1579898 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 20105002500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 20010820500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 12693791976 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 12874657982 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 439870000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 443917000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 663107000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 668307000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |